| blob | c8aae1f128effb5f7984c190bd17d2e639fe1f49 |
1 /*
2 * This file is part of Cleanflight and Betaflight.
3 *
4 * Cleanflight and Betaflight are free software. You can redistribute
5 * this software and/or modify this software under the terms of the
6 * GNU General Public License as published by the Free Software
7 * Foundation, either version 3 of the License, or (at your option)
8 * any later version.
9 *
10 * Cleanflight and Betaflight are distributed in the hope that they
11 * will be useful, but WITHOUT ANY WARRANTY; without even the implied
12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 * See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this software.
17 *
18 * If not, see <http://www.gnu.org/licenses/>.
19 */
21 #pragma once
26 // allow conditional definition of DMA related members
27 #if defined(USE_TIMER_DMA)
28 # define DEF_TIM_DMA_COND(...) __VA_ARGS__
29 #else
30 # define DEF_TIM_DMA_COND(...)
31 #endif
33 #if defined(USE_TIMER_MGMT)
34 #define TIMER_GET_IO_TAG(pin) DEFIO_TAG_E(pin)
35 #else
36 #define TIMER_GET_IO_TAG(pin) DEFIO_TAG(pin)
37 #endif
39 // map to base channel (strip N from channel); works only when channel N exists
40 #define DEF_TIM_TCH2BTCH(timch) CONCAT(B, timch)
41 #define BTCH_TIM1_CH1N BTCH_TIM1_CH1
42 #define BTCH_TIM1_CH2N BTCH_TIM1_CH2
43 #define BTCH_TIM1_CH3N BTCH_TIM1_CH3
44 #ifdef STM32G4
45 #define BTCH_TIM1_CH4N BTCH_TIM1_CH4
46 #endif
48 #define BTCH_TIM8_CH1N BTCH_TIM8_CH1
49 #define BTCH_TIM8_CH2N BTCH_TIM8_CH2
50 #define BTCH_TIM8_CH3N BTCH_TIM8_CH3
51 #ifdef STM32G4
52 #define BTCH_TIM8_CH4N BTCH_TIM8_CH4
53 #endif
55 #define BTCH_TIM20_CH1N BTCH_TIM20_CH1
56 #define BTCH_TIM20_CH2N BTCH_TIM20_CH2
57 #define BTCH_TIM20_CH3N BTCH_TIM20_CH3
59 #define BTCH_TIM13_CH1N BTCH_TIM13_CH1
60 #define BTCH_TIM14_CH1N BTCH_TIM14_CH1
61 #define BTCH_TIM15_CH1N BTCH_TIM15_CH1
62 #define BTCH_TIM16_CH1N BTCH_TIM16_CH1
63 #define BTCH_TIM17_CH1N BTCH_TIM17_CH1
65 // channel table D(chan_n, n_type)
66 #define DEF_TIM_CH_GET(ch) CONCAT2(DEF_TIM_CH__, ch)
67 #define DEF_TIM_CH__CH_CH1 D(1, 0)
68 #define DEF_TIM_CH__CH_CH2 D(2, 0)
69 #define DEF_TIM_CH__CH_CH3 D(3, 0)
70 #define DEF_TIM_CH__CH_CH4 D(4, 0)
71 #define DEF_TIM_CH__CH_CH1N D(1, 1)
72 #define DEF_TIM_CH__CH_CH2N D(2, 1)
73 #define DEF_TIM_CH__CH_CH3N D(3, 1)
74 #ifdef STM32G4
75 #define DEF_TIM_CH__CH_CH4N D(4, 1)
76 #endif
78 // timer table D(tim_n)
79 #define DEF_TIM_TIM_GET(tim) CONCAT2(DEF_TIM_TIM__, tim)
80 #define DEF_TIM_TIM__TIM_TIM1 D(1)
81 #define DEF_TIM_TIM__TIM_TIM2 D(2)
82 #define DEF_TIM_TIM__TIM_TIM3 D(3)
83 #define DEF_TIM_TIM__TIM_TIM4 D(4)
84 #define DEF_TIM_TIM__TIM_TIM5 D(5)
85 #define DEF_TIM_TIM__TIM_TIM6 D(6)
86 #define DEF_TIM_TIM__TIM_TIM7 D(7)
87 #define DEF_TIM_TIM__TIM_TIM8 D(8)
88 #define DEF_TIM_TIM__TIM_TIM9 D(9)
89 #define DEF_TIM_TIM__TIM_TIM10 D(10)
90 #define DEF_TIM_TIM__TIM_TIM11 D(11)
91 #define DEF_TIM_TIM__TIM_TIM12 D(12)
92 #define DEF_TIM_TIM__TIM_TIM13 D(13)
93 #define DEF_TIM_TIM__TIM_TIM14 D(14)
94 #define DEF_TIM_TIM__TIM_TIM15 D(15)
95 #define DEF_TIM_TIM__TIM_TIM16 D(16)
96 #define DEF_TIM_TIM__TIM_TIM17 D(17)
97 #define DEF_TIM_TIM__TIM_TIM18 D(18)
98 #define DEF_TIM_TIM__TIM_TIM19 D(19)
99 #define DEF_TIM_TIM__TIM_TIM20 D(20)
100 #define DEF_TIM_TIM__TIM_TIM21 D(21)
101 #define DEF_TIM_TIM__TIM_TIM22 D(22)
103 // get record from DMA table
104 // DMA table is identical for all targets for consistency, only variant 0 is defined on F1,F3
105 // DMA table entry for TIMx Channel y, with two variants:
106 // #define DEF_TIM_DMA__BTCH_TIMx_CHy D(var0),D(var1)
107 // Parameters in D(...) are target-specific
108 // DMA table for channel without DMA
109 // #define DEF_TIM_DMA__BTCH_TIMx_CHy NONE
110 // N channels are converted to corresponding base channel first
112 // Create accessor macro and call it with entry from table
113 // DMA_VARIANT_MISSING are used to satisfy variable arguments (-Wpedantic) and to get better error message (undefined symbol instead of preprocessor error)
114 #define DEF_TIM_DMA_GET(variant, timch) PP_CALL(CONCAT(DEF_TIM_DMA_GET_VARIANT__, variant), CONCAT(DEF_TIM_DMA__, DEF_TIM_TCH2BTCH(timch)), DMA_VARIANT_MISSING, DMA_VARIANT_MISSING, ERROR)
116 #define DEF_TIM_DMA_GET_VARIANT__0(_0, ...) _0
117 #define DEF_TIM_DMA_GET_VARIANT__1(_0, _1, ...) _1
118 #define DEF_TIM_DMA_GET_VARIANT__2(_0, _1, _2, ...) _2
119 #define DEF_TIM_DMA_GET_VARIANT__3(_0, _1, _2, _3, ...) _3
120 #define DEF_TIM_DMA_GET_VARIANT__4(_0, _1, _2, _3, _4, ...) _4
121 #define DEF_TIM_DMA_GET_VARIANT__5(_0, _1, _2, _3, _4, _5, ...) _5
122 #define DEF_TIM_DMA_GET_VARIANT__6(_0, _1, _2, _3, _4, _5, _6, ...) _6
123 #define DEF_TIM_DMA_GET_VARIANT__7(_0, _1, _2, _3, _4, _5, _6, _7, ...) _7
124 #define DEF_TIM_DMA_GET_VARIANT__8(_0, _1, _2, _3, _4, _5, _6, _7, _8, ...) _8
125 #define DEF_TIM_DMA_GET_VARIANT__9(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, ...) _9
126 #define DEF_TIM_DMA_GET_VARIANT__10(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, ...) _10
127 #define DEF_TIM_DMA_GET_VARIANT__11(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, ...) _11
128 #define DEF_TIM_DMA_GET_VARIANT__12(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, ...) _12
129 #define DEF_TIM_DMA_GET_VARIANT__13(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, ...) _13
130 #define DEF_TIM_DMA_GET_VARIANT__14(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, ...) _14
131 #define DEF_TIM_DMA_GET_VARIANT__15(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, ...) _15
133 // symbolic names for DMA variants
134 #define DMA_VAR0 0
135 #define DMA_VAR1 1
136 #define DMA_VAR2 2
138 // get record from AF table
139 // Parameters in D(...) are target-specific
140 #define DEF_TIM_AF_GET(timch, pin) CONCAT4(DEF_TIM_AF__, pin, __, timch)
142 // define output type (N-channel)
143 #define DEF_TIM_OUTPUT(ch) CONCAT(DEF_TIM_OUTPUT__, DEF_TIM_CH_GET(ch))
144 #define DEF_TIM_OUTPUT__D(chan_n, n_channel) PP_IIF(n_channel, TIMER_OUTPUT_N_CHANNEL, TIMER_OUTPUT_NONE)
146 #if defined(STM32F4)
148 #define DEF_TIM(tim, chan, pin, out, dmaopt) { \
149 tim, \
150 TIMER_GET_IO_TAG(pin), \
151 DEF_TIM_CHANNEL(CH_ ## chan), \
152 (DEF_TIM_OUTPUT(CH_ ## chan) | out), \
153 DEF_TIM_AF(TIM_ ## tim) \
155 DEF_TIM_DMA_STREAM(dmaopt, TCH_## tim ## _ ## chan), \
156 DEF_TIM_DMA_CHANNEL(dmaopt, TCH_## tim ## _ ## chan) \
157 ) \
159 DEF_TIM_DMA_STREAM(0, TCH_## tim ## _UP), \
160 DEF_TIM_DMA_CHANNEL(0, TCH_## tim ## _UP), \
161 DEF_TIM_DMA_HANDLER(0, TCH_## tim ## _UP) \
162 ) \
163 } \
164 /**/
166 #define DEF_TIM_CHANNEL(ch) CONCAT(DEF_TIM_CHANNEL__, DEF_TIM_CH_GET(ch))
167 #define DEF_TIM_CHANNEL__D(chan_n, n_channel) TIM_Channel_ ## chan_n
169 #define DEF_TIM_AF(tim) CONCAT(DEF_TIM_AF__, DEF_TIM_TIM_GET(tim))
170 #define DEF_TIM_AF__D(tim_n) GPIO_AF_TIM ## tim_n
172 #define DEF_TIM_DMA_CHANNEL(variant, timch) \
173 CONCAT(DEF_TIM_DMA_CHANNEL__, DEF_TIM_DMA_GET(variant, timch))
174 #define DEF_TIM_DMA_CHANNEL__D(dma_n, stream_n, chan_n) DMA_Channel_ ## chan_n
175 #define DEF_TIM_DMA_CHANNEL__NONE DMA_Channel_0
177 #define DEF_TIM_DMA_STREAM(variant, timch) \
178 CONCAT(DEF_TIM_DMA_STREAM__, DEF_TIM_DMA_GET(variant, timch))
179 #define DEF_TIM_DMA_STREAM__D(dma_n, stream_n, chan_n) (dmaResource_t *)DMA ## dma_n ## _Stream ## stream_n
180 #define DEF_TIM_DMA_STREAM__NONE NULL
182 #define DEF_TIM_DMA_HANDLER(variant, timch) \
183 CONCAT(DEF_TIM_DMA_HANDLER__, DEF_TIM_DMA_GET(variant, timch))
184 #define DEF_TIM_DMA_HANDLER__D(dma_n, stream_n, chan_n) DMA ## dma_n ## _ST ## stream_n ## _HANDLER
185 #define DEF_TIM_DMA_HANDLER__NONE 0
187 /* F4 Stream Mappings */
188 // D(DMAx, Stream, Channel)
189 #define DEF_TIM_DMA__BTCH_TIM1_CH1 D(2, 6, 0),D(2, 1, 6),D(2, 3, 6)
190 #define DEF_TIM_DMA__BTCH_TIM1_CH2 D(2, 6, 0),D(2, 2, 6)
191 #define DEF_TIM_DMA__BTCH_TIM1_CH3 D(2, 6, 0),D(2, 6, 6)
192 #define DEF_TIM_DMA__BTCH_TIM1_CH4 D(2, 4, 6)
194 #define DEF_TIM_DMA__BTCH_TIM2_CH1 D(1, 5, 3)
195 #define DEF_TIM_DMA__BTCH_TIM2_CH2 D(1, 6, 3)
196 #define DEF_TIM_DMA__BTCH_TIM2_CH3 D(1, 1, 3)
197 #define DEF_TIM_DMA__BTCH_TIM2_CH4 D(1, 7, 3),D(1, 6, 3)
199 #define DEF_TIM_DMA__BTCH_TIM3_CH1 D(1, 4, 5)
200 #define DEF_TIM_DMA__BTCH_TIM3_CH2 D(1, 5, 5)
201 #define DEF_TIM_DMA__BTCH_TIM3_CH3 D(1, 7, 5)
202 #define DEF_TIM_DMA__BTCH_TIM3_CH4 D(1, 2, 5)
204 #define DEF_TIM_DMA__BTCH_TIM4_CH1 D(1, 0, 2)
205 #define DEF_TIM_DMA__BTCH_TIM4_CH2 D(1, 3, 2)
206 #define DEF_TIM_DMA__BTCH_TIM4_CH3 D(1, 7, 2)
208 #define DEF_TIM_DMA__BTCH_TIM5_CH1 D(1, 2, 6)
209 #define DEF_TIM_DMA__BTCH_TIM5_CH2 D(1, 4, 6)
210 #define DEF_TIM_DMA__BTCH_TIM5_CH3 D(1, 0, 6)
211 #define DEF_TIM_DMA__BTCH_TIM5_CH4 D(1, 1, 6),D(1, 3, 6)
213 #define DEF_TIM_DMA__BTCH_TIM8_CH1 D(2, 2, 0),D(2, 2, 7)
214 #define DEF_TIM_DMA__BTCH_TIM8_CH2 D(2, 2, 0),D(2, 3, 7)
215 #define DEF_TIM_DMA__BTCH_TIM8_CH3 D(2, 2, 0),D(2, 4, 7)
216 #define DEF_TIM_DMA__BTCH_TIM8_CH4 D(2, 7, 7)
218 #define DEF_TIM_DMA__BTCH_TIM4_CH4 NONE
220 #define DEF_TIM_DMA__BTCH_TIM9_CH1 NONE
221 #define DEF_TIM_DMA__BTCH_TIM9_CH2 NONE
223 #define DEF_TIM_DMA__BTCH_TIM10_CH1 NONE
225 #define DEF_TIM_DMA__BTCH_TIM11_CH1 NONE
227 #define DEF_TIM_DMA__BTCH_TIM12_CH1 NONE
228 #define DEF_TIM_DMA__BTCH_TIM12_CH2 NONE
230 #define DEF_TIM_DMA__BTCH_TIM13_CH1 NONE
232 #define DEF_TIM_DMA__BTCH_TIM14_CH1 NONE
234 // TIM_UP table
235 #define DEF_TIM_DMA__BTCH_TIM1_UP D(2, 5, 6)
236 #define DEF_TIM_DMA__BTCH_TIM2_UP D(1, 7, 3)
237 #define DEF_TIM_DMA__BTCH_TIM3_UP D(1, 2, 5)
238 #define DEF_TIM_DMA__BTCH_TIM4_UP D(1, 6, 2)
239 #define DEF_TIM_DMA__BTCH_TIM5_UP D(1, 0, 6)
240 #define DEF_TIM_DMA__BTCH_TIM6_UP D(1, 1, 7)
241 #define DEF_TIM_DMA__BTCH_TIM7_UP D(1, 4, 1)
242 #define DEF_TIM_DMA__BTCH_TIM8_UP D(2, 1, 7)
243 #define DEF_TIM_DMA__BTCH_TIM9_UP NONE
244 #define DEF_TIM_DMA__BTCH_TIM10_UP NONE
245 #define DEF_TIM_DMA__BTCH_TIM11_UP NONE
246 #define DEF_TIM_DMA__BTCH_TIM12_UP NONE
247 #define DEF_TIM_DMA__BTCH_TIM13_UP NONE
248 #define DEF_TIM_DMA__BTCH_TIM14_UP NONE
250 #elif defined(STM32F7)
251 #define DEF_TIM(tim, chan, pin, out, dmaopt) { \
252 tim, \
253 TIMER_GET_IO_TAG(pin), \
254 DEF_TIM_CHANNEL(CH_ ## chan), \
255 (DEF_TIM_OUTPUT(CH_ ## chan) | out), \
256 DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
258 DEF_TIM_DMA_STREAM(dmaopt, TCH_## tim ## _ ## chan), \
259 DEF_TIM_DMA_CHANNEL(dmaopt, TCH_## tim ## _ ## chan) \
260 ) \
262 DEF_TIM_DMA_STREAM(0, TCH_## tim ## _UP), \
263 DEF_TIM_DMA_CHANNEL(0, TCH_## tim ## _UP), \
264 DEF_TIM_DMA_HANDLER(0, TCH_## tim ## _UP) \
265 ) \
266 } \
267 /**/
269 #define DEF_TIM_CHANNEL(ch) CONCAT(DEF_TIM_CHANNEL__, DEF_TIM_CH_GET(ch))
270 #define DEF_TIM_CHANNEL__D(chan_n, n_channel) TIM_CHANNEL_ ## chan_n
272 #define DEF_TIM_AF(timch, pin) CONCAT(DEF_TIM_AF__, DEF_TIM_AF_GET(timch, pin))
273 #define DEF_TIM_AF__D(af_n, tim_n) GPIO_AF ## af_n ## _TIM ## tim_n
275 #define DEF_TIM_DMA_CHANNEL(variant, timch) \
276 CONCAT(DEF_TIM_DMA_CHANNEL__, DEF_TIM_DMA_GET(variant, timch))
277 #define DEF_TIM_DMA_CHANNEL__D(dma_n, stream_n, chan_n) DMA_CHANNEL_ ## chan_n
278 #define DEF_TIM_DMA_CHANNEL__NONE DMA_CHANNEL_0
280 #define DEF_TIM_DMA_STREAM(variant, timch) \
281 CONCAT(DEF_TIM_DMA_STREAM__, DEF_TIM_DMA_GET(variant, timch))
282 #define DEF_TIM_DMA_STREAM__D(dma_n, stream_n, chan_n) (dmaResource_t *)DMA ## dma_n ## _Stream ## stream_n
283 #define DEF_TIM_DMA_STREAM__NONE NULL
285 #define DEF_TIM_DMA_HANDLER(variant, timch) \
286 CONCAT(DEF_TIM_DMA_HANDLER__, DEF_TIM_DMA_GET(variant, timch))
287 #define DEF_TIM_DMA_HANDLER__D(dma_n, stream_n, chan_n) DMA ## dma_n ## _ST ## stream_n ## _HANDLER
288 #define DEF_TIM_DMA_HANDLER__NONE 0
290 /* F7 Stream Mappings */
291 // D(DMAx, Stream, Channel)
292 #define DEF_TIM_DMA__BTCH_TIM1_CH1 D(2, 6, 0),D(2, 1, 6),D(2, 3, 6)
293 #define DEF_TIM_DMA__BTCH_TIM1_CH2 D(2, 6, 0),D(2, 2, 6)
294 #define DEF_TIM_DMA__BTCH_TIM1_CH3 D(2, 6, 0),D(2, 6, 6)
295 #define DEF_TIM_DMA__BTCH_TIM1_CH4 D(2, 4, 6)
297 #define DEF_TIM_DMA__BTCH_TIM2_CH1 D(1, 5, 3)
298 #define DEF_TIM_DMA__BTCH_TIM2_CH2 D(1, 6, 3)
299 #define DEF_TIM_DMA__BTCH_TIM2_CH3 D(1, 1, 3)
300 #define DEF_TIM_DMA__BTCH_TIM2_CH4 D(1, 7, 3),D(1, 6, 3)
302 #define DEF_TIM_DMA__BTCH_TIM3_CH1 D(1, 4, 5)
303 #define DEF_TIM_DMA__BTCH_TIM3_CH2 D(1, 5, 5)
304 #define DEF_TIM_DMA__BTCH_TIM3_CH3 D(1, 7, 5)
305 #define DEF_TIM_DMA__BTCH_TIM3_CH4 D(1, 2, 5)
307 #define DEF_TIM_DMA__BTCH_TIM4_CH1 D(1, 0, 2)
308 #define DEF_TIM_DMA__BTCH_TIM4_CH2 D(1, 3, 2)
309 #define DEF_TIM_DMA__BTCH_TIM4_CH3 D(1, 7, 2)
311 #define DEF_TIM_DMA__BTCH_TIM5_CH1 D(1, 2, 6)
312 #define DEF_TIM_DMA__BTCH_TIM5_CH2 D(1, 4, 6)
313 #define DEF_TIM_DMA__BTCH_TIM5_CH3 D(1, 0, 6)
314 #define DEF_TIM_DMA__BTCH_TIM5_CH4 D(1, 1, 6),D(1, 3, 6)
316 #define DEF_TIM_DMA__BTCH_TIM8_CH1 D(2, 2, 0),D(2, 2, 7)
317 #define DEF_TIM_DMA__BTCH_TIM8_CH2 D(2, 2, 0),D(2, 3, 7)
318 #define DEF_TIM_DMA__BTCH_TIM8_CH3 D(2, 2, 0),D(2, 4, 7)
319 #define DEF_TIM_DMA__BTCH_TIM8_CH4 D(2, 7, 7)
321 #define DEF_TIM_DMA__BTCH_TIM4_CH4 NONE
323 #define DEF_TIM_DMA__BTCH_TIM9_CH1 NONE
324 #define DEF_TIM_DMA__BTCH_TIM9_CH2 NONE
326 #define DEF_TIM_DMA__BTCH_TIM10_CH1 NONE
328 #define DEF_TIM_DMA__BTCH_TIM11_CH1 NONE
330 #define DEF_TIM_DMA__BTCH_TIM12_CH1 NONE
331 #define DEF_TIM_DMA__BTCH_TIM12_CH2 NONE
333 #define DEF_TIM_DMA__BTCH_TIM13_CH1 NONE
335 #define DEF_TIM_DMA__BTCH_TIM14_CH1 NONE
337 // TIM_UP table
338 #define DEF_TIM_DMA__BTCH_TIM1_UP D(2, 5, 6)
339 #define DEF_TIM_DMA__BTCH_TIM2_UP D(1, 7, 3)
340 #define DEF_TIM_DMA__BTCH_TIM3_UP D(1, 2, 5)
341 #define DEF_TIM_DMA__BTCH_TIM4_UP D(1, 6, 2)
342 #define DEF_TIM_DMA__BTCH_TIM5_UP D(1, 0, 6)
343 #define DEF_TIM_DMA__BTCH_TIM6_UP D(1, 1, 7)
344 #define DEF_TIM_DMA__BTCH_TIM7_UP D(1, 4, 1)
345 #define DEF_TIM_DMA__BTCH_TIM8_UP D(2, 1, 7)
346 #define DEF_TIM_DMA__BTCH_TIM9_UP NONE
347 #define DEF_TIM_DMA__BTCH_TIM10_UP NONE
348 #define DEF_TIM_DMA__BTCH_TIM11_UP NONE
349 #define DEF_TIM_DMA__BTCH_TIM12_UP NONE
350 #define DEF_TIM_DMA__BTCH_TIM13_UP NONE
351 #define DEF_TIM_DMA__BTCH_TIM14_UP NONE
353 // AF table
355 // NONE
356 #define DEF_TIM_AF__NONE__TCH_TIM1_CH1 D(1, 1)
357 #define DEF_TIM_AF__NONE__TCH_TIM1_CH2 D(1, 1)
358 #define DEF_TIM_AF__NONE__TCH_TIM1_CH3 D(1, 1)
359 #define DEF_TIM_AF__NONE__TCH_TIM1_CH4 D(1, 1)
360 #define DEF_TIM_AF__NONE__TCH_TIM8_CH1 D(3, 8)
361 #define DEF_TIM_AF__NONE__TCH_TIM8_CH2 D(3, 8)
362 #define DEF_TIM_AF__NONE__TCH_TIM8_CH3 D(3, 8)
363 #define DEF_TIM_AF__NONE__TCH_TIM8_CH4 D(3, 8)
365 //PORTA
366 #define DEF_TIM_AF__PA0__TCH_TIM2_CH1 D(1, 2)
367 #define DEF_TIM_AF__PA1__TCH_TIM2_CH2 D(1, 2)
368 #define DEF_TIM_AF__PA2__TCH_TIM2_CH3 D(1, 2)
369 #define DEF_TIM_AF__PA3__TCH_TIM2_CH4 D(1, 2)
370 #define DEF_TIM_AF__PA5__TCH_TIM2_CH1 D(1, 2)
371 #define DEF_TIM_AF__PA7__TCH_TIM1_CH1N D(1, 1)
372 #define DEF_TIM_AF__PA8__TCH_TIM1_CH1 D(1, 1)
373 #define DEF_TIM_AF__PA9__TCH_TIM1_CH2 D(1, 1)
374 #define DEF_TIM_AF__PA10__TCH_TIM1_CH3 D(1, 1)
375 #define DEF_TIM_AF__PA11__TCH_TIM1_CH1N D(1, 1)
376 #define DEF_TIM_AF__PA15__TCH_TIM2_CH1 D(1, 2)
378 #define DEF_TIM_AF__PA0__TCH_TIM5_CH1 D(2, 5)
379 #define DEF_TIM_AF__PA1__TCH_TIM5_CH2 D(2, 5)
380 #define DEF_TIM_AF__PA2__TCH_TIM5_CH3 D(2, 5)
381 #define DEF_TIM_AF__PA3__TCH_TIM5_CH4 D(2, 5)
382 #define DEF_TIM_AF__PA6__TCH_TIM3_CH1 D(2, 3)
383 #define DEF_TIM_AF__PA7__TCH_TIM3_CH2 D(2, 3)
385 #define DEF_TIM_AF__PA2__TCH_TIM9_CH1 D(3, 9)
386 #define DEF_TIM_AF__PA3__TCH_TIM9_CH2 D(3, 9)
387 #define DEF_TIM_AF__PA5__TCH_TIM8_CH1N D(3, 8)
388 #define DEF_TIM_AF__PA7__TCH_TIM8_CH1N D(3, 8)
390 #define DEF_TIM_AF__PA6__TCH_TIM13_CH1 D(9, 13)
391 #define DEF_TIM_AF__PA7__TCH_TIM14_CH1 D(9, 14)
393 //PORTB
394 #define DEF_TIM_AF__PB0__TCH_TIM1_CH2N D(1, 1)
395 #define DEF_TIM_AF__PB1__TCH_TIM1_CH3N D(1, 1)
396 #define DEF_TIM_AF__PB3__TCH_TIM2_CH2 D(1, 2)
397 #define DEF_TIM_AF__PB10__TCH_TIM2_CH3 D(1, 2)
398 #define DEF_TIM_AF__PB11__TCH_TIM2_CH4 D(1, 2)
399 #define DEF_TIM_AF__PB13__TCH_TIM1_CH1N D(1, 1)
400 #define DEF_TIM_AF__PB14__TCH_TIM1_CH2N D(1, 1)
401 #define DEF_TIM_AF__PB15__TCH_TIM1_CH3N D(1, 1)
403 #define DEF_TIM_AF__PB0__TCH_TIM3_CH3 D(2, 3)
404 #define DEF_TIM_AF__PB1__TCH_TIM3_CH4 D(2, 3)
405 #define DEF_TIM_AF__PB4__TCH_TIM3_CH1 D(2, 3)
406 #define DEF_TIM_AF__PB5__TCH_TIM3_CH2 D(2, 3)
407 #define DEF_TIM_AF__PB6__TCH_TIM4_CH1 D(2, 4)
408 #define DEF_TIM_AF__PB7__TCH_TIM4_CH2 D(2, 4)
409 #define DEF_TIM_AF__PB8__TCH_TIM4_CH3 D(2, 4)
410 #define DEF_TIM_AF__PB9__TCH_TIM4_CH4 D(2, 4)
412 #define DEF_TIM_AF__PB0__TCH_TIM8_CH2N D(3, 8)
413 #define DEF_TIM_AF__PB1__TCH_TIM8_CH3N D(3, 8)
414 #define DEF_TIM_AF__PB8__TCH_TIM10_CH1 D(3, 10)
415 #define DEF_TIM_AF__PB9__TCH_TIM11_CH1 D(3, 11)
416 #define DEF_TIM_AF__PB14__TCH_TIM8_CH2N D(3, 8)
417 #define DEF_TIM_AF__PB15__TCH_TIM8_CH3N D(3, 8)
419 #define DEF_TIM_AF__PB14__TCH_TIM12_CH1 D(9, 12)
420 #define DEF_TIM_AF__PB15__TCH_TIM12_CH2 D(9, 12)
422 //PORTC
423 #define DEF_TIM_AF__PC6__TCH_TIM3_CH1 D(2, 3)
424 #define DEF_TIM_AF__PC7__TCH_TIM3_CH2 D(2, 3)
425 #define DEF_TIM_AF__PC8__TCH_TIM3_CH3 D(2, 3)
426 #define DEF_TIM_AF__PC9__TCH_TIM3_CH4 D(2, 3)
428 #define DEF_TIM_AF__PC6__TCH_TIM8_CH1 D(3, 8)
429 #define DEF_TIM_AF__PC7__TCH_TIM8_CH2 D(3, 8)
430 #define DEF_TIM_AF__PC8__TCH_TIM8_CH3 D(3, 8)
431 #define DEF_TIM_AF__PC9__TCH_TIM8_CH4 D(3, 8)
433 //PORTD
434 #define DEF_TIM_AF__PD12__TCH_TIM4_CH1 D(2, 4)
435 #define DEF_TIM_AF__PD13__TCH_TIM4_CH2 D(2, 4)
436 #define DEF_TIM_AF__PD14__TCH_TIM4_CH3 D(2, 4)
437 #define DEF_TIM_AF__PD15__TCH_TIM4_CH4 D(2, 4)
439 //PORTE
440 #define DEF_TIM_AF__PE8__TCH_TIM1_CH1N D(1, 1)
441 #define DEF_TIM_AF__PE9__TCH_TIM1_CH1 D(1, 1)
442 #define DEF_TIM_AF__PE10__TCH_TIM1_CH2N D(1, 1)
443 #define DEF_TIM_AF__PE11__TCH_TIM1_CH2 D(1, 1)
444 #define DEF_TIM_AF__PE12__TCH_TIM1_CH3N D(1, 1)
445 #define DEF_TIM_AF__PE13__TCH_TIM1_CH3 D(1, 1)
446 #define DEF_TIM_AF__PE14__TCH_TIM1_CH4 D(1, 1)
448 #define DEF_TIM_AF__PE5__TCH_TIM9_CH1 D(3, 9)
449 #define DEF_TIM_AF__PE6__TCH_TIM9_CH2 D(3, 9)
451 //PORTF
452 #define DEF_TIM_AF__PF6__TCH_TIM10_CH1 D(3, 10)
453 #define DEF_TIM_AF__PF7__TCH_TIM11_CH1 D(3, 11)
455 //PORTH
456 #define DEF_TIM_AF__PH10__TCH_TIM5_CH1 D(2, 5)
457 #define DEF_TIM_AF__PH11__TCH_TIM5_CH2 D(2, 5)
458 #define DEF_TIM_AF__PH12__TCH_TIM5_CH3 D(2, 5)
460 #define DEF_TIM_AF__PH13__TCH_TIM8_CH1N D(3, 8)
461 #define DEF_TIM_AF__PH14__TCH_TIM8_CH2N D(3, 8)
462 #define DEF_TIM_AF__PH15__TCH_TIM8_CH3N D(3, 8)
464 #define DEF_TIM_AF__PH6__TCH_TIM12_CH1 D(9, 12)
465 #define DEF_TIM_AF__PH9__TCH_TIM12_CH2 D(9, 12)
467 //PORTI
468 #define DEF_TIM_AF__PI0__TCH_TIM5_CH4 D(2, 5)
470 #define DEF_TIM_AF__PI2__TCH_TIM8_CH4 D(3, 8)
471 #define DEF_TIM_AF__PI5__TCH_TIM8_CH1 D(3, 8)
472 #define DEF_TIM_AF__PI6__TCH_TIM8_CH2 D(3, 8)
473 #define DEF_TIM_AF__PI7__TCH_TIM8_CH3 D(3, 8)
475 #elif defined(STM32H7)
476 #define DEF_TIM(tim, chan, pin, out, dmaopt, upopt) { \
477 tim, \
478 TIMER_GET_IO_TAG(pin), \
479 DEF_TIM_CHANNEL(CH_ ## chan), \
480 (DEF_TIM_OUTPUT(CH_ ## chan) | out), \
481 DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
483 DEF_TIM_DMA_STREAM(dmaopt, TCH_## tim ## _ ## chan), \
484 DEF_TIM_DMA_REQUEST(TCH_## tim ## _ ## chan) \
485 ) \
487 DEF_TIM_DMA_STREAM(upopt, TCH_## tim ## _UP), \
488 DEF_TIM_DMA_REQUEST(TCH_## tim ## _UP), \
489 DEF_TIM_DMA_HANDLER(upopt, TCH_## tim ## _UP) \
490 ) \
491 } \
492 /**/
494 #define DEF_TIM_CHANNEL(ch) CONCAT(DEF_TIM_CHANNEL__, DEF_TIM_CH_GET(ch))
495 #define DEF_TIM_CHANNEL__D(chan_n, n_channel) TIM_CHANNEL_ ## chan_n
497 #define DEF_TIM_AF(timch, pin) CONCAT(DEF_TIM_AF__, DEF_TIM_AF_GET(timch, pin))
498 #define DEF_TIM_AF__D(af_n, tim_n) GPIO_AF ## af_n ## _TIM ## tim_n
500 #define DEF_TIM_DMA_STREAM(variant, timch) \
501 CONCAT(DEF_TIM_DMA_STREAM__, DEF_TIM_DMA_GET(variant, timch))
502 #define DEF_TIM_DMA_STREAM__D(dma_n, stream_n) (dmaResource_t *)DMA ## dma_n ## _Stream ## stream_n
503 #define DEF_TIM_DMA_STREAM__NONE NULL
505 // XXX This is awful. There must be some smart way of doing this ...
506 #define DEF_TIM_DMA_REQUEST(timch) \
507 CONCAT(DEF_TIM_DMA_REQ__, DEF_TIM_TCH2BTCH(timch))
509 #define DEF_TIM_DMA_HANDLER(variant, timch) \
510 CONCAT(DEF_TIM_DMA_HANDLER__, DEF_TIM_DMA_GET(variant, timch))
511 #define DEF_TIM_DMA_HANDLER__D(dma_n, stream_n) DMA ## dma_n ## _ST ## stream_n ## _HANDLER
512 #define DEF_TIM_DMA_HANDLER__NONE 0
514 /* H7 Stream Mappings */
515 // D(DMAx, Stream)
517 // H7 has DMAMUX that allow arbitrary assignment of peripherals to streams.
519 #define DEF_TIM_DMA_FULL \
520 D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), \
521 D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7)
523 #define DEF_TIM_DMA__BTCH_TIM1_CH1 DEF_TIM_DMA_FULL
524 #define DEF_TIM_DMA__BTCH_TIM1_CH2 DEF_TIM_DMA_FULL
525 #define DEF_TIM_DMA__BTCH_TIM1_CH3 DEF_TIM_DMA_FULL
526 #define DEF_TIM_DMA__BTCH_TIM1_CH4 DEF_TIM_DMA_FULL
528 #define DEF_TIM_DMA__BTCH_TIM2_CH1 DEF_TIM_DMA_FULL
529 #define DEF_TIM_DMA__BTCH_TIM2_CH2 DEF_TIM_DMA_FULL
530 #define DEF_TIM_DMA__BTCH_TIM2_CH3 DEF_TIM_DMA_FULL
531 #define DEF_TIM_DMA__BTCH_TIM2_CH4 DEF_TIM_DMA_FULL
533 #define DEF_TIM_DMA__BTCH_TIM3_CH1 DEF_TIM_DMA_FULL
534 #define DEF_TIM_DMA__BTCH_TIM3_CH2 DEF_TIM_DMA_FULL
535 #define DEF_TIM_DMA__BTCH_TIM3_CH3 DEF_TIM_DMA_FULL
536 #define DEF_TIM_DMA__BTCH_TIM3_CH4 DEF_TIM_DMA_FULL
538 #define DEF_TIM_DMA__BTCH_TIM4_CH1 DEF_TIM_DMA_FULL
539 #define DEF_TIM_DMA__BTCH_TIM4_CH2 DEF_TIM_DMA_FULL
540 #define DEF_TIM_DMA__BTCH_TIM4_CH3 DEF_TIM_DMA_FULL
541 #define DEF_TIM_DMA__BTCH_TIM4_CH4 NONE
543 #define DEF_TIM_DMA__BTCH_TIM5_CH1 DEF_TIM_DMA_FULL
544 #define DEF_TIM_DMA__BTCH_TIM5_CH2 DEF_TIM_DMA_FULL
545 #define DEF_TIM_DMA__BTCH_TIM5_CH3 DEF_TIM_DMA_FULL
546 #define DEF_TIM_DMA__BTCH_TIM5_CH4 DEF_TIM_DMA_FULL
548 #define DEF_TIM_DMA__BTCH_TIM8_CH1 DEF_TIM_DMA_FULL
549 #define DEF_TIM_DMA__BTCH_TIM8_CH2 DEF_TIM_DMA_FULL
550 #define DEF_TIM_DMA__BTCH_TIM8_CH3 DEF_TIM_DMA_FULL
551 #define DEF_TIM_DMA__BTCH_TIM8_CH4 DEF_TIM_DMA_FULL
553 #define DEF_TIM_DMA__BTCH_TIM12_CH1 NONE
554 #define DEF_TIM_DMA__BTCH_TIM12_CH2 NONE
556 #define DEF_TIM_DMA__BTCH_TIM13_CH1 NONE
558 #define DEF_TIM_DMA__BTCH_TIM14_CH1 NONE
560 #define DEF_TIM_DMA__BTCH_TIM15_CH1 DEF_TIM_DMA_FULL
561 #define DEF_TIM_DMA__BTCH_TIM15_CH2 NONE
563 #define DEF_TIM_DMA__BTCH_TIM16_CH1 DEF_TIM_DMA_FULL
565 #define DEF_TIM_DMA__BTCH_TIM17_CH1 DEF_TIM_DMA_FULL
567 #if defined(STM32H723xx) || defined(STM32H725xx)
568 #define DEF_TIM_DMA__BTCH_TIM23_CH1 DEF_TIM_DMA_FULL
569 #define DEF_TIM_DMA__BTCH_TIM23_CH2 DEF_TIM_DMA_FULL
570 #define DEF_TIM_DMA__BTCH_TIM23_CH3 DEF_TIM_DMA_FULL
571 #define DEF_TIM_DMA__BTCH_TIM23_CH4 DEF_TIM_DMA_FULL
573 #define DEF_TIM_DMA__BTCH_TIM24_CH1 DEF_TIM_DMA_FULL
574 #define DEF_TIM_DMA__BTCH_TIM24_CH2 DEF_TIM_DMA_FULL
575 #define DEF_TIM_DMA__BTCH_TIM24_CH3 DEF_TIM_DMA_FULL
576 #define DEF_TIM_DMA__BTCH_TIM24_CH4 DEF_TIM_DMA_FULL
577 #endif
579 // TIM_UP table
580 #define DEF_TIM_DMA__BTCH_TIM1_UP DEF_TIM_DMA_FULL
581 #define DEF_TIM_DMA__BTCH_TIM2_UP DEF_TIM_DMA_FULL
582 #define DEF_TIM_DMA__BTCH_TIM3_UP DEF_TIM_DMA_FULL
583 #define DEF_TIM_DMA__BTCH_TIM4_UP DEF_TIM_DMA_FULL
584 #define DEF_TIM_DMA__BTCH_TIM5_UP DEF_TIM_DMA_FULL
585 #define DEF_TIM_DMA__BTCH_TIM6_UP DEF_TIM_DMA_FULL
586 #define DEF_TIM_DMA__BTCH_TIM7_UP DEF_TIM_DMA_FULL
587 #define DEF_TIM_DMA__BTCH_TIM8_UP DEF_TIM_DMA_FULL
588 #define DEF_TIM_DMA__BTCH_TIM12_UP NONE
589 #define DEF_TIM_DMA__BTCH_TIM13_UP NONE
590 #define DEF_TIM_DMA__BTCH_TIM14_UP NONE
591 #define DEF_TIM_DMA__BTCH_TIM15_UP DEF_TIM_DMA_FULL
592 #define DEF_TIM_DMA__BTCH_TIM16_UP DEF_TIM_DMA_FULL
593 #define DEF_TIM_DMA__BTCH_TIM17_UP DEF_TIM_DMA_FULL
595 #if defined(STM32H723xx) || defined(STM32H725xx)
596 #define DEF_TIM_DMA__BTCH_TIM23_UP DEF_TIM_DMA_FULL
597 #define DEF_TIM_DMA__BTCH_TIM24_UP DEF_TIM_DMA_FULL
598 #endif
600 // TIMx_CHy request table
602 // This is not defined in stm32h7xx_hal_timer.h
603 #define DMA_REQUEST_NONE 255
605 #define DEF_TIM_DMA_REQ__BTCH_TIM1_CH1 DMA_REQUEST_TIM1_CH1
606 #define DEF_TIM_DMA_REQ__BTCH_TIM1_CH2 DMA_REQUEST_TIM1_CH2
607 #define DEF_TIM_DMA_REQ__BTCH_TIM1_CH3 DMA_REQUEST_TIM1_CH3
608 #define DEF_TIM_DMA_REQ__BTCH_TIM1_CH4 DMA_REQUEST_TIM1_CH4
610 #define DEF_TIM_DMA_REQ__BTCH_TIM2_CH1 DMA_REQUEST_TIM2_CH1
611 #define DEF_TIM_DMA_REQ__BTCH_TIM2_CH2 DMA_REQUEST_TIM2_CH2
612 #define DEF_TIM_DMA_REQ__BTCH_TIM2_CH3 DMA_REQUEST_TIM2_CH3
613 #define DEF_TIM_DMA_REQ__BTCH_TIM2_CH4 DMA_REQUEST_TIM2_CH4
615 #define DEF_TIM_DMA_REQ__BTCH_TIM3_CH1 DMA_REQUEST_TIM3_CH1
616 #define DEF_TIM_DMA_REQ__BTCH_TIM3_CH2 DMA_REQUEST_TIM3_CH2
617 #define DEF_TIM_DMA_REQ__BTCH_TIM3_CH3 DMA_REQUEST_TIM3_CH3
618 #define DEF_TIM_DMA_REQ__BTCH_TIM3_CH4 DMA_REQUEST_TIM3_CH4
620 #define DEF_TIM_DMA_REQ__BTCH_TIM4_CH1 DMA_REQUEST_TIM4_CH1
621 #define DEF_TIM_DMA_REQ__BTCH_TIM4_CH2 DMA_REQUEST_TIM4_CH2
622 #define DEF_TIM_DMA_REQ__BTCH_TIM4_CH3 DMA_REQUEST_TIM4_CH3
623 #define DEF_TIM_DMA_REQ__BTCH_TIM4_CH4 DMA_REQUEST_NONE
625 #define DEF_TIM_DMA_REQ__BTCH_TIM5_CH1 DMA_REQUEST_TIM5_CH1
626 #define DEF_TIM_DMA_REQ__BTCH_TIM5_CH2 DMA_REQUEST_TIM5_CH2
627 #define DEF_TIM_DMA_REQ__BTCH_TIM5_CH3 DMA_REQUEST_TIM5_CH3
628 #define DEF_TIM_DMA_REQ__BTCH_TIM5_CH4 DMA_REQUEST_TIM5_CH4
630 #define DEF_TIM_DMA_REQ__BTCH_TIM8_CH1 DMA_REQUEST_TIM8_CH1
631 #define DEF_TIM_DMA_REQ__BTCH_TIM8_CH2 DMA_REQUEST_TIM8_CH2
632 #define DEF_TIM_DMA_REQ__BTCH_TIM8_CH3 DMA_REQUEST_TIM8_CH3
633 #define DEF_TIM_DMA_REQ__BTCH_TIM8_CH4 DMA_REQUEST_TIM8_CH4
635 #define DEF_TIM_DMA_REQ__BTCH_TIM12_CH1 DMA_REQUEST_NONE
636 #define DEF_TIM_DMA_REQ__BTCH_TIM12_CH2 DMA_REQUEST_NONE
638 #define DEF_TIM_DMA_REQ__BTCH_TIM13_CH1 DMA_REQUEST_NONE
640 #define DEF_TIM_DMA_REQ__BTCH_TIM14_CH1 DMA_REQUEST_NONE
642 #define DEF_TIM_DMA_REQ__BTCH_TIM15_CH1 DMA_REQUEST_TIM15_CH1
643 #define DEF_TIM_DMA_REQ__BTCH_TIM15_CH2 DMA_REQUEST_NONE
645 #define DEF_TIM_DMA_REQ__BTCH_TIM16_CH1 DMA_REQUEST_TIM16_CH1
647 #define DEF_TIM_DMA_REQ__BTCH_TIM17_CH1 DMA_REQUEST_TIM17_CH1
649 #if defined(STM32H723xx) || defined(STM32H725xx)
650 #define DEF_TIM_DMA_REQ__BTCH_TIM23_CH1 DMA_REQUEST_TIM23_CH1
651 #define DEF_TIM_DMA_REQ__BTCH_TIM23_CH2 DMA_REQUEST_TIM23_CH2
652 #define DEF_TIM_DMA_REQ__BTCH_TIM23_CH3 DMA_REQUEST_TIM23_CH3
653 #define DEF_TIM_DMA_REQ__BTCH_TIM23_CH4 DMA_REQUEST_TIM23_CH4
655 #define DEF_TIM_DMA_REQ__BTCH_TIM24_CH1 DMA_REQUEST_TIM24_CH1
656 #define DEF_TIM_DMA_REQ__BTCH_TIM24_CH2 DMA_REQUEST_TIM24_CH2
657 #define DEF_TIM_DMA_REQ__BTCH_TIM24_CH3 DMA_REQUEST_TIM24_CH3
658 #define DEF_TIM_DMA_REQ__BTCH_TIM24_CH4 DMA_REQUEST_TIM24_CH4
659 #endif
661 // TIM_UP request table
662 #define DEF_TIM_DMA_REQ__BTCH_TIM1_UP DMA_REQUEST_TIM1_UP
663 #define DEF_TIM_DMA_REQ__BTCH_TIM2_UP DMA_REQUEST_TIM2_UP
664 #define DEF_TIM_DMA_REQ__BTCH_TIM3_UP DMA_REQUEST_TIM3_UP
665 #define DEF_TIM_DMA_REQ__BTCH_TIM4_UP DMA_REQUEST_TIM4_UP
666 #define DEF_TIM_DMA_REQ__BTCH_TIM5_UP DMA_REQUEST_TIM5_UP
667 #define DEF_TIM_DMA_REQ__BTCH_TIM6_UP DMA_REQUEST_TIM6_UP
668 #define DEF_TIM_DMA_REQ__BTCH_TIM7_UP DMA_REQUEST_TIM7_UP
669 #define DEF_TIM_DMA_REQ__BTCH_TIM8_UP DMA_REQUEST_TIM8_UP
670 #define DEF_TIM_DMA_REQ__BTCH_TIM12_UP DMA_REQUEST_NONE
671 #define DEF_TIM_DMA_REQ__BTCH_TIM13_UP DMA_REQUEST_NONE
672 #define DEF_TIM_DMA_REQ__BTCH_TIM14_UP DMA_REQUEST_NONE
673 #define DEF_TIM_DMA_REQ__BTCH_TIM15_UP DMA_REQUEST_TIM15_UP
674 #define DEF_TIM_DMA_REQ__BTCH_TIM16_UP DMA_REQUEST_TIM16_UP
675 #define DEF_TIM_DMA_REQ__BTCH_TIM17_UP DMA_REQUEST_TIM17_UP
677 #if defined(STM32H723xx) || defined(STM32H725xx)
678 #define DEF_TIM_DMA_REQ__BTCH_TIM23_UP DMA_REQUEST_TIM23_UP
679 #define DEF_TIM_DMA_REQ__BTCH_TIM24_UP DMA_REQUEST_TIM24_UP
680 #endif
682 // AF table
684 // NONE
685 #define DEF_TIM_AF__NONE__TCH_TIM1_CH1 D(1, 1)
686 #define DEF_TIM_AF__NONE__TCH_TIM1_CH2 D(1, 1)
687 #define DEF_TIM_AF__NONE__TCH_TIM1_CH3 D(1, 1)
688 #define DEF_TIM_AF__NONE__TCH_TIM1_CH4 D(1, 1)
689 #define DEF_TIM_AF__NONE__TCH_TIM8_CH1 D(3, 8)
690 #define DEF_TIM_AF__NONE__TCH_TIM8_CH2 D(3, 8)
691 #define DEF_TIM_AF__NONE__TCH_TIM8_CH3 D(3, 8)
692 #define DEF_TIM_AF__NONE__TCH_TIM8_CH4 D(3, 8)
694 //PORTA
695 #define DEF_TIM_AF__PA0__TCH_TIM2_CH1 D(1, 2)
696 #define DEF_TIM_AF__PA1__TCH_TIM2_CH2 D(1, 2)
697 #define DEF_TIM_AF__PA2__TCH_TIM2_CH3 D(1, 2)
698 #define DEF_TIM_AF__PA3__TCH_TIM2_CH4 D(1, 2)
699 #define DEF_TIM_AF__PA5__TCH_TIM2_CH1 D(1, 2)
700 #define DEF_TIM_AF__PA7__TCH_TIM1_CH1N D(1, 1)
701 #define DEF_TIM_AF__PA8__TCH_TIM1_CH1 D(1, 1)
702 #define DEF_TIM_AF__PA9__TCH_TIM1_CH2 D(1, 1)
703 #define DEF_TIM_AF__PA10__TCH_TIM1_CH3 D(1, 1)
704 #define DEF_TIM_AF__PA11__TCH_TIM1_CH4 D(1, 1)
705 #define DEF_TIM_AF__PA15__TCH_TIM2_CH1 D(1, 2)
707 #define DEF_TIM_AF__PA0__TCH_TIM5_CH1 D(2, 5)
708 #define DEF_TIM_AF__PA1__TCH_TIM5_CH2 D(2, 5)
709 #define DEF_TIM_AF__PA2__TCH_TIM5_CH3 D(2, 5)
710 #define DEF_TIM_AF__PA3__TCH_TIM5_CH4 D(2, 5)
711 #define DEF_TIM_AF__PA6__TCH_TIM3_CH1 D(2, 3)
712 #define DEF_TIM_AF__PA7__TCH_TIM3_CH2 D(2, 3)
714 #define DEF_TIM_AF__PA5__TCH_TIM8_CH1N D(3, 8)
715 #define DEF_TIM_AF__PA7__TCH_TIM8_CH1N D(3, 8)
717 #define DEF_TIM_AF__PA6__TCH_TIM13_CH1 D(9, 13)
718 #define DEF_TIM_AF__PA7__TCH_TIM14_CH1 D(9, 14)
720 #define DEF_TIM_AF__PA1__TCH_TIM15_CH1N D(4, 15)
721 #define DEF_TIM_AF__PA2__TCH_TIM15_CH1 D(4, 15)
722 #define DEF_TIM_AF__PA3__TCH_TIM15_CH2 D(4, 15)
724 //PORTB
725 #define DEF_TIM_AF__PB0__TCH_TIM1_CH2N D(1, 1)
726 #define DEF_TIM_AF__PB1__TCH_TIM1_CH3N D(1, 1)
727 #define DEF_TIM_AF__PB3__TCH_TIM2_CH2 D(1, 2)
728 #define DEF_TIM_AF__PB6__TCH_TIM16_CH1N D(1, 16)
729 #define DEF_TIM_AF__PB7__TCH_TIM17_CH1N D(1, 17)
730 #define DEF_TIM_AF__PB8__TCH_TIM16_CH1 D(1, 16)
731 #define DEF_TIM_AF__PB9__TCH_TIM17_CH1 D(1, 17)
732 #define DEF_TIM_AF__PB10__TCH_TIM2_CH3 D(1, 2)
733 #define DEF_TIM_AF__PB11__TCH_TIM2_CH4 D(1, 2)
734 #define DEF_TIM_AF__PB13__TCH_TIM1_CH1N D(1, 1)
735 #define DEF_TIM_AF__PB14__TCH_TIM1_CH2N D(1, 1)
736 #define DEF_TIM_AF__PB15__TCH_TIM1_CH3N D(1, 1)
738 #define DEF_TIM_AF__PB0__TCH_TIM3_CH3 D(2, 3)
739 #define DEF_TIM_AF__PB1__TCH_TIM3_CH4 D(2, 3)
740 #define DEF_TIM_AF__PB4__TCH_TIM3_CH1 D(2, 3)
741 #define DEF_TIM_AF__PB5__TCH_TIM3_CH2 D(2, 3)
742 #define DEF_TIM_AF__PB6__TCH_TIM4_CH1 D(2, 4)
743 #define DEF_TIM_AF__PB7__TCH_TIM4_CH2 D(2, 4)
744 #define DEF_TIM_AF__PB8__TCH_TIM4_CH3 D(2, 4)
745 #define DEF_TIM_AF__PB9__TCH_TIM4_CH4 D(2, 4)
747 #define DEF_TIM_AF__PB14__TCH_TIM12_CH1 D(2, 12)
748 #define DEF_TIM_AF__PB15__TCH_TIM12_CH2 D(2, 12)
750 //PORTC
751 #define DEF_TIM_AF__PC6__TCH_TIM3_CH1 D(2, 3)
752 #define DEF_TIM_AF__PC7__TCH_TIM3_CH2 D(2, 3)
753 #define DEF_TIM_AF__PC8__TCH_TIM3_CH3 D(2, 3)
754 #define DEF_TIM_AF__PC9__TCH_TIM3_CH4 D(2, 3)
756 #define DEF_TIM_AF__PC6__TCH_TIM8_CH1 D(3, 8)
757 #define DEF_TIM_AF__PC7__TCH_TIM8_CH2 D(3, 8)
758 #define DEF_TIM_AF__PC8__TCH_TIM8_CH3 D(3, 8)
759 #define DEF_TIM_AF__PC9__TCH_TIM8_CH4 D(3, 8)
761 //PORTD
762 #define DEF_TIM_AF__PD12__TCH_TIM4_CH1 D(2, 4)
763 #define DEF_TIM_AF__PD13__TCH_TIM4_CH2 D(2, 4)
764 #define DEF_TIM_AF__PD14__TCH_TIM4_CH3 D(2, 4)
765 #define DEF_TIM_AF__PD15__TCH_TIM4_CH4 D(2, 4)
767 //PORTE
768 #define DEF_TIM_AF__PE8__TCH_TIM1_CH1N D(1, 1)
769 #define DEF_TIM_AF__PE9__TCH_TIM1_CH1 D(1, 1)
770 #define DEF_TIM_AF__PE10__TCH_TIM1_CH2N D(1, 1)
771 #define DEF_TIM_AF__PE11__TCH_TIM1_CH2 D(1, 1)
772 #define DEF_TIM_AF__PE12__TCH_TIM1_CH3N D(1, 1)
773 #define DEF_TIM_AF__PE13__TCH_TIM1_CH3 D(1, 1)
774 #define DEF_TIM_AF__PE14__TCH_TIM1_CH4 D(1, 1)
776 #define DEF_TIM_AF__PE4__TCH_TIM15_CH1N D(4, 15)
777 #define DEF_TIM_AF__PE5__TCH_TIM15_CH1 D(4, 15)
778 #define DEF_TIM_AF__PE6__TCH_TIM15_CH2 D(4, 15)
780 //PORTF
781 #define DEF_TIM_AF__PF6__TCH_TIM16_CH1 D(1, 16)
782 #define DEF_TIM_AF__PF7__TCH_TIM17_CH1 D(1, 17)
783 #define DEF_TIM_AF__PF8__TCH_TIM16_CH1N D(1, 16)
784 #define DEF_TIM_AF__PF9__TCH_TIM17_CH1N D(1, 17)
786 #define DEF_TIM_AF__PF8__TCH_TIM13_CH1N D(9, 13)
787 #define DEF_TIM_AF__PF9__TCH_TIM14_CH1N D(9, 14)
789 #if defined(STM32H723xx) || defined(STM32H725xx)
790 #define DEF_TIM_AF__PF0__TCH_TIM23_CH1 D(13, 23)
791 #define DEF_TIM_AF__PF1__TCH_TIM23_CH2 D(13, 23)
792 #define DEF_TIM_AF__PF2__TCH_TIM23_CH3 D(13, 23)
793 #define DEF_TIM_AF__PF3__TCH_TIM23_CH4 D(13, 23)
794 #define DEF_TIM_AF__PF6__TCH_TIM23_CH1 D(13, 23)
795 #define DEF_TIM_AF__PF7__TCH_TIM23_CH2 D(13, 23)
796 #define DEF_TIM_AF__PF8__TCH_TIM23_CH3 D(13, 23)
797 #define DEF_TIM_AF__PF9__TCH_TIM23_CH4 D(13, 23)
799 #define DEF_TIM_AF__PF11__TCH_TIM24_CH1 D(14, 24)
800 #define DEF_TIM_AF__PF12__TCH_TIM24_CH2 D(14, 24)
801 #define DEF_TIM_AF__PF13__TCH_TIM24_CH3 D(14, 24)
802 #define DEF_TIM_AF__PF14__TCH_TIM24_CH4 D(14, 24)
803 #endif
805 //PORTH
806 #define DEF_TIM_AF__PH6__TCH_TIM12_CH1 D(2, 12)
807 #define DEF_TIM_AF__PH9__TCH_TIM12_CH2 D(2, 12)
808 #define DEF_TIM_AF__PH10__TCH_TIM5_CH1 D(2, 5)
809 #define DEF_TIM_AF__PH11__TCH_TIM5_CH2 D(2, 5)
810 #define DEF_TIM_AF__PH12__TCH_TIM5_CH3 D(2, 5)
811 #define DEF_TIM_AF__PH13__TCH_TIM8_CH1N D(3, 8)
812 #define DEF_TIM_AF__PH14__TCH_TIM8_CH2N D(3, 8)
813 #define DEF_TIM_AF__PH15__TCH_TIM8_CH3N D(3, 8)
815 //PORTI
816 #define DEF_TIM_AF__PI0__TCH_TIM5_CH4 D(2, 5)
818 #define DEF_TIM_AF__PI2__TCH_TIM8_CH4 D(3, 8)
819 #define DEF_TIM_AF__PI5__TCH_TIM8_CH1 D(3, 8)
820 #define DEF_TIM_AF__PI6__TCH_TIM8_CH2 D(3, 8)
821 #define DEF_TIM_AF__PI7__TCH_TIM8_CH3 D(3, 8)
823 #elif defined(STM32G4)
825 // Missing from FW1.0.0 library?
828 #define DEF_TIM(tim, chan, pin, out, dmaopt, upopt) { \
829 tim, \
830 TIMER_GET_IO_TAG(pin), \
831 DEF_TIM_CHANNEL(CH_ ## chan), \
832 (DEF_TIM_OUTPUT(CH_ ## chan) | out), \
833 DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
835 DEF_TIM_DMA_CHANNEL(dmaopt, TCH_## tim ## _ ## chan), \
836 DEF_TIM_DMA_REQUEST(TCH_## tim ## _ ## chan) \
837 ) \
839 DEF_TIM_DMA_CHANNEL(upopt, TCH_## tim ## _UP), \
840 DEF_TIM_DMA_REQUEST(TCH_## tim ## _UP), \
841 DEF_TIM_DMA_HANDLER(upopt, TCH_## tim ## _UP) \
842 ) \
843 } \
844 /**/
846 #define DEF_TIM_CHANNEL(ch) CONCAT(DEF_TIM_CHANNEL__, DEF_TIM_CH_GET(ch))
847 #define DEF_TIM_CHANNEL__D(chan_n, n_channel) TIM_CHANNEL_ ## chan_n
849 #define DEF_TIM_AF(timch, pin) CONCAT(DEF_TIM_AF__, DEF_TIM_AF_GET(timch, pin))
850 #define DEF_TIM_AF__D(af_n, tim_n) GPIO_AF ## af_n ## _TIM ## tim_n
852 #define DEF_TIM_DMA_CHANNEL(variant, timch) \
853 CONCAT(DEF_TIM_DMA_CHANNEL__, DEF_TIM_DMA_GET(variant, timch))
854 #define DEF_TIM_DMA_CHANNEL__D(dma_n, channel_n) (dmaResource_t *)DMA ## dma_n ## _Channel ## channel_n
855 #define DEF_TIM_DMA_CHANNEL__NONE NULL
857 // XXX This is awful. There must be some smart way of doing this ...
858 #define DEF_TIM_DMA_REQUEST(timch) \
859 CONCAT(DEF_TIM_DMA_REQ__, DEF_TIM_TCH2BTCH(timch))
861 #define DEF_TIM_DMA_HANDLER(variant, timch) \
862 CONCAT(DEF_TIM_DMA_HANDLER__, DEF_TIM_DMA_GET(variant, timch))
863 #define DEF_TIM_DMA_HANDLER__D(dma_n, channel_n) DMA ## dma_n ## _CH ## channel_n ## _HANDLER
864 #define DEF_TIM_DMA_HANDLER__NONE 0
866 /* G4 Channel Mappings */
867 // D(DMAx, Stream)
869 // G4 has DMAMUX that allow arbitrary assignment of peripherals to streams.
871 #define DEF_TIM_DMA_FULL \
872 D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), D(1, 8), \
873 D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(2, 8)
875 #define DEF_TIM_DMA__BTCH_TIM1_CH1 DEF_TIM_DMA_FULL
876 #define DEF_TIM_DMA__BTCH_TIM1_CH2 DEF_TIM_DMA_FULL
877 #define DEF_TIM_DMA__BTCH_TIM1_CH3 DEF_TIM_DMA_FULL
878 #define DEF_TIM_DMA__BTCH_TIM1_CH4 DEF_TIM_DMA_FULL
880 #define DEF_TIM_DMA__BTCH_TIM2_CH1 DEF_TIM_DMA_FULL
881 #define DEF_TIM_DMA__BTCH_TIM2_CH2 DEF_TIM_DMA_FULL
882 #define DEF_TIM_DMA__BTCH_TIM2_CH3 DEF_TIM_DMA_FULL
883 #define DEF_TIM_DMA__BTCH_TIM2_CH4 DEF_TIM_DMA_FULL
885 #define DEF_TIM_DMA__BTCH_TIM3_CH1 DEF_TIM_DMA_FULL
886 #define DEF_TIM_DMA__BTCH_TIM3_CH2 DEF_TIM_DMA_FULL
887 #define DEF_TIM_DMA__BTCH_TIM3_CH3 DEF_TIM_DMA_FULL
888 #define DEF_TIM_DMA__BTCH_TIM3_CH4 DEF_TIM_DMA_FULL
890 #define DEF_TIM_DMA__BTCH_TIM4_CH1 DEF_TIM_DMA_FULL
891 #define DEF_TIM_DMA__BTCH_TIM4_CH2 DEF_TIM_DMA_FULL
892 #define DEF_TIM_DMA__BTCH_TIM4_CH3 DEF_TIM_DMA_FULL
893 #define DEF_TIM_DMA__BTCH_TIM4_CH4 DEF_TIM_DMA_FULL
895 #define DEF_TIM_DMA__BTCH_TIM5_CH1 DEF_TIM_DMA_FULL
896 #define DEF_TIM_DMA__BTCH_TIM5_CH2 DEF_TIM_DMA_FULL
897 #define DEF_TIM_DMA__BTCH_TIM5_CH3 DEF_TIM_DMA_FULL
898 #define DEF_TIM_DMA__BTCH_TIM5_CH4 DEF_TIM_DMA_FULL
900 #define DEF_TIM_DMA__BTCH_TIM8_CH1 DEF_TIM_DMA_FULL
901 #define DEF_TIM_DMA__BTCH_TIM8_CH2 DEF_TIM_DMA_FULL
902 #define DEF_TIM_DMA__BTCH_TIM8_CH3 DEF_TIM_DMA_FULL
903 #define DEF_TIM_DMA__BTCH_TIM8_CH4 DEF_TIM_DMA_FULL
905 #define DEF_TIM_DMA__BTCH_TIM15_CH1 DEF_TIM_DMA_FULL
906 #define DEF_TIM_DMA__BTCH_TIM15_CH2 NONE
908 #define DEF_TIM_DMA__BTCH_TIM16_CH1 DEF_TIM_DMA_FULL
910 #define DEF_TIM_DMA__BTCH_TIM17_CH1 DEF_TIM_DMA_FULL
912 #define DEF_TIM_DMA__BTCH_TIM20_CH1 DEF_TIM_DMA_FULL
913 #define DEF_TIM_DMA__BTCH_TIM20_CH2 DEF_TIM_DMA_FULL
914 #define DEF_TIM_DMA__BTCH_TIM20_CH3 DEF_TIM_DMA_FULL
915 #define DEF_TIM_DMA__BTCH_TIM20_CH4 DEF_TIM_DMA_FULL
917 // TIM_UP table
918 #define DEF_TIM_DMA__BTCH_TIM1_UP DEF_TIM_DMA_FULL
919 #define DEF_TIM_DMA__BTCH_TIM2_UP DEF_TIM_DMA_FULL
920 #define DEF_TIM_DMA__BTCH_TIM3_UP DEF_TIM_DMA_FULL
921 #define DEF_TIM_DMA__BTCH_TIM4_UP DEF_TIM_DMA_FULL
922 #define DEF_TIM_DMA__BTCH_TIM5_UP DEF_TIM_DMA_FULL
923 #define DEF_TIM_DMA__BTCH_TIM6_UP DEF_TIM_DMA_FULL
924 #define DEF_TIM_DMA__BTCH_TIM7_UP DEF_TIM_DMA_FULL
925 #define DEF_TIM_DMA__BTCH_TIM8_UP DEF_TIM_DMA_FULL
926 #define DEF_TIM_DMA__BTCH_TIM15_UP DEF_TIM_DMA_FULL
927 #define DEF_TIM_DMA__BTCH_TIM16_UP DEF_TIM_DMA_FULL
928 #define DEF_TIM_DMA__BTCH_TIM17_UP DEF_TIM_DMA_FULL
929 #define DEF_TIM_DMA__BTCH_TIM20_UP DEF_TIM_DMA_FULL
931 // TIMx_CHy request table
933 // This is not defined in stm32g7xx_hal_timer.h
934 #define DMA_REQUEST_NONE 255
936 #define DEF_TIM_DMA_REQ__BTCH_TIM1_CH1 DMA_REQUEST_TIM1_CH1
937 #define DEF_TIM_DMA_REQ__BTCH_TIM1_CH2 DMA_REQUEST_TIM1_CH2
938 #define DEF_TIM_DMA_REQ__BTCH_TIM1_CH3 DMA_REQUEST_TIM1_CH3
939 #define DEF_TIM_DMA_REQ__BTCH_TIM1_CH4 DMA_REQUEST_TIM1_CH4
941 #define DEF_TIM_DMA_REQ__BTCH_TIM2_CH1 DMA_REQUEST_TIM2_CH1
942 #define DEF_TIM_DMA_REQ__BTCH_TIM2_CH2 DMA_REQUEST_TIM2_CH2
943 #define DEF_TIM_DMA_REQ__BTCH_TIM2_CH3 DMA_REQUEST_TIM2_CH3
944 #define DEF_TIM_DMA_REQ__BTCH_TIM2_CH4 DMA_REQUEST_TIM2_CH4
946 #define DEF_TIM_DMA_REQ__BTCH_TIM3_CH1 DMA_REQUEST_TIM3_CH1
947 #define DEF_TIM_DMA_REQ__BTCH_TIM3_CH2 DMA_REQUEST_TIM3_CH2
948 #define DEF_TIM_DMA_REQ__BTCH_TIM3_CH3 DMA_REQUEST_TIM3_CH3
949 #define DEF_TIM_DMA_REQ__BTCH_TIM3_CH4 DMA_REQUEST_TIM3_CH4
951 #define DEF_TIM_DMA_REQ__BTCH_TIM4_CH1 DMA_REQUEST_TIM4_CH1
952 #define DEF_TIM_DMA_REQ__BTCH_TIM4_CH2 DMA_REQUEST_TIM4_CH2
953 #define DEF_TIM_DMA_REQ__BTCH_TIM4_CH3 DMA_REQUEST_TIM4_CH3
954 #define DEF_TIM_DMA_REQ__BTCH_TIM4_CH4 DMA_REQUEST_TIM4_CH4
956 #define DEF_TIM_DMA_REQ__BTCH_TIM5_CH1 DMA_REQUEST_TIM5_CH1
957 #define DEF_TIM_DMA_REQ__BTCH_TIM5_CH2 DMA_REQUEST_TIM5_CH2
958 #define DEF_TIM_DMA_REQ__BTCH_TIM5_CH3 DMA_REQUEST_TIM5_CH3
959 #define DEF_TIM_DMA_REQ__BTCH_TIM5_CH4 DMA_REQUEST_TIM5_CH4
961 #define DEF_TIM_DMA_REQ__BTCH_TIM8_CH1 DMA_REQUEST_TIM8_CH1
962 #define DEF_TIM_DMA_REQ__BTCH_TIM8_CH2 DMA_REQUEST_TIM8_CH2
963 #define DEF_TIM_DMA_REQ__BTCH_TIM8_CH3 DMA_REQUEST_TIM8_CH3
964 #define DEF_TIM_DMA_REQ__BTCH_TIM8_CH4 DMA_REQUEST_TIM8_CH4
966 #define DEF_TIM_DMA_REQ__BTCH_TIM15_CH1 DMA_REQUEST_TIM15_CH1
967 #define DEF_TIM_DMA_REQ__BTCH_TIM15_CH2 DMA_REQUEST_NONE
969 #define DEF_TIM_DMA_REQ__BTCH_TIM16_CH1 DMA_REQUEST_TIM16_CH1
971 #define DEF_TIM_DMA_REQ__BTCH_TIM17_CH1 DMA_REQUEST_TIM17_CH1
973 #define DEF_TIM_DMA_REQ__BTCH_TIM20_CH1 DMA_REQUEST_TIM20_CH1
974 #define DEF_TIM_DMA_REQ__BTCH_TIM20_CH2 DMA_REQUEST_TIM20_CH2
975 #define DEF_TIM_DMA_REQ__BTCH_TIM20_CH3 DMA_REQUEST_TIM20_CH3
976 #define DEF_TIM_DMA_REQ__BTCH_TIM20_CH4 DMA_REQUEST_TIM20_CH4
978 // TIM_UP request table
979 #define DEF_TIM_DMA_REQ__BTCH_TIM1_UP DMA_REQUEST_TIM1_UP
980 #define DEF_TIM_DMA_REQ__BTCH_TIM2_UP DMA_REQUEST_TIM2_UP
981 #define DEF_TIM_DMA_REQ__BTCH_TIM3_UP DMA_REQUEST_TIM3_UP
982 #define DEF_TIM_DMA_REQ__BTCH_TIM4_UP DMA_REQUEST_TIM4_UP
983 #define DEF_TIM_DMA_REQ__BTCH_TIM5_UP DMA_REQUEST_TIM5_UP
984 #define DEF_TIM_DMA_REQ__BTCH_TIM6_UP DMA_REQUEST_TIM6_UP
985 #define DEF_TIM_DMA_REQ__BTCH_TIM7_UP DMA_REQUEST_TIM7_UP
986 #define DEF_TIM_DMA_REQ__BTCH_TIM8_UP DMA_REQUEST_TIM8_UP
987 #define DEF_TIM_DMA_REQ__BTCH_TIM15_UP DMA_REQUEST_TIM15_UP
988 #define DEF_TIM_DMA_REQ__BTCH_TIM16_UP DMA_REQUEST_TIM16_UP
989 #define DEF_TIM_DMA_REQ__BTCH_TIM17_UP DMA_REQUEST_TIM17_UP
990 #define DEF_TIM_DMA_REQ__BTCH_TIM20_UP DMA_REQUEST_TIM20_UP
992 // AF table
994 //NONE
995 #define DEF_TIM_AF__NONE__TCH_TIM1_CH1 D(6, 1)
996 #define DEF_TIM_AF__NONE__TCH_TIM1_CH2 D(6, 1)
997 #define DEF_TIM_AF__NONE__TCH_TIM1_CH3 D(6, 1)
998 #define DEF_TIM_AF__NONE__TCH_TIM1_CH4 D(6, 1)
999 #define DEF_TIM_AF__NONE__TCH_TIM8_CH1 D(3, 8)
1000 #define DEF_TIM_AF__NONE__TCH_TIM8_CH2 D(3, 8)
1001 #define DEF_TIM_AF__NONE__TCH_TIM8_CH3 D(3, 8)
1002 #define DEF_TIM_AF__NONE__TCH_TIM8_CH4 D(3, 8)
1004 //PORTA
1005 #define DEF_TIM_AF__PA0__TCH_TIM2_CH1 D(1, 2)
1006 #define DEF_TIM_AF__PA1__TCH_TIM2_CH2 D(1, 2)
1007 #define DEF_TIM_AF__PA2__TCH_TIM2_CH3 D(1, 2)
1008 #define DEF_TIM_AF__PA3__TCH_TIM2_CH4 D(1, 2)
1009 #define DEF_TIM_AF__PA5__TCH_TIM2_CH1 D(1, 2)
1010 #define DEF_TIM_AF__PA6__TCH_TIM16_CH1 D(1, 16)
1011 #define DEF_TIM_AF__PA7__TCH_TIM17_CH1 D(1, 17)
1012 #define DEF_TIM_AF__PA12__TCH_TIM16_CH1 D(1, 16)
1013 #define DEF_TIM_AF__PA13__TCH_TIM16_CH1N D(1, 16)
1014 #define DEF_TIM_AF__PA15__TCH_TIM2_CH1 D(1, 2)
1016 #define DEF_TIM_AF__PA0__TCH_TIM5_CH1 D(2, 5)
1017 #define DEF_TIM_AF__PA1__TCH_TIM5_CH2 D(2, 5)
1018 #define DEF_TIM_AF__PA2__TCH_TIM5_CH3 D(2, 5)
1019 #define DEF_TIM_AF__PA3__TCH_TIM5_CH4 D(2, 5)
1020 #define DEF_TIM_AF__PA4__TCH_TIM3_CH2 D(2, 3)
1021 #define DEF_TIM_AF__PA6__TCH_TIM3_CH1 D(2, 3)
1022 #define DEF_TIM_AF__PA7__TCH_TIM3_CH2 D(2, 3)
1023 #define DEF_TIM_AF__PA15__TCH_TIM8_CH1 D(2, 8)
1025 #define DEF_TIM_AF__PA7__TCH_TIM8_CH1N D(4, 8)
1027 #define DEF_TIM_AF__PA14__TCH_TIM8_CH2 D(5, 8)
1029 #define DEF_TIM_AF__PA7__TCH_TIM1_CH1N D(6, 1)
1030 #define DEF_TIM_AF__PA8__TCH_TIM1_CH1 D(6, 1)
1031 #define DEF_TIM_AF__PA9__TCH_TIM1_CH2 D(6, 1)
1032 #define DEF_TIM_AF__PA10__TCH_TIM1_CH3 D(6, 1)
1033 #define DEF_TIM_AF__PA11__TCH_TIM1_CH1N D(6, 1)
1034 #define DEF_TIM_AF__PA12__TCH_TIM1_CH2N D(6, 1)
1036 #define DEF_TIM_AF__PA1__TCH_TIM15_CH1N D(9, 15)
1037 #define DEF_TIM_AF__PA2__TCH_TIM15_CH1 D(9, 15)
1038 #define DEF_TIM_AF__PA3__TCH_TIM15_CH2 D(9, 15)
1040 #define DEF_TIM_AF__PA9__TCH_TIM2_CH3 D(10, 2)
1041 #define DEF_TIM_AF__PA10__TCH_TIM2_CH4 D(10, 2)
1042 #define DEF_TIM_AF__PA11__TCH_TIM4_CH1 D(10, 4)
1043 #define DEF_TIM_AF__PA12__TCH_TIM4_CH2 D(10, 4)
1044 #define DEF_TIM_AF__PA13__TCH_TIM4_CH3 D(10, 4)
1046 #define DEF_TIM_AF__PA11__TCH_TIM1_CH4 D(11, 1)
1048 //PORTB
1049 #define DEF_TIM_AF__PB3__TCH_TIM2_CH2 D(1, 2)
1050 #define DEF_TIM_AF__PB4__TCH_TIM16_CH1 D(1, 16)
1051 #define DEF_TIM_AF__PB6__TCH_TIM16_CH1N D(1, 16)
1052 #define DEF_TIM_AF__PB7__TCH_TIM17_CH1N D(1, 17)
1053 #define DEF_TIM_AF__PB8__TCH_TIM16_CH1 D(1, 16)
1054 #define DEF_TIM_AF__PB9__TCH_TIM17_CH1 D(1, 17)
1055 #define DEF_TIM_AF__PB10__TCH_TIM2_CH3 D(1, 2)
1056 #define DEF_TIM_AF__PB11__TCH_TIM2_CH4 D(1, 2)
1057 #define DEF_TIM_AF__PB14__TCH_TIM15_CH1 D(1, 15)
1058 #define DEF_TIM_AF__PB15__TCH_TIM15_CH2 D(1, 15)
1060 #define DEF_TIM_AF__PB0__TCH_TIM3_CH3 D(2, 3)
1061 #define DEF_TIM_AF__PB1__TCH_TIM3_CH4 D(2, 3)
1062 #define DEF_TIM_AF__PB2__TCH_TIM5_CH1 D(2, 5)
1063 #define DEF_TIM_AF__PB4__TCH_TIM3_CH1 D(2, 3)
1064 #define DEF_TIM_AF__PB5__TCH_TIM3_CH2 D(2, 3)
1065 #define DEF_TIM_AF__PB6__TCH_TIM4_CH1 D(2, 4)
1066 #define DEF_TIM_AF__PB7__TCH_TIM4_CH2 D(2, 4)
1067 #define DEF_TIM_AF__PB8__TCH_TIM4_CH3 D(2, 4)
1068 #define DEF_TIM_AF__PB9__TCH_TIM4_CH4 D(2, 4)
1069 #define DEF_TIM_AF__PB15__TCH_TIM15_CH1N D(2, 15)
1071 #define DEF_TIM_AF__PB2__TCH_TIM20_CH1 D(3, 20)
1072 #define DEF_TIM_AF__PB5__TCH_TIM8_CH3N D(3, 8)
1074 #define DEF_TIM_AF__PB0__TCH_TIM8_CH2N D(4, 8)
1075 #define DEF_TIM_AF__PB1__TCH_TIM8_CH3N D(4, 8)
1076 #define DEF_TIM_AF__PB3__TCH_TIM8_CH1N D(4, 8)
1077 #define DEF_TIM_AF__PB4__TCH_TIM8_CH2N D(4, 8)
1078 #define DEF_TIM_AF__PB15__TCH_TIM1_CH3N D(4, 1)
1080 #define DEF_TIM_AF__PB6__TCH_TIM8_CH1 D(5, 8)
1082 #define DEF_TIM_AF__PB0__TCH_TIM1_CH2N D(6, 1)
1083 #define DEF_TIM_AF__PB1__TCH_TIM1_CH3N D(6, 1)
1084 #define DEF_TIM_AF__PB13__TCH_TIM1_CH1N D(6, 1)
1085 #define DEF_TIM_AF__PB14__TCH_TIM1_CH2N D(6, 1)
1087 #define DEF_TIM_AF__PB5__TCH_TIM17_CH1 D(10, 17)
1088 #define DEF_TIM_AF__PB7__TCH_TIM3_CH4 D(10, 3)
1089 #define DEF_TIM_AF__PB8__TCH_TIM8_CH2 D(10, 8)
1090 #define DEF_TIM_AF__PB9__TCH_TIM8_CH3 D(10, 8)
1092 #define DEF_TIM_AF__PB9__TCH_TIM1_CH3N D(12, 1)
1094 //PORTC
1095 #define DEF_TIM_AF__PC12__TCH_TIM5_CH2 D(1, 5)
1097 #define DEF_TIM_AF__PC0__TCH_TIM1_CH1 D(2, 1)
1098 #define DEF_TIM_AF__PC1__TCH_TIM1_CH2 D(2, 1)
1099 #define DEF_TIM_AF__PC2__TCH_TIM1_CH3 D(2, 1)
1100 #define DEF_TIM_AF__PC3__TCH_TIM1_CH4 D(2, 1)
1101 #define DEF_TIM_AF__PC6__TCH_TIM3_CH1 D(2, 3)
1102 #define DEF_TIM_AF__PC7__TCH_TIM3_CH2 D(2, 3)
1103 #define DEF_TIM_AF__PC8__TCH_TIM3_CH3 D(2, 3)
1104 #define DEF_TIM_AF__PC9__TCH_TIM3_CH4 D(2, 3)
1106 #define DEF_TIM_AF__PC6__TCH_TIM8_CH1 D(4, 8)
1107 #define DEF_TIM_AF__PC7__TCH_TIM8_CH2 D(4, 8)
1108 #define DEF_TIM_AF__PC8__TCH_TIM8_CH3 D(4, 8)
1109 #define DEF_TIM_AF__PC9__TCH_TIM8_CH4 D(4, 8)
1110 #define DEF_TIM_AF__PC10__TCH_TIM8_CH1N D(4, 8)
1111 #define DEF_TIM_AF__PC11__TCH_TIM8_CH2N D(4, 8)
1112 #define DEF_TIM_AF__PC12__TCH_TIM8_CH3N D(4, 8)
1113 #define DEF_TIM_AF__PC13__TCH_TIM1_CH1N D(4, 1)
1115 #define DEF_TIM_AF__PC2__TCH_TIM20_CH2 D(6, 20)
1116 #define DEF_TIM_AF__PC5__TCH_TIM1_CH4N D(6, 1)
1117 #define DEF_TIM_AF__PC8__TCH_TIM20_CH3 D(6, 20)
1118 #define DEF_TIM_AF__PC13__TCH_TIM8_CH4N D(6, 8)
1120 #endif
1122 #if defined(STM32F7)
1124 #define FULL_TIMER_CHANNEL_COUNT 78
1125 #define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(8) | TIM_N(9) | TIM_N(10) | TIM_N(11) | TIM_N(12) | TIM_N(13) | TIM_N(14) )
1126 #define HARDWARE_TIMER_DEFINITION_COUNT 14
1128 #elif defined(STM32F4)
1130 #if defined(STM32F411xE)
1131 #define FULL_TIMER_CHANNEL_COUNT 59
1132 #define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(9) | TIM_N(10) | TIM_N(11) )
1133 #define HARDWARE_TIMER_DEFINITION_COUNT 10
1135 #else
1137 #define FULL_TIMER_CHANNEL_COUNT 78
1138 #define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(8) | TIM_N(9) | TIM_N(10) | TIM_N(11) | TIM_N(12) | TIM_N(13) | TIM_N(14) )
1139 #define HARDWARE_TIMER_DEFINITION_COUNT 14
1143 #elif defined(STM32H7)
1145 #define FULL_TIMER_CHANNEL_COUNT 87
1146 #define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(8) | TIM_N(12) | TIM_N(13) | TIM_N(14) | TIM_N(15) | TIM_N(16) | TIM_N(17) )
1147 #define HARDWARE_TIMER_DEFINITION_COUNT 17
1148 #define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(15) | BIT(16) | BIT(17) )
1150 #elif defined(STM32G4)
1153 #define USED_TIMERS ( TIM_N(1) | TIM_N(2) | TIM_N(3) | TIM_N(4) | TIM_N(5) | TIM_N(6) | TIM_N(7) | TIM_N(8) | TIM_N(15) | TIM_N(16) | TIM_N(17) | TIM_N(20) )
1154 #define HARDWARE_TIMER_DEFINITION_COUNT 12
1155 #define TIMUP_TIMERS ( BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(15) | BIT(16) | BIT(17) | BIT(20))
1157 #endif