Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
[binutils-gdb.git] / ld / testsuite / ld-x86-64 / plt.pd
blobb11cc22aab833d1af92a45e63b0b1ec32255278e
1 #source: plt.s
2 #as: --64
3 #ld: -melf_x86_64
4 #objdump: -drj.plt
5 #target: x86_64-*-*
7 .*: +file format .*
9 Disassembly of section .plt:
11 [0-9a-f]+ <fn1@plt-0x10>:
12  +[0-9a-f]+:    ff 35 ([0-9a-f]{2} ){4} *       pushq  0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x8>
13  +[0-9a-f]+:    ff 25 ([0-9a-f]{2} ){4} *       jmpq   \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x10>
14  +[0-9a-f]+:    0f 1f 40 00             nopl   0x0\(%rax\)
16 [0-9a-f]+ <fn1@plt>:
17  +[0-9a-f]+:    ff 25 ([0-9a-f]{2} ){4} *       jmpq   \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x18>
18  +[0-9a-f]+:    68 00 00 00 00          pushq  \$0x0
19  +[0-9a-f]+:    e9 ([0-9a-f]{2} ){4} *  jmpq   [0-9a-f]+ <fn1@plt-0x10>
21 [0-9a-f]+ <fn2@plt>:
22  +[0-9a-f]+:    ff 25 ([0-9a-f]{2} ){4} *       jmpq   \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x20>
23  +[0-9a-f]+:    68 01 00 00 00          pushq  \$0x1
24  +[0-9a-f]+:    e9 ([0-9a-f]{2} ){4} *  jmpq   [0-9a-f]+ <fn1@plt-0x10>