sim/cris/semcrisv32f-switch.c

   1 /* Simulator instruction semantics for crisv32f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2007 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { CRISV32F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { CRISV32F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { CRISV32F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { CRISV32F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { CRISV32F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { CRISV32F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { CRISV32F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
  42     { CRISV32F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
  43     { CRISV32F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
  44     { CRISV32F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
  45     { CRISV32F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
  46     { CRISV32F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
  47     { CRISV32F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
  48     { CRISV32F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
  49     { CRISV32F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
  50     { CRISV32F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
  51     { CRISV32F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
  52     { CRISV32F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
  53     { CRISV32F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
  54     { CRISV32F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
  55     { CRISV32F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
  56     { CRISV32F_INSN_ADDQ, && case_sem_INSN_ADDQ },
  57     { CRISV32F_INSN_SUBQ, && case_sem_INSN_SUBQ },
  58     { CRISV32F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
  59     { CRISV32F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
  60     { CRISV32F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
  61     { CRISV32F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
  62     { CRISV32F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
  63     { CRISV32F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
  64     { CRISV32F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
  65     { CRISV32F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
  66     { CRISV32F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
  67     { CRISV32F_INSN_CMPQ, && case_sem_INSN_CMPQ },
  68     { CRISV32F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
  69     { CRISV32F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
  70     { CRISV32F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
  71     { CRISV32F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
  72     { CRISV32F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
  73     { CRISV32F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
  74     { CRISV32F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
  75     { CRISV32F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
  76     { CRISV32F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
  77     { CRISV32F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
  78     { CRISV32F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
  79     { CRISV32F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
  80     { CRISV32F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
  81     { CRISV32F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
  82     { CRISV32F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
  83     { CRISV32F_INSN_MOVE_R_SPRV32, && case_sem_INSN_MOVE_R_SPRV32 },
  84     { CRISV32F_INSN_MOVE_SPR_RV32, && case_sem_INSN_MOVE_SPR_RV32 },
  85     { CRISV32F_INSN_MOVE_M_SPRV32, && case_sem_INSN_MOVE_M_SPRV32 },
  86     { CRISV32F_INSN_MOVE_C_SPRV32_P2, && case_sem_INSN_MOVE_C_SPRV32_P2 },
  87     { CRISV32F_INSN_MOVE_C_SPRV32_P3, && case_sem_INSN_MOVE_C_SPRV32_P3 },
  88     { CRISV32F_INSN_MOVE_C_SPRV32_P5, && case_sem_INSN_MOVE_C_SPRV32_P5 },
  89     { CRISV32F_INSN_MOVE_C_SPRV32_P6, && case_sem_INSN_MOVE_C_SPRV32_P6 },
  90     { CRISV32F_INSN_MOVE_C_SPRV32_P7, && case_sem_INSN_MOVE_C_SPRV32_P7 },
  91     { CRISV32F_INSN_MOVE_C_SPRV32_P9, && case_sem_INSN_MOVE_C_SPRV32_P9 },
  92     { CRISV32F_INSN_MOVE_C_SPRV32_P10, && case_sem_INSN_MOVE_C_SPRV32_P10 },
  93     { CRISV32F_INSN_MOVE_C_SPRV32_P11, && case_sem_INSN_MOVE_C_SPRV32_P11 },
  94     { CRISV32F_INSN_MOVE_C_SPRV32_P12, && case_sem_INSN_MOVE_C_SPRV32_P12 },
  95     { CRISV32F_INSN_MOVE_C_SPRV32_P13, && case_sem_INSN_MOVE_C_SPRV32_P13 },
  96     { CRISV32F_INSN_MOVE_C_SPRV32_P14, && case_sem_INSN_MOVE_C_SPRV32_P14 },
  97     { CRISV32F_INSN_MOVE_C_SPRV32_P15, && case_sem_INSN_MOVE_C_SPRV32_P15 },
  98     { CRISV32F_INSN_MOVE_SPR_MV32, && case_sem_INSN_MOVE_SPR_MV32 },
  99     { CRISV32F_INSN_MOVE_SS_R, && case_sem_INSN_MOVE_SS_R },
 100     { CRISV32F_INSN_MOVE_R_SS, && case_sem_INSN_MOVE_R_SS },
 101     { CRISV32F_INSN_MOVEM_R_M_V32, && case_sem_INSN_MOVEM_R_M_V32 },
 102     { CRISV32F_INSN_MOVEM_M_R_V32, && case_sem_INSN_MOVEM_M_R_V32 },
 103     { CRISV32F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
 104     { CRISV32F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
 105     { CRISV32F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
 106     { CRISV32F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
 107     { CRISV32F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
 108     { CRISV32F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
 109     { CRISV32F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
 110     { CRISV32F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
 111     { CRISV32F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
 112     { CRISV32F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
 113     { CRISV32F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
 114     { CRISV32F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
 115     { CRISV32F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
 116     { CRISV32F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
 117     { CRISV32F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
 118     { CRISV32F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
 119     { CRISV32F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
 120     { CRISV32F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
 121     { CRISV32F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
 122     { CRISV32F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
 123     { CRISV32F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
 124     { CRISV32F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
 125     { CRISV32F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
 126     { CRISV32F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
 127     { CRISV32F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
 128     { CRISV32F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
 129     { CRISV32F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
 130     { CRISV32F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
 131     { CRISV32F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
 132     { CRISV32F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
 133     { CRISV32F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
 134     { CRISV32F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
 135     { CRISV32F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
 136     { CRISV32F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
 137     { CRISV32F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
 138     { CRISV32F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
 139     { CRISV32F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
 140     { CRISV32F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
 141     { CRISV32F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
 142     { CRISV32F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
 143     { CRISV32F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
 144     { CRISV32F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
 145     { CRISV32F_INSN_ADDC_R, && case_sem_INSN_ADDC_R },
 146     { CRISV32F_INSN_ADDC_M, && case_sem_INSN_ADDC_M },
 147     { CRISV32F_INSN_ADDC_C, && case_sem_INSN_ADDC_C },
 148     { CRISV32F_INSN_LAPC_D, && case_sem_INSN_LAPC_D },
 149     { CRISV32F_INSN_LAPCQ, && case_sem_INSN_LAPCQ },
 150     { CRISV32F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
 151     { CRISV32F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
 152     { CRISV32F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
 153     { CRISV32F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
 154     { CRISV32F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
 155     { CRISV32F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
 156     { CRISV32F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
 157     { CRISV32F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
 158     { CRISV32F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
 159     { CRISV32F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
 160     { CRISV32F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
 161     { CRISV32F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
 162     { CRISV32F_INSN_MULS_B, && case_sem_INSN_MULS_B },
 163     { CRISV32F_INSN_MULS_W, && case_sem_INSN_MULS_W },
 164     { CRISV32F_INSN_MULS_D, && case_sem_INSN_MULS_D },
 165     { CRISV32F_INSN_MULU_B, && case_sem_INSN_MULU_B },
 166     { CRISV32F_INSN_MULU_W, && case_sem_INSN_MULU_W },
 167     { CRISV32F_INSN_MULU_D, && case_sem_INSN_MULU_D },
 168     { CRISV32F_INSN_MCP, && case_sem_INSN_MCP },
 169     { CRISV32F_INSN_DSTEP, && case_sem_INSN_DSTEP },
 170     { CRISV32F_INSN_ABS, && case_sem_INSN_ABS },
 171     { CRISV32F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
 172     { CRISV32F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
 173     { CRISV32F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
 174     { CRISV32F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
 175     { CRISV32F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
 176     { CRISV32F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
 177     { CRISV32F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
 178     { CRISV32F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
 179     { CRISV32F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
 180     { CRISV32F_INSN_ANDQ, && case_sem_INSN_ANDQ },
 181     { CRISV32F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
 182     { CRISV32F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
 183     { CRISV32F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
 184     { CRISV32F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
 185     { CRISV32F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
 186     { CRISV32F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
 187     { CRISV32F_INSN_ORCBR, && case_sem_INSN_ORCBR },
 188     { CRISV32F_INSN_ORCWR, && case_sem_INSN_ORCWR },
 189     { CRISV32F_INSN_ORCDR, && case_sem_INSN_ORCDR },
 190     { CRISV32F_INSN_ORQ, && case_sem_INSN_ORQ },
 191     { CRISV32F_INSN_XOR, && case_sem_INSN_XOR },
 192     { CRISV32F_INSN_SWAP, && case_sem_INSN_SWAP },
 193     { CRISV32F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
 194     { CRISV32F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
 195     { CRISV32F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
 196     { CRISV32F_INSN_ASRQ, && case_sem_INSN_ASRQ },
 197     { CRISV32F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
 198     { CRISV32F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
 199     { CRISV32F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
 200     { CRISV32F_INSN_LSRQ, && case_sem_INSN_LSRQ },
 201     { CRISV32F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
 202     { CRISV32F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
 203     { CRISV32F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
 204     { CRISV32F_INSN_LSLQ, && case_sem_INSN_LSLQ },
 205     { CRISV32F_INSN_BTST, && case_sem_INSN_BTST },
 206     { CRISV32F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
 207     { CRISV32F_INSN_SETF, && case_sem_INSN_SETF },
 208     { CRISV32F_INSN_CLEARF, && case_sem_INSN_CLEARF },
 209     { CRISV32F_INSN_RFE, && case_sem_INSN_RFE },
 210     { CRISV32F_INSN_SFE, && case_sem_INSN_SFE },
 211     { CRISV32F_INSN_RFG, && case_sem_INSN_RFG },
 212     { CRISV32F_INSN_RFN, && case_sem_INSN_RFN },
 213     { CRISV32F_INSN_HALT, && case_sem_INSN_HALT },
 214     { CRISV32F_INSN_BCC_B, && case_sem_INSN_BCC_B },
 215     { CRISV32F_INSN_BA_B, && case_sem_INSN_BA_B },
 216     { CRISV32F_INSN_BCC_W, && case_sem_INSN_BCC_W },
 217     { CRISV32F_INSN_BA_W, && case_sem_INSN_BA_W },
 218     { CRISV32F_INSN_JAS_R, && case_sem_INSN_JAS_R },
 219     { CRISV32F_INSN_JAS_C, && case_sem_INSN_JAS_C },
 220     { CRISV32F_INSN_JUMP_P, && case_sem_INSN_JUMP_P },
 221     { CRISV32F_INSN_BAS_C, && case_sem_INSN_BAS_C },
 222     { CRISV32F_INSN_JASC_R, && case_sem_INSN_JASC_R },
 223     { CRISV32F_INSN_JASC_C, && case_sem_INSN_JASC_C },
 224     { CRISV32F_INSN_BASC_C, && case_sem_INSN_BASC_C },
 225     { CRISV32F_INSN_BREAK, && case_sem_INSN_BREAK },
 226     { CRISV32F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
 227     { CRISV32F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
 228     { CRISV32F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
 229     { CRISV32F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
 230     { CRISV32F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
 231     { CRISV32F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
 232     { CRISV32F_INSN_SCC, && case_sem_INSN_SCC },
 233     { CRISV32F_INSN_LZ, && case_sem_INSN_LZ },
 234     { CRISV32F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
 235     { CRISV32F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
 236     { CRISV32F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
 237     { CRISV32F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
 238     { CRISV32F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
 239     { CRISV32F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
 240     { CRISV32F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
 241     { CRISV32F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
 242     { CRISV32F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
 243     { CRISV32F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
 244     { CRISV32F_INSN_FIDXI, && case_sem_INSN_FIDXI },
 245     { CRISV32F_INSN_FTAGI, && case_sem_INSN_FTAGI },
 246     { CRISV32F_INSN_FIDXD, && case_sem_INSN_FIDXD },
 247     { CRISV32F_INSN_FTAGD, && case_sem_INSN_FTAGD },
 248     { 0, 0 }
 249   };
 250   int i;
 251
 252   for (i = 0; labels[i].label != 0; ++i)
 253     {
 254 #if FAST_P
 255       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 256 #else
 257       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 258 #endif
 259     }
 260
 261 #undef DEFINE_LABELS
 262 #endif /* DEFINE_LABELS */
 263
 264 #ifdef DEFINE_SWITCH
 265
 266 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 267    off frills like tracing and profiling.  */
 268 /* FIXME: A better way would be to have TRACE_RESULT check for something
 269    that can cause it to be optimized out.  Another way would be to emit
 270    special handlers into the instruction "stream".  */
 271
 272 #if FAST_P
 273 #undef TRACE_RESULT
 274 #define TRACE_RESULT(cpu, abuf, name, type, val)
 275 #endif
 276
 277 #undef GET_ATTR
 278 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 279 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 280 #else
 281 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
 282 #endif
 283
 284 {
 285
 286 #if WITH_SCACHE_PBB
 287
 288 /* Branch to next handler without going around main loop.  */
 289 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 290 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 291
 292 #else /* ! WITH_SCACHE_PBB */
 293
 294 #define NEXT(vpc) BREAK (sem)
 295 #ifdef __GNUC__
 296 #if FAST_P
 297   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 298 #else
 299   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 300 #endif
 301 #else
 302   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 303 #endif
 304
 305 #endif /* ! WITH_SCACHE_PBB */
 306
 307     {
 308
 309   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 310 {
 311   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 312   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 313 #define FLD(f) abuf->fields.fmt_empty.f
 314   int UNUSED written = 0;
 315   IADDR UNUSED pc = abuf->addr;
 316   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 317
 318   {
 319     /* Update the recorded pc in the cpu state struct.
 320        Only necessary for WITH_SCACHE case, but to avoid the
 321        conditional compilation ....  */
 322     SET_H_PC (pc);
 323     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 324        using the default-insn-bitsize spec.  When executing insns in parallel
 325        we may want to queue the fault and continue execution.  */
 326     vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 327     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 328   }
 329
 330 #undef FLD
 331 }
 332   NEXT (vpc);
 333
 334   CASE (sem, INSN_X_AFTER) : /* --after-- */
 335 {
 336   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 337   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 338 #define FLD(f) abuf->fields.fmt_empty.f
 339   int UNUSED written = 0;
 340   IADDR UNUSED pc = abuf->addr;
 341   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 342
 343   {
 344 #if WITH_SCACHE_PBB_CRISV32F
 345     crisv32f_pbb_after (current_cpu, sem_arg);
 346 #endif
 347   }
 348
 349 #undef FLD
 350 }
 351   NEXT (vpc);
 352
 353   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 354 {
 355   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 356   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 357 #define FLD(f) abuf->fields.fmt_empty.f
 358   int UNUSED written = 0;
 359   IADDR UNUSED pc = abuf->addr;
 360   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 361
 362   {
 363 #if WITH_SCACHE_PBB_CRISV32F
 364     crisv32f_pbb_before (current_cpu, sem_arg);
 365 #endif
 366   }
 367
 368 #undef FLD
 369 }
 370   NEXT (vpc);
 371
 372   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 373 {
 374   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 375   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 376 #define FLD(f) abuf->fields.fmt_empty.f
 377   int UNUSED written = 0;
 378   IADDR UNUSED pc = abuf->addr;
 379   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 380
 381   {
 382 #if WITH_SCACHE_PBB_CRISV32F
 383 #ifdef DEFINE_SWITCH
 384     vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
 385                                pbb_br_type, pbb_br_npc);
 386     BREAK (sem);
 387 #else
 388     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 389     vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
 390                                CPU_PBB_BR_TYPE (current_cpu),
 391                                CPU_PBB_BR_NPC (current_cpu));
 392 #endif
 393 #endif
 394   }
 395
 396 #undef FLD
 397 }
 398   NEXT (vpc);
 399
 400   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 401 {
 402   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 403   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 404 #define FLD(f) abuf->fields.fmt_empty.f
 405   int UNUSED written = 0;
 406   IADDR UNUSED pc = abuf->addr;
 407   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 408
 409   {
 410 #if WITH_SCACHE_PBB_CRISV32F
 411     vpc = crisv32f_pbb_chain (current_cpu, sem_arg);
 412 #ifdef DEFINE_SWITCH
 413     BREAK (sem);
 414 #endif
 415 #endif
 416   }
 417
 418 #undef FLD
 419 }
 420   NEXT (vpc);
 421
 422   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 423 {
 424   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 425   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 426 #define FLD(f) abuf->fields.fmt_empty.f
 427   int UNUSED written = 0;
 428   IADDR UNUSED pc = abuf->addr;
 429   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 430
 431   {
 432 #if WITH_SCACHE_PBB_CRISV32F
 433 #if defined DEFINE_SWITCH || defined FAST_P
 434     /* In the switch case FAST_P is a constant, allowing several optimizations
 435        in any called inline functions.  */
 436     vpc = crisv32f_pbb_begin (current_cpu, FAST_P);
 437 #else
 438 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 439     vpc = crisv32f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 440 #else
 441     vpc = crisv32f_pbb_begin (current_cpu, 0);
 442 #endif
 443 #endif
 444 #endif
 445   }
 446
 447 #undef FLD
 448 }
 449   NEXT (vpc);
 450
 451   CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
 452 {
 453   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 454   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 455 #define FLD(f) abuf->fields.sfmt_addc_m.f
 456   int UNUSED written = 0;
 457   IADDR UNUSED pc = abuf->addr;
 458   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 459
 460 {
 461   QI tmp_newval;
 462   tmp_newval = GET_H_GR (FLD (f_operand1));
 463 {
 464   SI tmp_oldregval;
 465   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 466   {
 467     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 468     SET_H_GR (FLD (f_operand2), opval);
 469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 470   }
 471 }
 472 {
 473   {
 474     BI opval = LTQI (tmp_newval, 0);
 475     CPU (h_nbit) = opval;
 476     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 477   }
 478   {
 479     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 480     CPU (h_zbit) = opval;
 481     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 482   }
 483 SET_H_CBIT_MOVE (0);
 484 SET_H_VBIT_MOVE (0);
 485 {
 486   {
 487     BI opval = 0;
 488     CPU (h_xbit) = opval;
 489     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 490   }
 491   {
 492     BI opval = 0;
 493     SET_H_INSN_PREFIXED_P (opval);
 494     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 495   }
 496 }
 497 }
 498 }
 499
 500 #undef FLD
 501 }
 502   NEXT (vpc);
 503
 504   CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
 505 {
 506   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 507   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 508 #define FLD(f) abuf->fields.sfmt_addc_m.f
 509   int UNUSED written = 0;
 510   IADDR UNUSED pc = abuf->addr;
 511   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 512
 513 {
 514   HI tmp_newval;
 515   tmp_newval = GET_H_GR (FLD (f_operand1));
 516 {
 517   SI tmp_oldregval;
 518   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 519   {
 520     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 521     SET_H_GR (FLD (f_operand2), opval);
 522     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 523   }
 524 }
 525 {
 526   {
 527     BI opval = LTHI (tmp_newval, 0);
 528     CPU (h_nbit) = opval;
 529     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 530   }
 531   {
 532     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 533     CPU (h_zbit) = opval;
 534     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 535   }
 536 SET_H_CBIT_MOVE (0);
 537 SET_H_VBIT_MOVE (0);
 538 {
 539   {
 540     BI opval = 0;
 541     CPU (h_xbit) = opval;
 542     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 543   }
 544   {
 545     BI opval = 0;
 546     SET_H_INSN_PREFIXED_P (opval);
 547     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 548   }
 549 }
 550 }
 551 }
 552
 553 #undef FLD
 554 }
 555   NEXT (vpc);
 556
 557   CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
 558 {
 559   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 560   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 561 #define FLD(f) abuf->fields.sfmt_addc_m.f
 562   int UNUSED written = 0;
 563   IADDR UNUSED pc = abuf->addr;
 564   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 565
 566 {
 567   SI tmp_newval;
 568   tmp_newval = GET_H_GR (FLD (f_operand1));
 569   {
 570     SI opval = tmp_newval;
 571     SET_H_GR (FLD (f_operand2), opval);
 572     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 573   }
 574 {
 575   {
 576     BI opval = LTSI (tmp_newval, 0);
 577     CPU (h_nbit) = opval;
 578     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 579   }
 580   {
 581     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 582     CPU (h_zbit) = opval;
 583     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 584   }
 585 SET_H_CBIT_MOVE (0);
 586 SET_H_VBIT_MOVE (0);
 587 {
 588   {
 589     BI opval = 0;
 590     CPU (h_xbit) = opval;
 591     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 592   }
 593   {
 594     BI opval = 0;
 595     SET_H_INSN_PREFIXED_P (opval);
 596     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 597   }
 598 }
 599 }
 600 }
 601
 602 #undef FLD
 603 }
 604   NEXT (vpc);
 605
 606   CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
 607 {
 608   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 609   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 610 #define FLD(f) abuf->fields.sfmt_moveq.f
 611   int UNUSED written = 0;
 612   IADDR UNUSED pc = abuf->addr;
 613   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 614
 615 {
 616   SI tmp_newval;
 617   tmp_newval = FLD (f_s6);
 618   {
 619     SI opval = tmp_newval;
 620     SET_H_GR (FLD (f_operand2), opval);
 621     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 622   }
 623 {
 624 SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
 625 SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
 626 SET_H_CBIT_MOVE (0);
 627 SET_H_VBIT_MOVE (0);
 628 {
 629   {
 630     BI opval = 0;
 631     CPU (h_xbit) = opval;
 632     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 633   }
 634   {
 635     BI opval = 0;
 636     SET_H_INSN_PREFIXED_P (opval);
 637     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 638   }
 639 }
 640 }
 641 }
 642
 643 #undef FLD
 644 }
 645   NEXT (vpc);
 646
 647   CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
 648 {
 649   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 650   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 651 #define FLD(f) abuf->fields.sfmt_muls_b.f
 652   int UNUSED written = 0;
 653   IADDR UNUSED pc = abuf->addr;
 654   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 655
 656 {
 657   QI tmp_tmpops;
 658   SI tmp_newval;
 659   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 660   tmp_newval = EXTQISI (tmp_tmpops);
 661   {
 662     SI opval = tmp_newval;
 663     SET_H_GR (FLD (f_operand2), opval);
 664     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 665   }
 666 {
 667   {
 668     BI opval = LTSI (tmp_newval, 0);
 669     CPU (h_nbit) = opval;
 670     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 671   }
 672   {
 673     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 674     CPU (h_zbit) = opval;
 675     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 676   }
 677 SET_H_CBIT_MOVE (0);
 678 SET_H_VBIT_MOVE (0);
 679 {
 680   {
 681     BI opval = 0;
 682     CPU (h_xbit) = opval;
 683     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 684   }
 685   {
 686     BI opval = 0;
 687     SET_H_INSN_PREFIXED_P (opval);
 688     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 689   }
 690 }
 691 }
 692 }
 693
 694 #undef FLD
 695 }
 696   NEXT (vpc);
 697
 698   CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
 699 {
 700   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 701   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 702 #define FLD(f) abuf->fields.sfmt_muls_b.f
 703   int UNUSED written = 0;
 704   IADDR UNUSED pc = abuf->addr;
 705   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 706
 707 {
 708   HI tmp_tmpops;
 709   SI tmp_newval;
 710   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 711   tmp_newval = EXTHISI (tmp_tmpops);
 712   {
 713     SI opval = tmp_newval;
 714     SET_H_GR (FLD (f_operand2), opval);
 715     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 716   }
 717 {
 718   {
 719     BI opval = LTSI (tmp_newval, 0);
 720     CPU (h_nbit) = opval;
 721     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 722   }
 723   {
 724     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 725     CPU (h_zbit) = opval;
 726     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 727   }
 728 SET_H_CBIT_MOVE (0);
 729 SET_H_VBIT_MOVE (0);
 730 {
 731   {
 732     BI opval = 0;
 733     CPU (h_xbit) = opval;
 734     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 735   }
 736   {
 737     BI opval = 0;
 738     SET_H_INSN_PREFIXED_P (opval);
 739     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 740   }
 741 }
 742 }
 743 }
 744
 745 #undef FLD
 746 }
 747   NEXT (vpc);
 748
 749   CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
 750 {
 751   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 752   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 753 #define FLD(f) abuf->fields.sfmt_muls_b.f
 754   int UNUSED written = 0;
 755   IADDR UNUSED pc = abuf->addr;
 756   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 757
 758 {
 759   QI tmp_tmpops;
 760   SI tmp_newval;
 761   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 762   tmp_newval = ZEXTQISI (tmp_tmpops);
 763   {
 764     SI opval = tmp_newval;
 765     SET_H_GR (FLD (f_operand2), opval);
 766     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 767   }
 768 {
 769   {
 770     BI opval = LTSI (tmp_newval, 0);
 771     CPU (h_nbit) = opval;
 772     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 773   }
 774   {
 775     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 776     CPU (h_zbit) = opval;
 777     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 778   }
 779 SET_H_CBIT_MOVE (0);
 780 SET_H_VBIT_MOVE (0);
 781 {
 782   {
 783     BI opval = 0;
 784     CPU (h_xbit) = opval;
 785     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 786   }
 787   {
 788     BI opval = 0;
 789     SET_H_INSN_PREFIXED_P (opval);
 790     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 791   }
 792 }
 793 }
 794 }
 795
 796 #undef FLD
 797 }
 798   NEXT (vpc);
 799
 800   CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
 801 {
 802   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 803   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 804 #define FLD(f) abuf->fields.sfmt_muls_b.f
 805   int UNUSED written = 0;
 806   IADDR UNUSED pc = abuf->addr;
 807   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 808
 809 {
 810   HI tmp_tmpops;
 811   SI tmp_newval;
 812   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 813   tmp_newval = ZEXTHISI (tmp_tmpops);
 814   {
 815     SI opval = tmp_newval;
 816     SET_H_GR (FLD (f_operand2), opval);
 817     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 818   }
 819 {
 820   {
 821     BI opval = LTSI (tmp_newval, 0);
 822     CPU (h_nbit) = opval;
 823     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 824   }
 825   {
 826     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 827     CPU (h_zbit) = opval;
 828     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 829   }
 830 SET_H_CBIT_MOVE (0);
 831 SET_H_VBIT_MOVE (0);
 832 {
 833   {
 834     BI opval = 0;
 835     CPU (h_xbit) = opval;
 836     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 837   }
 838   {
 839     BI opval = 0;
 840     SET_H_INSN_PREFIXED_P (opval);
 841     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 842   }
 843 }
 844 }
 845 }
 846
 847 #undef FLD
 848 }
 849   NEXT (vpc);
 850
 851   CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
 852 {
 853   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 854   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 855 #define FLD(f) abuf->fields.sfmt_addcbr.f
 856   int UNUSED written = 0;
 857   IADDR UNUSED pc = abuf->addr;
 858   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 859
 860 {
 861   QI tmp_newval;
 862   tmp_newval = FLD (f_indir_pc__byte);
 863 {
 864   SI tmp_oldregval;
 865   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 866   {
 867     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 868     SET_H_GR (FLD (f_operand2), opval);
 869     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 870   }
 871 }
 872 {
 873   {
 874     BI opval = LTQI (tmp_newval, 0);
 875     CPU (h_nbit) = opval;
 876     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 877   }
 878   {
 879     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 880     CPU (h_zbit) = opval;
 881     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 882   }
 883 SET_H_CBIT_MOVE (0);
 884 SET_H_VBIT_MOVE (0);
 885 {
 886   {
 887     BI opval = 0;
 888     CPU (h_xbit) = opval;
 889     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 890   }
 891   {
 892     BI opval = 0;
 893     SET_H_INSN_PREFIXED_P (opval);
 894     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 895   }
 896 }
 897 }
 898 }
 899
 900 #undef FLD
 901 }
 902   NEXT (vpc);
 903
 904   CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
 905 {
 906   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 907   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 908 #define FLD(f) abuf->fields.sfmt_addcwr.f
 909   int UNUSED written = 0;
 910   IADDR UNUSED pc = abuf->addr;
 911   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 912
 913 {
 914   HI tmp_newval;
 915   tmp_newval = FLD (f_indir_pc__word);
 916 {
 917   SI tmp_oldregval;
 918   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 919   {
 920     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 921     SET_H_GR (FLD (f_operand2), opval);
 922     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 923   }
 924 }
 925 {
 926   {
 927     BI opval = LTHI (tmp_newval, 0);
 928     CPU (h_nbit) = opval;
 929     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 930   }
 931   {
 932     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 933     CPU (h_zbit) = opval;
 934     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 935   }
 936 SET_H_CBIT_MOVE (0);
 937 SET_H_VBIT_MOVE (0);
 938 {
 939   {
 940     BI opval = 0;
 941     CPU (h_xbit) = opval;
 942     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 943   }
 944   {
 945     BI opval = 0;
 946     SET_H_INSN_PREFIXED_P (opval);
 947     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 948   }
 949 }
 950 }
 951 }
 952
 953 #undef FLD
 954 }
 955   NEXT (vpc);
 956
 957   CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
 958 {
 959   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 960   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 961 #define FLD(f) abuf->fields.sfmt_bound_cd.f
 962   int UNUSED written = 0;
 963   IADDR UNUSED pc = abuf->addr;
 964   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
 965
 966 {
 967   SI tmp_newval;
 968   tmp_newval = FLD (f_indir_pc__dword);
 969   {
 970     SI opval = tmp_newval;
 971     SET_H_GR (FLD (f_operand2), opval);
 972     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 973   }
 974 {
 975   {
 976     BI opval = LTSI (tmp_newval, 0);
 977     CPU (h_nbit) = opval;
 978     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 979   }
 980   {
 981     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 982     CPU (h_zbit) = opval;
 983     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 984   }
 985 SET_H_CBIT_MOVE (0);
 986 SET_H_VBIT_MOVE (0);
 987 {
 988   {
 989     BI opval = 0;
 990     CPU (h_xbit) = opval;
 991     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 992   }
 993   {
 994     BI opval = 0;
 995     SET_H_INSN_PREFIXED_P (opval);
 996     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 997   }
 998 }
 999 }
1000 }
1001
1002 #undef FLD
1003 }
1004   NEXT (vpc);
1005
1006   CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
1007 {
1008   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1009   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1010 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1011   int UNUSED written = 0;
1012   IADDR UNUSED pc = abuf->addr;
1013   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1014
1015 {
1016   SI tmp_newval;
1017   tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1018   {
1019     SI opval = tmp_newval;
1020     SET_H_GR (FLD (f_operand2), opval);
1021     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1022   }
1023 {
1024   {
1025     BI opval = LTSI (tmp_newval, 0);
1026     CPU (h_nbit) = opval;
1027     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1028   }
1029   {
1030     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1031     CPU (h_zbit) = opval;
1032     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1033   }
1034 SET_H_CBIT_MOVE (0);
1035 SET_H_VBIT_MOVE (0);
1036 {
1037   {
1038     BI opval = 0;
1039     CPU (h_xbit) = opval;
1040     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1041   }
1042   {
1043     BI opval = 0;
1044     SET_H_INSN_PREFIXED_P (opval);
1045     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1046   }
1047 }
1048 }
1049 }
1050
1051 #undef FLD
1052 }
1053   NEXT (vpc);
1054
1055   CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
1056 {
1057   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1058   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1059 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1060   int UNUSED written = 0;
1061   IADDR UNUSED pc = abuf->addr;
1062   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1063
1064 {
1065   SI tmp_newval;
1066   tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1067   {
1068     SI opval = tmp_newval;
1069     SET_H_GR (FLD (f_operand2), opval);
1070     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1071   }
1072 {
1073   {
1074     BI opval = LTSI (tmp_newval, 0);
1075     CPU (h_nbit) = opval;
1076     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1077   }
1078   {
1079     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1080     CPU (h_zbit) = opval;
1081     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1082   }
1083 SET_H_CBIT_MOVE (0);
1084 SET_H_VBIT_MOVE (0);
1085 {
1086   {
1087     BI opval = 0;
1088     CPU (h_xbit) = opval;
1089     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1090   }
1091   {
1092     BI opval = 0;
1093     SET_H_INSN_PREFIXED_P (opval);
1094     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1095   }
1096 }
1097 }
1098 }
1099
1100 #undef FLD
1101 }
1102   NEXT (vpc);
1103
1104   CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
1105 {
1106   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1107   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1108 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1109   int UNUSED written = 0;
1110   IADDR UNUSED pc = abuf->addr;
1111   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1112
1113 {
1114   SI tmp_newval;
1115   tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1116   {
1117     SI opval = tmp_newval;
1118     SET_H_GR (FLD (f_operand2), opval);
1119     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1120   }
1121 {
1122   {
1123     BI opval = LTSI (tmp_newval, 0);
1124     CPU (h_nbit) = opval;
1125     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1126   }
1127   {
1128     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1129     CPU (h_zbit) = opval;
1130     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1131   }
1132 SET_H_CBIT_MOVE (0);
1133 SET_H_VBIT_MOVE (0);
1134 {
1135   {
1136     BI opval = 0;
1137     CPU (h_xbit) = opval;
1138     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1139   }
1140   {
1141     BI opval = 0;
1142     SET_H_INSN_PREFIXED_P (opval);
1143     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1144   }
1145 }
1146 }
1147 }
1148
1149 #undef FLD
1150 }
1151   NEXT (vpc);
1152
1153   CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
1154 {
1155   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1156   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1157 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1158   int UNUSED written = 0;
1159   IADDR UNUSED pc = abuf->addr;
1160   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1161
1162 {
1163   SI tmp_newval;
1164   tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1165   {
1166     SI opval = tmp_newval;
1167     SET_H_GR (FLD (f_operand2), opval);
1168     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1169   }
1170 {
1171   {
1172     BI opval = LTSI (tmp_newval, 0);
1173     CPU (h_nbit) = opval;
1174     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1175   }
1176   {
1177     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1178     CPU (h_zbit) = opval;
1179     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1180   }
1181 SET_H_CBIT_MOVE (0);
1182 SET_H_VBIT_MOVE (0);
1183 {
1184   {
1185     BI opval = 0;
1186     CPU (h_xbit) = opval;
1187     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1188   }
1189   {
1190     BI opval = 0;
1191     SET_H_INSN_PREFIXED_P (opval);
1192     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1193   }
1194 }
1195 }
1196 }
1197
1198 #undef FLD
1199 }
1200   NEXT (vpc);
1201
1202   CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
1203 {
1204   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1205   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1206 #define FLD(f) abuf->fields.sfmt_addq.f
1207   int UNUSED written = 0;
1208   IADDR UNUSED pc = abuf->addr;
1209   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1210
1211 {
1212   SI tmp_tmpopd;
1213   SI tmp_tmpops;
1214   BI tmp_carry;
1215   SI tmp_newval;
1216   tmp_tmpops = FLD (f_u6);
1217   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1218   tmp_carry = CPU (h_cbit);
1219   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1220   {
1221     SI opval = tmp_newval;
1222     SET_H_GR (FLD (f_operand2), opval);
1223     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1224   }
1225 {
1226   {
1227     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
1228     CPU (h_cbit) = opval;
1229     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1230   }
1231   {
1232     BI opval = LTSI (tmp_newval, 0);
1233     CPU (h_nbit) = opval;
1234     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1235   }
1236   {
1237     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1238     CPU (h_zbit) = opval;
1239     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1240   }
1241   {
1242     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1243     CPU (h_vbit) = opval;
1244     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1245   }
1246 {
1247   {
1248     BI opval = 0;
1249     CPU (h_xbit) = opval;
1250     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1251   }
1252   {
1253     BI opval = 0;
1254     SET_H_INSN_PREFIXED_P (opval);
1255     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1256   }
1257 }
1258 }
1259 }
1260
1261 #undef FLD
1262 }
1263   NEXT (vpc);
1264
1265   CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
1266 {
1267   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1268   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1269 #define FLD(f) abuf->fields.sfmt_addq.f
1270   int UNUSED written = 0;
1271   IADDR UNUSED pc = abuf->addr;
1272   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1273
1274 {
1275   SI tmp_tmpopd;
1276   SI tmp_tmpops;
1277   BI tmp_carry;
1278   SI tmp_newval;
1279   tmp_tmpops = FLD (f_u6);
1280   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1281   tmp_carry = CPU (h_cbit);
1282   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1283   {
1284     SI opval = tmp_newval;
1285     SET_H_GR (FLD (f_operand2), opval);
1286     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1287   }
1288 {
1289   {
1290     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1291     CPU (h_cbit) = opval;
1292     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1293   }
1294   {
1295     BI opval = LTSI (tmp_newval, 0);
1296     CPU (h_nbit) = opval;
1297     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1298   }
1299   {
1300     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1301     CPU (h_zbit) = opval;
1302     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1303   }
1304   {
1305     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1306     CPU (h_vbit) = opval;
1307     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1308   }
1309 {
1310   {
1311     BI opval = 0;
1312     CPU (h_xbit) = opval;
1313     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1314   }
1315   {
1316     BI opval = 0;
1317     SET_H_INSN_PREFIXED_P (opval);
1318     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1319   }
1320 }
1321 }
1322 }
1323
1324 #undef FLD
1325 }
1326   NEXT (vpc);
1327
1328   CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
1329 {
1330   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1331   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1332 #define FLD(f) abuf->fields.sfmt_muls_b.f
1333   int UNUSED written = 0;
1334   IADDR UNUSED pc = abuf->addr;
1335   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1336
1337 {
1338   QI tmp_tmpopd;
1339   QI tmp_tmpops;
1340   BI tmp_carry;
1341   QI tmp_newval;
1342   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1343   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1344   tmp_carry = CPU (h_cbit);
1345   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1346 ((void) 0); /*nop*/
1347 {
1348   {
1349     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1350     CPU (h_cbit) = opval;
1351     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1352   }
1353   {
1354     BI opval = LTQI (tmp_newval, 0);
1355     CPU (h_nbit) = opval;
1356     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1357   }
1358   {
1359     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1360     CPU (h_zbit) = opval;
1361     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1362   }
1363   {
1364     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1365     CPU (h_vbit) = opval;
1366     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1367   }
1368 {
1369   {
1370     BI opval = 0;
1371     CPU (h_xbit) = opval;
1372     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1373   }
1374   {
1375     BI opval = 0;
1376     SET_H_INSN_PREFIXED_P (opval);
1377     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1378   }
1379 }
1380 }
1381 }
1382
1383 #undef FLD
1384 }
1385   NEXT (vpc);
1386
1387   CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
1388 {
1389   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1390   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1391 #define FLD(f) abuf->fields.sfmt_muls_b.f
1392   int UNUSED written = 0;
1393   IADDR UNUSED pc = abuf->addr;
1394   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1395
1396 {
1397   HI tmp_tmpopd;
1398   HI tmp_tmpops;
1399   BI tmp_carry;
1400   HI tmp_newval;
1401   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1402   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1403   tmp_carry = CPU (h_cbit);
1404   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1405 ((void) 0); /*nop*/
1406 {
1407   {
1408     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1409     CPU (h_cbit) = opval;
1410     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1411   }
1412   {
1413     BI opval = LTHI (tmp_newval, 0);
1414     CPU (h_nbit) = opval;
1415     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1416   }
1417   {
1418     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1419     CPU (h_zbit) = opval;
1420     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1421   }
1422   {
1423     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1424     CPU (h_vbit) = opval;
1425     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1426   }
1427 {
1428   {
1429     BI opval = 0;
1430     CPU (h_xbit) = opval;
1431     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1432   }
1433   {
1434     BI opval = 0;
1435     SET_H_INSN_PREFIXED_P (opval);
1436     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1437   }
1438 }
1439 }
1440 }
1441
1442 #undef FLD
1443 }
1444   NEXT (vpc);
1445
1446   CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
1447 {
1448   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1449   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1450 #define FLD(f) abuf->fields.sfmt_muls_b.f
1451   int UNUSED written = 0;
1452   IADDR UNUSED pc = abuf->addr;
1453   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1454
1455 {
1456   SI tmp_tmpopd;
1457   SI tmp_tmpops;
1458   BI tmp_carry;
1459   SI tmp_newval;
1460   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1461   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1462   tmp_carry = CPU (h_cbit);
1463   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1464 ((void) 0); /*nop*/
1465 {
1466   {
1467     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1468     CPU (h_cbit) = opval;
1469     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1470   }
1471   {
1472     BI opval = LTSI (tmp_newval, 0);
1473     CPU (h_nbit) = opval;
1474     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1475   }
1476   {
1477     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1478     CPU (h_zbit) = opval;
1479     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1480   }
1481   {
1482     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1483     CPU (h_vbit) = opval;
1484     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1485   }
1486 {
1487   {
1488     BI opval = 0;
1489     CPU (h_xbit) = opval;
1490     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1491   }
1492   {
1493     BI opval = 0;
1494     SET_H_INSN_PREFIXED_P (opval);
1495     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1496   }
1497 }
1498 }
1499 }
1500
1501 #undef FLD
1502 }
1503   NEXT (vpc);
1504
1505   CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
1506 {
1507   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1508   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1509 #define FLD(f) abuf->fields.sfmt_addc_m.f
1510   int UNUSED written = 0;
1511   IADDR UNUSED pc = abuf->addr;
1512   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1513
1514 {
1515   QI tmp_tmpopd;
1516   QI tmp_tmpops;
1517   BI tmp_carry;
1518   QI tmp_newval;
1519   tmp_tmpops = ({   SI tmp_addr;
1520   QI tmp_tmp_mem;
1521   BI tmp_postinc;
1522   tmp_postinc = FLD (f_memmode);
1523 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1524 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1525 ; if (NEBI (tmp_postinc, 0)) {
1526 {
1527 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1528   tmp_addr = ADDSI (tmp_addr, 1);
1529 }
1530   {
1531     SI opval = tmp_addr;
1532     SET_H_GR (FLD (f_operand1), opval);
1533     written |= (1 << 9);
1534     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1535   }
1536 }
1537 }
1538 ; tmp_tmp_mem; });
1539   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1540   tmp_carry = CPU (h_cbit);
1541   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1542 ((void) 0); /*nop*/
1543 {
1544   {
1545     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1546     CPU (h_cbit) = opval;
1547     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1548   }
1549   {
1550     BI opval = LTQI (tmp_newval, 0);
1551     CPU (h_nbit) = opval;
1552     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1553   }
1554   {
1555     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1556     CPU (h_zbit) = opval;
1557     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1558   }
1559   {
1560     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1561     CPU (h_vbit) = opval;
1562     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1563   }
1564 {
1565   {
1566     BI opval = 0;
1567     CPU (h_xbit) = opval;
1568     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1569   }
1570   {
1571     BI opval = 0;
1572     SET_H_INSN_PREFIXED_P (opval);
1573     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1574   }
1575 }
1576 }
1577 }
1578
1579   abuf->written = written;
1580 #undef FLD
1581 }
1582   NEXT (vpc);
1583
1584   CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
1585 {
1586   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1587   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1588 #define FLD(f) abuf->fields.sfmt_addc_m.f
1589   int UNUSED written = 0;
1590   IADDR UNUSED pc = abuf->addr;
1591   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1592
1593 {
1594   HI tmp_tmpopd;
1595   HI tmp_tmpops;
1596   BI tmp_carry;
1597   HI tmp_newval;
1598   tmp_tmpops = ({   SI tmp_addr;
1599   HI tmp_tmp_mem;
1600   BI tmp_postinc;
1601   tmp_postinc = FLD (f_memmode);
1602 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1603 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
1604 ; if (NEBI (tmp_postinc, 0)) {
1605 {
1606 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1607   tmp_addr = ADDSI (tmp_addr, 2);
1608 }
1609   {
1610     SI opval = tmp_addr;
1611     SET_H_GR (FLD (f_operand1), opval);
1612     written |= (1 << 9);
1613     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1614   }
1615 }
1616 }
1617 ; tmp_tmp_mem; });
1618   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1619   tmp_carry = CPU (h_cbit);
1620   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1621 ((void) 0); /*nop*/
1622 {
1623   {
1624     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1625     CPU (h_cbit) = opval;
1626     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1627   }
1628   {
1629     BI opval = LTHI (tmp_newval, 0);
1630     CPU (h_nbit) = opval;
1631     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1632   }
1633   {
1634     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1635     CPU (h_zbit) = opval;
1636     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1637   }
1638   {
1639     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1640     CPU (h_vbit) = opval;
1641     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1642   }
1643 {
1644   {
1645     BI opval = 0;
1646     CPU (h_xbit) = opval;
1647     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1648   }
1649   {
1650     BI opval = 0;
1651     SET_H_INSN_PREFIXED_P (opval);
1652     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1653   }
1654 }
1655 }
1656 }
1657
1658   abuf->written = written;
1659 #undef FLD
1660 }
1661   NEXT (vpc);
1662
1663   CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
1664 {
1665   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1666   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1667 #define FLD(f) abuf->fields.sfmt_addc_m.f
1668   int UNUSED written = 0;
1669   IADDR UNUSED pc = abuf->addr;
1670   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1671
1672 {
1673   SI tmp_tmpopd;
1674   SI tmp_tmpops;
1675   BI tmp_carry;
1676   SI tmp_newval;
1677   tmp_tmpops = ({   SI tmp_addr;
1678   SI tmp_tmp_mem;
1679   BI tmp_postinc;
1680   tmp_postinc = FLD (f_memmode);
1681 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1682 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
1683 ; if (NEBI (tmp_postinc, 0)) {
1684 {
1685 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1686   tmp_addr = ADDSI (tmp_addr, 4);
1687 }
1688   {
1689     SI opval = tmp_addr;
1690     SET_H_GR (FLD (f_operand1), opval);
1691     written |= (1 << 9);
1692     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1693   }
1694 }
1695 }
1696 ; tmp_tmp_mem; });
1697   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1698   tmp_carry = CPU (h_cbit);
1699   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1700 ((void) 0); /*nop*/
1701 {
1702   {
1703     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1704     CPU (h_cbit) = opval;
1705     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1706   }
1707   {
1708     BI opval = LTSI (tmp_newval, 0);
1709     CPU (h_nbit) = opval;
1710     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1711   }
1712   {
1713     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1714     CPU (h_zbit) = opval;
1715     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1716   }
1717   {
1718     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1719     CPU (h_vbit) = opval;
1720     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1721   }
1722 {
1723   {
1724     BI opval = 0;
1725     CPU (h_xbit) = opval;
1726     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1727   }
1728   {
1729     BI opval = 0;
1730     SET_H_INSN_PREFIXED_P (opval);
1731     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1732   }
1733 }
1734 }
1735 }
1736
1737   abuf->written = written;
1738 #undef FLD
1739 }
1740   NEXT (vpc);
1741
1742   CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
1743 {
1744   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1745   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1746 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1747   int UNUSED written = 0;
1748   IADDR UNUSED pc = abuf->addr;
1749   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1750
1751 {
1752   QI tmp_tmpopd;
1753   QI tmp_tmpops;
1754   BI tmp_carry;
1755   QI tmp_newval;
1756   tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
1757   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1758   tmp_carry = CPU (h_cbit);
1759   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1760 ((void) 0); /*nop*/
1761 {
1762   {
1763     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1764     CPU (h_cbit) = opval;
1765     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1766   }
1767   {
1768     BI opval = LTQI (tmp_newval, 0);
1769     CPU (h_nbit) = opval;
1770     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1771   }
1772   {
1773     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1774     CPU (h_zbit) = opval;
1775     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1776   }
1777   {
1778     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1779     CPU (h_vbit) = opval;
1780     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1781   }
1782 {
1783   {
1784     BI opval = 0;
1785     CPU (h_xbit) = opval;
1786     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1787   }
1788   {
1789     BI opval = 0;
1790     SET_H_INSN_PREFIXED_P (opval);
1791     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1792   }
1793 }
1794 }
1795 }
1796
1797 #undef FLD
1798 }
1799   NEXT (vpc);
1800
1801   CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
1802 {
1803   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1804   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1805 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1806   int UNUSED written = 0;
1807   IADDR UNUSED pc = abuf->addr;
1808   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1809
1810 {
1811   HI tmp_tmpopd;
1812   HI tmp_tmpops;
1813   BI tmp_carry;
1814   HI tmp_newval;
1815   tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
1816   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1817   tmp_carry = CPU (h_cbit);
1818   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1819 ((void) 0); /*nop*/
1820 {
1821   {
1822     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1823     CPU (h_cbit) = opval;
1824     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1825   }
1826   {
1827     BI opval = LTHI (tmp_newval, 0);
1828     CPU (h_nbit) = opval;
1829     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1830   }
1831   {
1832     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1833     CPU (h_zbit) = opval;
1834     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1835   }
1836   {
1837     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1838     CPU (h_vbit) = opval;
1839     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1840   }
1841 {
1842   {
1843     BI opval = 0;
1844     CPU (h_xbit) = opval;
1845     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1846   }
1847   {
1848     BI opval = 0;
1849     SET_H_INSN_PREFIXED_P (opval);
1850     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1851   }
1852 }
1853 }
1854 }
1855
1856 #undef FLD
1857 }
1858   NEXT (vpc);
1859
1860   CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
1861 {
1862   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1863   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1864 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1865   int UNUSED written = 0;
1866   IADDR UNUSED pc = abuf->addr;
1867   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1868
1869 {
1870   SI tmp_tmpopd;
1871   SI tmp_tmpops;
1872   BI tmp_carry;
1873   SI tmp_newval;
1874   tmp_tmpops = FLD (f_indir_pc__dword);
1875   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1876   tmp_carry = CPU (h_cbit);
1877   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1878 ((void) 0); /*nop*/
1879 {
1880   {
1881     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1882     CPU (h_cbit) = opval;
1883     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1884   }
1885   {
1886     BI opval = LTSI (tmp_newval, 0);
1887     CPU (h_nbit) = opval;
1888     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1889   }
1890   {
1891     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1892     CPU (h_zbit) = opval;
1893     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1894   }
1895   {
1896     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1897     CPU (h_vbit) = opval;
1898     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1899   }
1900 {
1901   {
1902     BI opval = 0;
1903     CPU (h_xbit) = opval;
1904     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1905   }
1906   {
1907     BI opval = 0;
1908     SET_H_INSN_PREFIXED_P (opval);
1909     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1910   }
1911 }
1912 }
1913 }
1914
1915 #undef FLD
1916 }
1917   NEXT (vpc);
1918
1919   CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
1920 {
1921   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1922   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1923 #define FLD(f) abuf->fields.sfmt_andq.f
1924   int UNUSED written = 0;
1925   IADDR UNUSED pc = abuf->addr;
1926   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1927
1928 {
1929   SI tmp_tmpopd;
1930   SI tmp_tmpops;
1931   BI tmp_carry;
1932   SI tmp_newval;
1933   tmp_tmpops = FLD (f_s6);
1934   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1935   tmp_carry = CPU (h_cbit);
1936   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1937 ((void) 0); /*nop*/
1938 {
1939   {
1940     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1941     CPU (h_cbit) = opval;
1942     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1943   }
1944   {
1945     BI opval = LTSI (tmp_newval, 0);
1946     CPU (h_nbit) = opval;
1947     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1948   }
1949   {
1950     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1951     CPU (h_zbit) = opval;
1952     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1953   }
1954   {
1955     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1956     CPU (h_vbit) = opval;
1957     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1958   }
1959 {
1960   {
1961     BI opval = 0;
1962     CPU (h_xbit) = opval;
1963     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1964   }
1965   {
1966     BI opval = 0;
1967     SET_H_INSN_PREFIXED_P (opval);
1968     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1969   }
1970 }
1971 }
1972 }
1973
1974 #undef FLD
1975 }
1976   NEXT (vpc);
1977
1978   CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
1979 {
1980   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1981   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1982 #define FLD(f) abuf->fields.sfmt_addc_m.f
1983   int UNUSED written = 0;
1984   IADDR UNUSED pc = abuf->addr;
1985   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1986
1987 {
1988   SI tmp_tmpopd;
1989   SI tmp_tmpops;
1990   BI tmp_carry;
1991   SI tmp_newval;
1992   tmp_tmpops = EXTQISI (({   SI tmp_addr;
1993   QI tmp_tmp_mem;
1994   BI tmp_postinc;
1995   tmp_postinc = FLD (f_memmode);
1996 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1997 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1998 ; if (NEBI (tmp_postinc, 0)) {
1999 {
2000 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2001   tmp_addr = ADDSI (tmp_addr, 1);
2002 }
2003   {
2004     SI opval = tmp_addr;
2005     SET_H_GR (FLD (f_operand1), opval);
2006     written |= (1 << 9);
2007     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2008   }
2009 }
2010 }
2011 ; tmp_tmp_mem; }));
2012   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2013   tmp_carry = CPU (h_cbit);
2014   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2015 ((void) 0); /*nop*/
2016 {
2017   {
2018     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2019     CPU (h_cbit) = opval;
2020     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2021   }
2022   {
2023     BI opval = LTSI (tmp_newval, 0);
2024     CPU (h_nbit) = opval;
2025     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2026   }
2027   {
2028     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2029     CPU (h_zbit) = opval;
2030     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2031   }
2032   {
2033     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2034     CPU (h_vbit) = opval;
2035     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2036   }
2037 {
2038   {
2039     BI opval = 0;
2040     CPU (h_xbit) = opval;
2041     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2042   }
2043   {
2044     BI opval = 0;
2045     SET_H_INSN_PREFIXED_P (opval);
2046     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2047   }
2048 }
2049 }
2050 }
2051
2052   abuf->written = written;
2053 #undef FLD
2054 }
2055   NEXT (vpc);
2056
2057   CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
2058 {
2059   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2060   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2061 #define FLD(f) abuf->fields.sfmt_addc_m.f
2062   int UNUSED written = 0;
2063   IADDR UNUSED pc = abuf->addr;
2064   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2065
2066 {
2067   SI tmp_tmpopd;
2068   SI tmp_tmpops;
2069   BI tmp_carry;
2070   SI tmp_newval;
2071   tmp_tmpops = EXTHISI (({   SI tmp_addr;
2072   HI tmp_tmp_mem;
2073   BI tmp_postinc;
2074   tmp_postinc = FLD (f_memmode);
2075 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2076 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2077 ; if (NEBI (tmp_postinc, 0)) {
2078 {
2079 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2080   tmp_addr = ADDSI (tmp_addr, 2);
2081 }
2082   {
2083     SI opval = tmp_addr;
2084     SET_H_GR (FLD (f_operand1), opval);
2085     written |= (1 << 9);
2086     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2087   }
2088 }
2089 }
2090 ; tmp_tmp_mem; }));
2091   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2092   tmp_carry = CPU (h_cbit);
2093   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2094 ((void) 0); /*nop*/
2095 {
2096   {
2097     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2098     CPU (h_cbit) = opval;
2099     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2100   }
2101   {
2102     BI opval = LTSI (tmp_newval, 0);
2103     CPU (h_nbit) = opval;
2104     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2105   }
2106   {
2107     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2108     CPU (h_zbit) = opval;
2109     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2110   }
2111   {
2112     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2113     CPU (h_vbit) = opval;
2114     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2115   }
2116 {
2117   {
2118     BI opval = 0;
2119     CPU (h_xbit) = opval;
2120     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2121   }
2122   {
2123     BI opval = 0;
2124     SET_H_INSN_PREFIXED_P (opval);
2125     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2126   }
2127 }
2128 }
2129 }
2130
2131   abuf->written = written;
2132 #undef FLD
2133 }
2134   NEXT (vpc);
2135
2136   CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
2137 {
2138   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2139   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2140 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2141   int UNUSED written = 0;
2142   IADDR UNUSED pc = abuf->addr;
2143   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2144
2145 {
2146   SI tmp_tmpopd;
2147   SI tmp_tmpops;
2148   BI tmp_carry;
2149   SI tmp_newval;
2150   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2151   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2152   tmp_carry = CPU (h_cbit);
2153   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2154 ((void) 0); /*nop*/
2155 {
2156   {
2157     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2158     CPU (h_cbit) = opval;
2159     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2160   }
2161   {
2162     BI opval = LTSI (tmp_newval, 0);
2163     CPU (h_nbit) = opval;
2164     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2165   }
2166   {
2167     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2168     CPU (h_zbit) = opval;
2169     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2170   }
2171   {
2172     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2173     CPU (h_vbit) = opval;
2174     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2175   }
2176 {
2177   {
2178     BI opval = 0;
2179     CPU (h_xbit) = opval;
2180     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2181   }
2182   {
2183     BI opval = 0;
2184     SET_H_INSN_PREFIXED_P (opval);
2185     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2186   }
2187 }
2188 }
2189 }
2190
2191 #undef FLD
2192 }
2193   NEXT (vpc);
2194
2195   CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
2196 {
2197   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2198   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2199 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2200   int UNUSED written = 0;
2201   IADDR UNUSED pc = abuf->addr;
2202   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2203
2204 {
2205   SI tmp_tmpopd;
2206   SI tmp_tmpops;
2207   BI tmp_carry;
2208   SI tmp_newval;
2209   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2210   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2211   tmp_carry = CPU (h_cbit);
2212   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2213 ((void) 0); /*nop*/
2214 {
2215   {
2216     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2217     CPU (h_cbit) = opval;
2218     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2219   }
2220   {
2221     BI opval = LTSI (tmp_newval, 0);
2222     CPU (h_nbit) = opval;
2223     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2224   }
2225   {
2226     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2227     CPU (h_zbit) = opval;
2228     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2229   }
2230   {
2231     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2232     CPU (h_vbit) = opval;
2233     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2234   }
2235 {
2236   {
2237     BI opval = 0;
2238     CPU (h_xbit) = opval;
2239     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2240   }
2241   {
2242     BI opval = 0;
2243     SET_H_INSN_PREFIXED_P (opval);
2244     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2245   }
2246 }
2247 }
2248 }
2249
2250 #undef FLD
2251 }
2252   NEXT (vpc);
2253
2254   CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
2255 {
2256   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2257   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2258 #define FLD(f) abuf->fields.sfmt_addc_m.f
2259   int UNUSED written = 0;
2260   IADDR UNUSED pc = abuf->addr;
2261   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2262
2263 {
2264   SI tmp_tmpopd;
2265   SI tmp_tmpops;
2266   BI tmp_carry;
2267   SI tmp_newval;
2268   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
2269   QI tmp_tmp_mem;
2270   BI tmp_postinc;
2271   tmp_postinc = FLD (f_memmode);
2272 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2273 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2274 ; if (NEBI (tmp_postinc, 0)) {
2275 {
2276 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2277   tmp_addr = ADDSI (tmp_addr, 1);
2278 }
2279   {
2280     SI opval = tmp_addr;
2281     SET_H_GR (FLD (f_operand1), opval);
2282     written |= (1 << 9);
2283     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2284   }
2285 }
2286 }
2287 ; tmp_tmp_mem; }));
2288   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2289   tmp_carry = CPU (h_cbit);
2290   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2291 ((void) 0); /*nop*/
2292 {
2293   {
2294     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2295     CPU (h_cbit) = opval;
2296     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2297   }
2298   {
2299     BI opval = LTSI (tmp_newval, 0);
2300     CPU (h_nbit) = opval;
2301     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2302   }
2303   {
2304     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2305     CPU (h_zbit) = opval;
2306     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2307   }
2308   {
2309     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2310     CPU (h_vbit) = opval;
2311     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2312   }
2313 {
2314   {
2315     BI opval = 0;
2316     CPU (h_xbit) = opval;
2317     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2318   }
2319   {
2320     BI opval = 0;
2321     SET_H_INSN_PREFIXED_P (opval);
2322     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2323   }
2324 }
2325 }
2326 }
2327
2328   abuf->written = written;
2329 #undef FLD
2330 }
2331   NEXT (vpc);
2332
2333   CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
2334 {
2335   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2336   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2337 #define FLD(f) abuf->fields.sfmt_addc_m.f
2338   int UNUSED written = 0;
2339   IADDR UNUSED pc = abuf->addr;
2340   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2341
2342 {
2343   SI tmp_tmpopd;
2344   SI tmp_tmpops;
2345   BI tmp_carry;
2346   SI tmp_newval;
2347   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
2348   HI tmp_tmp_mem;
2349   BI tmp_postinc;
2350   tmp_postinc = FLD (f_memmode);
2351 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2352 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2353 ; if (NEBI (tmp_postinc, 0)) {
2354 {
2355 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2356   tmp_addr = ADDSI (tmp_addr, 2);
2357 }
2358   {
2359     SI opval = tmp_addr;
2360     SET_H_GR (FLD (f_operand1), opval);
2361     written |= (1 << 9);
2362     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2363   }
2364 }
2365 }
2366 ; tmp_tmp_mem; }));
2367   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2368   tmp_carry = CPU (h_cbit);
2369   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2370 ((void) 0); /*nop*/
2371 {
2372   {
2373     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2374     CPU (h_cbit) = opval;
2375     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2376   }
2377   {
2378     BI opval = LTSI (tmp_newval, 0);
2379     CPU (h_nbit) = opval;
2380     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2381   }
2382   {
2383     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2384     CPU (h_zbit) = opval;
2385     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2386   }
2387   {
2388     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2389     CPU (h_vbit) = opval;
2390     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2391   }
2392 {
2393   {
2394     BI opval = 0;
2395     CPU (h_xbit) = opval;
2396     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2397   }
2398   {
2399     BI opval = 0;
2400     SET_H_INSN_PREFIXED_P (opval);
2401     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2402   }
2403 }
2404 }
2405 }
2406
2407   abuf->written = written;
2408 #undef FLD
2409 }
2410   NEXT (vpc);
2411
2412   CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
2413 {
2414   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2415   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2416 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2417   int UNUSED written = 0;
2418   IADDR UNUSED pc = abuf->addr;
2419   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2420
2421 {
2422   SI tmp_tmpopd;
2423   SI tmp_tmpops;
2424   BI tmp_carry;
2425   SI tmp_newval;
2426   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2427   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2428   tmp_carry = CPU (h_cbit);
2429   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2430 ((void) 0); /*nop*/
2431 {
2432   {
2433     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2434     CPU (h_cbit) = opval;
2435     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2436   }
2437   {
2438     BI opval = LTSI (tmp_newval, 0);
2439     CPU (h_nbit) = opval;
2440     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2441   }
2442   {
2443     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2444     CPU (h_zbit) = opval;
2445     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2446   }
2447   {
2448     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2449     CPU (h_vbit) = opval;
2450     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2451   }
2452 {
2453   {
2454     BI opval = 0;
2455     CPU (h_xbit) = opval;
2456     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2457   }
2458   {
2459     BI opval = 0;
2460     SET_H_INSN_PREFIXED_P (opval);
2461     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2462   }
2463 }
2464 }
2465 }
2466
2467 #undef FLD
2468 }
2469   NEXT (vpc);
2470
2471   CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
2472 {
2473   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2474   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2475 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2476   int UNUSED written = 0;
2477   IADDR UNUSED pc = abuf->addr;
2478   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2479
2480 {
2481   SI tmp_tmpopd;
2482   SI tmp_tmpops;
2483   BI tmp_carry;
2484   SI tmp_newval;
2485   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2486   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2487   tmp_carry = CPU (h_cbit);
2488   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2489 ((void) 0); /*nop*/
2490 {
2491   {
2492     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2493     CPU (h_cbit) = opval;
2494     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2495   }
2496   {
2497     BI opval = LTSI (tmp_newval, 0);
2498     CPU (h_nbit) = opval;
2499     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2500   }
2501   {
2502     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2503     CPU (h_zbit) = opval;
2504     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2505   }
2506   {
2507     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2508     CPU (h_vbit) = opval;
2509     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2510   }
2511 {
2512   {
2513     BI opval = 0;
2514     CPU (h_xbit) = opval;
2515     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2516   }
2517   {
2518     BI opval = 0;
2519     SET_H_INSN_PREFIXED_P (opval);
2520     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2521   }
2522 }
2523 }
2524 }
2525
2526 #undef FLD
2527 }
2528   NEXT (vpc);
2529
2530   CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
2531 {
2532   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2533   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2534 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2535   int UNUSED written = 0;
2536   IADDR UNUSED pc = abuf->addr;
2537   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2538
2539 {
2540   SI tmp_tmp;
2541   tmp_tmp = ({   SI tmp_addr;
2542   QI tmp_tmp_mem;
2543   BI tmp_postinc;
2544   tmp_postinc = FLD (f_memmode);
2545 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2546 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2547 ; if (NEBI (tmp_postinc, 0)) {
2548 {
2549 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2550   tmp_addr = ADDSI (tmp_addr, 1);
2551 }
2552   {
2553     SI opval = tmp_addr;
2554     SET_H_GR (FLD (f_operand1), opval);
2555     written |= (1 << 10);
2556     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2557   }
2558 }
2559 }
2560 ; tmp_tmp_mem; });
2561 {
2562   SI tmp_oldregval;
2563   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2564   {
2565     SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
2566     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2567     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2568   }
2569 }
2570 {
2571   {
2572     BI opval = LTQI (tmp_tmp, 0);
2573     CPU (h_nbit) = opval;
2574     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2575   }
2576   {
2577     BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2578     CPU (h_zbit) = opval;
2579     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2580   }
2581 SET_H_CBIT_MOVE (0);
2582 SET_H_VBIT_MOVE (0);
2583 {
2584   {
2585     BI opval = 0;
2586     CPU (h_xbit) = opval;
2587     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2588   }
2589   {
2590     BI opval = 0;
2591     SET_H_INSN_PREFIXED_P (opval);
2592     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2593   }
2594 }
2595 }
2596 }
2597
2598   abuf->written = written;
2599 #undef FLD
2600 }
2601   NEXT (vpc);
2602
2603   CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
2604 {
2605   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2606   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2607 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2608   int UNUSED written = 0;
2609   IADDR UNUSED pc = abuf->addr;
2610   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2611
2612 {
2613   SI tmp_tmp;
2614   tmp_tmp = ({   SI tmp_addr;
2615   HI tmp_tmp_mem;
2616   BI tmp_postinc;
2617   tmp_postinc = FLD (f_memmode);
2618 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2619 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2620 ; if (NEBI (tmp_postinc, 0)) {
2621 {
2622 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2623   tmp_addr = ADDSI (tmp_addr, 2);
2624 }
2625   {
2626     SI opval = tmp_addr;
2627     SET_H_GR (FLD (f_operand1), opval);
2628     written |= (1 << 10);
2629     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2630   }
2631 }
2632 }
2633 ; tmp_tmp_mem; });
2634 {
2635   SI tmp_oldregval;
2636   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2637   {
2638     SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
2639     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2640     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2641   }
2642 }
2643 {
2644   {
2645     BI opval = LTHI (tmp_tmp, 0);
2646     CPU (h_nbit) = opval;
2647     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2648   }
2649   {
2650     BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2651     CPU (h_zbit) = opval;
2652     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2653   }
2654 SET_H_CBIT_MOVE (0);
2655 SET_H_VBIT_MOVE (0);
2656 {
2657   {
2658     BI opval = 0;
2659     CPU (h_xbit) = opval;
2660     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2661   }
2662   {
2663     BI opval = 0;
2664     SET_H_INSN_PREFIXED_P (opval);
2665     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2666   }
2667 }
2668 }
2669 }
2670
2671   abuf->written = written;
2672 #undef FLD
2673 }
2674   NEXT (vpc);
2675
2676   CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
2677 {
2678   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2679   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2680 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2681   int UNUSED written = 0;
2682   IADDR UNUSED pc = abuf->addr;
2683   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2684
2685 {
2686   SI tmp_tmp;
2687   tmp_tmp = ({   SI tmp_addr;
2688   SI tmp_tmp_mem;
2689   BI tmp_postinc;
2690   tmp_postinc = FLD (f_memmode);
2691 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2692 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
2693 ; if (NEBI (tmp_postinc, 0)) {
2694 {
2695 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2696   tmp_addr = ADDSI (tmp_addr, 4);
2697 }
2698   {
2699     SI opval = tmp_addr;
2700     SET_H_GR (FLD (f_operand1), opval);
2701     written |= (1 << 9);
2702     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2703   }
2704 }
2705 }
2706 ; tmp_tmp_mem; });
2707   {
2708     SI opval = tmp_tmp;
2709     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2710     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2711   }
2712 {
2713   {
2714     BI opval = LTSI (tmp_tmp, 0);
2715     CPU (h_nbit) = opval;
2716     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2717   }
2718   {
2719     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2720     CPU (h_zbit) = opval;
2721     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2722   }
2723 SET_H_CBIT_MOVE (0);
2724 SET_H_VBIT_MOVE (0);
2725 {
2726   {
2727     BI opval = 0;
2728     CPU (h_xbit) = opval;
2729     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2730   }
2731   {
2732     BI opval = 0;
2733     SET_H_INSN_PREFIXED_P (opval);
2734     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2735   }
2736 }
2737 }
2738 }
2739
2740   abuf->written = written;
2741 #undef FLD
2742 }
2743   NEXT (vpc);
2744
2745   CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
2746 {
2747   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2748   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2749 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2750   int UNUSED written = 0;
2751   IADDR UNUSED pc = abuf->addr;
2752   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2753
2754 {
2755   SI tmp_tmp;
2756   tmp_tmp = EXTQISI (({   SI tmp_addr;
2757   QI tmp_tmp_mem;
2758   BI tmp_postinc;
2759   tmp_postinc = FLD (f_memmode);
2760 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2761 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2762 ; if (NEBI (tmp_postinc, 0)) {
2763 {
2764 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2765   tmp_addr = ADDSI (tmp_addr, 1);
2766 }
2767   {
2768     SI opval = tmp_addr;
2769     SET_H_GR (FLD (f_operand1), opval);
2770     written |= (1 << 8);
2771     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2772   }
2773 }
2774 }
2775 ; tmp_tmp_mem; }));
2776 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2777   {
2778     SI opval = tmp_tmp;
2779     SET_H_GR (FLD (f_operand1), opval);
2780     written |= (1 << 8);
2781     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2782   }
2783 } else {
2784   {
2785     SI opval = tmp_tmp;
2786     SET_H_GR (FLD (f_operand2), opval);
2787     written |= (1 << 7);
2788     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2789   }
2790 }
2791 {
2792   {
2793     BI opval = LTSI (tmp_tmp, 0);
2794     CPU (h_nbit) = opval;
2795     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2796   }
2797   {
2798     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2799     CPU (h_zbit) = opval;
2800     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2801   }
2802 SET_H_CBIT_MOVE (0);
2803 SET_H_VBIT_MOVE (0);
2804 {
2805   {
2806     BI opval = 0;
2807     CPU (h_xbit) = opval;
2808     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2809   }
2810   {
2811     BI opval = 0;
2812     SET_H_INSN_PREFIXED_P (opval);
2813     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2814   }
2815 }
2816 }
2817 }
2818
2819   abuf->written = written;
2820 #undef FLD
2821 }
2822   NEXT (vpc);
2823
2824   CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
2825 {
2826   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2827   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2828 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2829   int UNUSED written = 0;
2830   IADDR UNUSED pc = abuf->addr;
2831   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2832
2833 {
2834   SI tmp_tmp;
2835   tmp_tmp = EXTHISI (({   SI tmp_addr;
2836   HI tmp_tmp_mem;
2837   BI tmp_postinc;
2838   tmp_postinc = FLD (f_memmode);
2839 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2840 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2841 ; if (NEBI (tmp_postinc, 0)) {
2842 {
2843 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2844   tmp_addr = ADDSI (tmp_addr, 2);
2845 }
2846   {
2847     SI opval = tmp_addr;
2848     SET_H_GR (FLD (f_operand1), opval);
2849     written |= (1 << 8);
2850     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2851   }
2852 }
2853 }
2854 ; tmp_tmp_mem; }));
2855 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2856   {
2857     SI opval = tmp_tmp;
2858     SET_H_GR (FLD (f_operand1), opval);
2859     written |= (1 << 8);
2860     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2861   }
2862 } else {
2863   {
2864     SI opval = tmp_tmp;
2865     SET_H_GR (FLD (f_operand2), opval);
2866     written |= (1 << 7);
2867     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2868   }
2869 }
2870 {
2871   {
2872     BI opval = LTSI (tmp_tmp, 0);
2873     CPU (h_nbit) = opval;
2874     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2875   }
2876   {
2877     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2878     CPU (h_zbit) = opval;
2879     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2880   }
2881 SET_H_CBIT_MOVE (0);
2882 SET_H_VBIT_MOVE (0);
2883 {
2884   {
2885     BI opval = 0;
2886     CPU (h_xbit) = opval;
2887     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2888   }
2889   {
2890     BI opval = 0;
2891     SET_H_INSN_PREFIXED_P (opval);
2892     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2893   }
2894 }
2895 }
2896 }
2897
2898   abuf->written = written;
2899 #undef FLD
2900 }
2901   NEXT (vpc);
2902
2903   CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
2904 {
2905   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2906   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2907 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2908   int UNUSED written = 0;
2909   IADDR UNUSED pc = abuf->addr;
2910   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2911
2912 {
2913   SI tmp_tmp;
2914   tmp_tmp = ZEXTQISI (({   SI tmp_addr;
2915   QI tmp_tmp_mem;
2916   BI tmp_postinc;
2917   tmp_postinc = FLD (f_memmode);
2918 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2919 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2920 ; if (NEBI (tmp_postinc, 0)) {
2921 {
2922 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2923   tmp_addr = ADDSI (tmp_addr, 1);
2924 }
2925   {
2926     SI opval = tmp_addr;
2927     SET_H_GR (FLD (f_operand1), opval);
2928     written |= (1 << 8);
2929     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2930   }
2931 }
2932 }
2933 ; tmp_tmp_mem; }));
2934 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2935   {
2936     SI opval = tmp_tmp;
2937     SET_H_GR (FLD (f_operand1), opval);
2938     written |= (1 << 8);
2939     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2940   }
2941 } else {
2942   {
2943     SI opval = tmp_tmp;
2944     SET_H_GR (FLD (f_operand2), opval);
2945     written |= (1 << 7);
2946     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2947   }
2948 }
2949 {
2950   {
2951     BI opval = LTSI (tmp_tmp, 0);
2952     CPU (h_nbit) = opval;
2953     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2954   }
2955   {
2956     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2957     CPU (h_zbit) = opval;
2958     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2959   }
2960 SET_H_CBIT_MOVE (0);
2961 SET_H_VBIT_MOVE (0);
2962 {
2963   {
2964     BI opval = 0;
2965     CPU (h_xbit) = opval;
2966     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2967   }
2968   {
2969     BI opval = 0;
2970     SET_H_INSN_PREFIXED_P (opval);
2971     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2972   }
2973 }
2974 }
2975 }
2976
2977   abuf->written = written;
2978 #undef FLD
2979 }
2980   NEXT (vpc);
2981
2982   CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
2983 {
2984   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2985   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2986 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2987   int UNUSED written = 0;
2988   IADDR UNUSED pc = abuf->addr;
2989   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2990
2991 {
2992   SI tmp_tmp;
2993   tmp_tmp = ZEXTHISI (({   SI tmp_addr;
2994   HI tmp_tmp_mem;
2995   BI tmp_postinc;
2996   tmp_postinc = FLD (f_memmode);
2997 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2998 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2999 ; if (NEBI (tmp_postinc, 0)) {
3000 {
3001 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3002   tmp_addr = ADDSI (tmp_addr, 2);
3003 }
3004   {
3005     SI opval = tmp_addr;
3006     SET_H_GR (FLD (f_operand1), opval);
3007     written |= (1 << 8);
3008     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3009   }
3010 }
3011 }
3012 ; tmp_tmp_mem; }));
3013 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3014   {
3015     SI opval = tmp_tmp;
3016     SET_H_GR (FLD (f_operand1), opval);
3017     written |= (1 << 8);
3018     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3019   }
3020 } else {
3021   {
3022     SI opval = tmp_tmp;
3023     SET_H_GR (FLD (f_operand2), opval);
3024     written |= (1 << 7);
3025     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3026   }
3027 }
3028 {
3029   {
3030     BI opval = LTSI (tmp_tmp, 0);
3031     CPU (h_nbit) = opval;
3032     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3033   }
3034   {
3035     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3036     CPU (h_zbit) = opval;
3037     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3038   }
3039 SET_H_CBIT_MOVE (0);
3040 SET_H_VBIT_MOVE (0);
3041 {
3042   {
3043     BI opval = 0;
3044     CPU (h_xbit) = opval;
3045     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3046   }
3047   {
3048     BI opval = 0;
3049     SET_H_INSN_PREFIXED_P (opval);
3050     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3051   }
3052 }
3053 }
3054 }
3055
3056   abuf->written = written;
3057 #undef FLD
3058 }
3059   NEXT (vpc);
3060
3061   CASE (sem, INSN_MOVE_R_SPRV32) : /* move ${Rs},${Pd} */
3062 {
3063   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3064   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3065 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
3066   int UNUSED written = 0;
3067   IADDR UNUSED pc = abuf->addr;
3068   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3069
3070 {
3071   SI tmp_tmp;
3072   SI tmp_rno;
3073   tmp_tmp = GET_H_GR (FLD (f_operand1));
3074   tmp_rno = FLD (f_operand2);
3075 if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
3076 cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
3077 }
3078  else {
3079   {
3080     SI opval = tmp_tmp;
3081     SET_H_SR (FLD (f_operand2), opval);
3082     written |= (1 << 2);
3083     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3084   }
3085 }
3086 {
3087   {
3088     BI opval = 0;
3089     CPU (h_xbit) = opval;
3090     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3091   }
3092   {
3093     BI opval = 0;
3094     SET_H_INSN_PREFIXED_P (opval);
3095     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3096   }
3097 }
3098 }
3099
3100   abuf->written = written;
3101 #undef FLD
3102 }
3103   NEXT (vpc);
3104
3105   CASE (sem, INSN_MOVE_SPR_RV32) : /* move ${Ps},${Rd-sfield} */
3106 {
3107   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3108   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3109 #define FLD(f) abuf->fields.sfmt_mcp.f
3110   int UNUSED written = 0;
3111   IADDR UNUSED pc = abuf->addr;
3112   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3113
3114 {
3115   SI tmp_grno;
3116   SI tmp_prno;
3117   SI tmp_newval;
3118   tmp_prno = FLD (f_operand2);
3119   tmp_newval = GET_H_SR (FLD (f_operand2));
3120 if (EQSI (tmp_prno, 2)) {
3121   {
3122     SI opval = tmp_newval;
3123     SET_H_GR (FLD (f_operand1), opval);
3124     written |= (1 << 4);
3125     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3126   }
3127 }
3128  else if (EQSI (tmp_prno, 3)) {
3129 {
3130   SI tmp_oldregval;
3131   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3132   {
3133     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3134     SET_H_GR (FLD (f_operand1), opval);
3135     written |= (1 << 4);
3136     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3137   }
3138 }
3139 }
3140  else if (EQSI (tmp_prno, 5)) {
3141   {
3142     SI opval = tmp_newval;
3143     SET_H_GR (FLD (f_operand1), opval);
3144     written |= (1 << 4);
3145     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3146   }
3147 }
3148  else if (EQSI (tmp_prno, 6)) {
3149   {
3150     SI opval = tmp_newval;
3151     SET_H_GR (FLD (f_operand1), opval);
3152     written |= (1 << 4);
3153     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3154   }
3155 }
3156  else if (EQSI (tmp_prno, 7)) {
3157   {
3158     SI opval = tmp_newval;
3159     SET_H_GR (FLD (f_operand1), opval);
3160     written |= (1 << 4);
3161     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3162   }
3163 }
3164  else if (EQSI (tmp_prno, 9)) {
3165   {
3166     SI opval = tmp_newval;
3167     SET_H_GR (FLD (f_operand1), opval);
3168     written |= (1 << 4);
3169     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3170   }
3171 }
3172  else if (EQSI (tmp_prno, 10)) {
3173   {
3174     SI opval = tmp_newval;
3175     SET_H_GR (FLD (f_operand1), opval);
3176     written |= (1 << 4);
3177     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3178   }
3179 }
3180  else if (EQSI (tmp_prno, 11)) {
3181   {
3182     SI opval = tmp_newval;
3183     SET_H_GR (FLD (f_operand1), opval);
3184     written |= (1 << 4);
3185     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3186   }
3187 }
3188  else if (EQSI (tmp_prno, 12)) {
3189   {
3190     SI opval = tmp_newval;
3191     SET_H_GR (FLD (f_operand1), opval);
3192     written |= (1 << 4);
3193     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3194   }
3195 }
3196  else if (EQSI (tmp_prno, 13)) {
3197   {
3198     SI opval = tmp_newval;
3199     SET_H_GR (FLD (f_operand1), opval);
3200     written |= (1 << 4);
3201     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3202   }
3203 }
3204  else if (EQSI (tmp_prno, 14)) {
3205   {
3206     SI opval = tmp_newval;
3207     SET_H_GR (FLD (f_operand1), opval);
3208     written |= (1 << 4);
3209     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3210   }
3211 }
3212  else if (EQSI (tmp_prno, 15)) {
3213   {
3214     SI opval = tmp_newval;
3215     SET_H_GR (FLD (f_operand1), opval);
3216     written |= (1 << 4);
3217     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3218   }
3219 }
3220  else if (EQSI (tmp_prno, 0)) {
3221 {
3222   SI tmp_oldregval;
3223   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3224   {
3225     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3226     SET_H_GR (FLD (f_operand1), opval);
3227     written |= (1 << 4);
3228     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3229   }
3230 }
3231 }
3232  else if (EQSI (tmp_prno, 1)) {
3233 {
3234   SI tmp_oldregval;
3235   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3236   {
3237     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3238     SET_H_GR (FLD (f_operand1), opval);
3239     written |= (1 << 4);
3240     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3241   }
3242 }
3243 }
3244  else if (EQSI (tmp_prno, 4)) {
3245 {
3246   SI tmp_oldregval;
3247   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3248   {
3249     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3250     SET_H_GR (FLD (f_operand1), opval);
3251     written |= (1 << 4);
3252     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3253   }
3254 }
3255 }
3256  else if (EQSI (tmp_prno, 8)) {
3257   {
3258     SI opval = tmp_newval;
3259     SET_H_GR (FLD (f_operand1), opval);
3260     written |= (1 << 4);
3261     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3262   }
3263 }
3264  else {
3265 cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
3266 }
3267 {
3268   {
3269     BI opval = 0;
3270     CPU (h_xbit) = opval;
3271     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3272   }
3273   {
3274     BI opval = 0;
3275     SET_H_INSN_PREFIXED_P (opval);
3276     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3277   }
3278 }
3279 }
3280
3281   abuf->written = written;
3282 #undef FLD
3283 }
3284   NEXT (vpc);
3285
3286   CASE (sem, INSN_MOVE_M_SPRV32) : /* move [${Rs}${inc}],${Pd} */
3287 {
3288   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3289   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3290 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
3291   int UNUSED written = 0;
3292   IADDR UNUSED pc = abuf->addr;
3293   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3294
3295 {
3296   SI tmp_rno;
3297   SI tmp_newval;
3298   tmp_rno = FLD (f_operand2);
3299 if (EQSI (tmp_rno, 2)) {
3300   tmp_newval = ({   SI tmp_addr;
3301   SI tmp_tmp_mem;
3302   BI tmp_postinc;
3303   tmp_postinc = FLD (f_memmode);
3304 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3305 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3306 ; if (NEBI (tmp_postinc, 0)) {
3307 {
3308 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3309   tmp_addr = ADDSI (tmp_addr, 4);
3310 }
3311   {
3312     SI opval = tmp_addr;
3313     SET_H_GR (FLD (f_operand1), opval);
3314     written |= (1 << 8);
3315     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3316   }
3317 }
3318 }
3319 ; tmp_tmp_mem; });
3320 }
3321  else if (EQSI (tmp_rno, 3)) {
3322   tmp_newval = EXTQISI (({   SI tmp_addr;
3323   QI tmp_tmp_mem;
3324   BI tmp_postinc;
3325   tmp_postinc = FLD (f_memmode);
3326 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3327 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3328 ; if (NEBI (tmp_postinc, 0)) {
3329 {
3330 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3331   tmp_addr = ADDSI (tmp_addr, 1);
3332 }
3333   {
3334     SI opval = tmp_addr;
3335     SET_H_GR (FLD (f_operand1), opval);
3336     written |= (1 << 8);
3337     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3338   }
3339 }
3340 }
3341 ; tmp_tmp_mem; }));
3342 }
3343  else if (EQSI (tmp_rno, 5)) {
3344   tmp_newval = ({   SI tmp_addr;
3345   SI tmp_tmp_mem;
3346   BI tmp_postinc;
3347   tmp_postinc = FLD (f_memmode);
3348 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3349 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3350 ; if (NEBI (tmp_postinc, 0)) {
3351 {
3352 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3353   tmp_addr = ADDSI (tmp_addr, 4);
3354 }
3355   {
3356     SI opval = tmp_addr;
3357     SET_H_GR (FLD (f_operand1), opval);
3358     written |= (1 << 8);
3359     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3360   }
3361 }
3362 }
3363 ; tmp_tmp_mem; });
3364 }
3365  else if (EQSI (tmp_rno, 6)) {
3366   tmp_newval = ({   SI tmp_addr;
3367   SI tmp_tmp_mem;
3368   BI tmp_postinc;
3369   tmp_postinc = FLD (f_memmode);
3370 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3371 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3372 ; if (NEBI (tmp_postinc, 0)) {
3373 {
3374 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3375   tmp_addr = ADDSI (tmp_addr, 4);
3376 }
3377   {
3378     SI opval = tmp_addr;
3379     SET_H_GR (FLD (f_operand1), opval);
3380     written |= (1 << 8);
3381     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3382   }
3383 }
3384 }
3385 ; tmp_tmp_mem; });
3386 }
3387  else if (EQSI (tmp_rno, 7)) {
3388   tmp_newval = ({   SI tmp_addr;
3389   SI tmp_tmp_mem;
3390   BI tmp_postinc;
3391   tmp_postinc = FLD (f_memmode);
3392 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3393 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3394 ; if (NEBI (tmp_postinc, 0)) {
3395 {
3396 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3397   tmp_addr = ADDSI (tmp_addr, 4);
3398 }
3399   {
3400     SI opval = tmp_addr;
3401     SET_H_GR (FLD (f_operand1), opval);
3402     written |= (1 << 8);
3403     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3404   }
3405 }
3406 }
3407 ; tmp_tmp_mem; });
3408 }
3409  else if (EQSI (tmp_rno, 9)) {
3410   tmp_newval = ({   SI tmp_addr;
3411   SI tmp_tmp_mem;
3412   BI tmp_postinc;
3413   tmp_postinc = FLD (f_memmode);
3414 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3415 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3416 ; if (NEBI (tmp_postinc, 0)) {
3417 {
3418 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3419   tmp_addr = ADDSI (tmp_addr, 4);
3420 }
3421   {
3422     SI opval = tmp_addr;
3423     SET_H_GR (FLD (f_operand1), opval);
3424     written |= (1 << 8);
3425     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3426   }
3427 }
3428 }
3429 ; tmp_tmp_mem; });
3430 }
3431  else if (EQSI (tmp_rno, 10)) {
3432   tmp_newval = ({   SI tmp_addr;
3433   SI tmp_tmp_mem;
3434   BI tmp_postinc;
3435   tmp_postinc = FLD (f_memmode);
3436 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3437 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3438 ; if (NEBI (tmp_postinc, 0)) {
3439 {
3440 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3441   tmp_addr = ADDSI (tmp_addr, 4);
3442 }
3443   {
3444     SI opval = tmp_addr;
3445     SET_H_GR (FLD (f_operand1), opval);
3446     written |= (1 << 8);
3447     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3448   }
3449 }
3450 }
3451 ; tmp_tmp_mem; });
3452 }
3453  else if (EQSI (tmp_rno, 11)) {
3454   tmp_newval = ({   SI tmp_addr;
3455   SI tmp_tmp_mem;
3456   BI tmp_postinc;
3457   tmp_postinc = FLD (f_memmode);
3458 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3459 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3460 ; if (NEBI (tmp_postinc, 0)) {
3461 {
3462 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3463   tmp_addr = ADDSI (tmp_addr, 4);
3464 }
3465   {
3466     SI opval = tmp_addr;
3467     SET_H_GR (FLD (f_operand1), opval);
3468     written |= (1 << 8);
3469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3470   }
3471 }
3472 }
3473 ; tmp_tmp_mem; });
3474 }
3475  else if (EQSI (tmp_rno, 12)) {
3476   tmp_newval = ({   SI tmp_addr;
3477   SI tmp_tmp_mem;
3478   BI tmp_postinc;
3479   tmp_postinc = FLD (f_memmode);
3480 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3481 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3482 ; if (NEBI (tmp_postinc, 0)) {
3483 {
3484 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3485   tmp_addr = ADDSI (tmp_addr, 4);
3486 }
3487   {
3488     SI opval = tmp_addr;
3489     SET_H_GR (FLD (f_operand1), opval);
3490     written |= (1 << 8);
3491     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3492   }
3493 }
3494 }
3495 ; tmp_tmp_mem; });
3496 }
3497  else if (EQSI (tmp_rno, 13)) {
3498   tmp_newval = ({   SI tmp_addr;
3499   SI tmp_tmp_mem;
3500   BI tmp_postinc;
3501   tmp_postinc = FLD (f_memmode);
3502 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3503 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3504 ; if (NEBI (tmp_postinc, 0)) {
3505 {
3506 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3507   tmp_addr = ADDSI (tmp_addr, 4);
3508 }
3509   {
3510     SI opval = tmp_addr;
3511     SET_H_GR (FLD (f_operand1), opval);
3512     written |= (1 << 8);
3513     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3514   }
3515 }
3516 }
3517 ; tmp_tmp_mem; });
3518 }
3519  else if (EQSI (tmp_rno, 14)) {
3520   tmp_newval = ({   SI tmp_addr;
3521   SI tmp_tmp_mem;
3522   BI tmp_postinc;
3523   tmp_postinc = FLD (f_memmode);
3524 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3525 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3526 ; if (NEBI (tmp_postinc, 0)) {
3527 {
3528 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3529   tmp_addr = ADDSI (tmp_addr, 4);
3530 }
3531   {
3532     SI opval = tmp_addr;
3533     SET_H_GR (FLD (f_operand1), opval);
3534     written |= (1 << 8);
3535     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3536   }
3537 }
3538 }
3539 ; tmp_tmp_mem; });
3540 }
3541  else if (EQSI (tmp_rno, 15)) {
3542   tmp_newval = ({   SI tmp_addr;
3543   SI tmp_tmp_mem;
3544   BI tmp_postinc;
3545   tmp_postinc = FLD (f_memmode);
3546 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3547 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3548 ; if (NEBI (tmp_postinc, 0)) {
3549 {
3550 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3551   tmp_addr = ADDSI (tmp_addr, 4);
3552 }
3553   {
3554     SI opval = tmp_addr;
3555     SET_H_GR (FLD (f_operand1), opval);
3556     written |= (1 << 8);
3557     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3558   }
3559 }
3560 }
3561 ; tmp_tmp_mem; });
3562 }
3563  else {
3564 cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
3565 }
3566   {
3567     SI opval = tmp_newval;
3568     SET_H_SR (FLD (f_operand2), opval);
3569     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3570   }
3571 {
3572   {
3573     BI opval = 0;
3574     CPU (h_xbit) = opval;
3575     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3576   }
3577   {
3578     BI opval = 0;
3579     SET_H_INSN_PREFIXED_P (opval);
3580     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3581   }
3582 }
3583 }
3584
3585   abuf->written = written;
3586 #undef FLD
3587 }
3588   NEXT (vpc);
3589
3590   CASE (sem, INSN_MOVE_C_SPRV32_P2) : /* move ${const32},${Pd} */
3591 {
3592   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3593   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3594 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3595   int UNUSED written = 0;
3596   IADDR UNUSED pc = abuf->addr;
3597   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3598
3599 {
3600   {
3601     SI opval = FLD (f_indir_pc__dword);
3602     SET_H_SR (FLD (f_operand2), opval);
3603     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3604   }
3605 {
3606   {
3607     BI opval = 0;
3608     CPU (h_xbit) = opval;
3609     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3610   }
3611   {
3612     BI opval = 0;
3613     SET_H_INSN_PREFIXED_P (opval);
3614     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3615   }
3616 }
3617 }
3618
3619 #undef FLD
3620 }
3621   NEXT (vpc);
3622
3623   CASE (sem, INSN_MOVE_C_SPRV32_P3) : /* move ${const32},${Pd} */
3624 {
3625   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3626   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3627 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3628   int UNUSED written = 0;
3629   IADDR UNUSED pc = abuf->addr;
3630   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3631
3632 {
3633   {
3634     SI opval = FLD (f_indir_pc__dword);
3635     SET_H_SR (FLD (f_operand2), opval);
3636     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3637   }
3638 {
3639   {
3640     BI opval = 0;
3641     CPU (h_xbit) = opval;
3642     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3643   }
3644   {
3645     BI opval = 0;
3646     SET_H_INSN_PREFIXED_P (opval);
3647     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3648   }
3649 }
3650 }
3651
3652 #undef FLD
3653 }
3654   NEXT (vpc);
3655
3656   CASE (sem, INSN_MOVE_C_SPRV32_P5) : /* move ${const32},${Pd} */
3657 {
3658   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3659   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3660 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3661   int UNUSED written = 0;
3662   IADDR UNUSED pc = abuf->addr;
3663   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3664
3665 {
3666   {
3667     SI opval = FLD (f_indir_pc__dword);
3668     SET_H_SR (FLD (f_operand2), opval);
3669     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3670   }
3671 {
3672   {
3673     BI opval = 0;
3674     CPU (h_xbit) = opval;
3675     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3676   }
3677   {
3678     BI opval = 0;
3679     SET_H_INSN_PREFIXED_P (opval);
3680     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3681   }
3682 }
3683 }
3684
3685 #undef FLD
3686 }
3687   NEXT (vpc);
3688
3689   CASE (sem, INSN_MOVE_C_SPRV32_P6) : /* move ${const32},${Pd} */
3690 {
3691   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3692   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3693 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3694   int UNUSED written = 0;
3695   IADDR UNUSED pc = abuf->addr;
3696   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3697
3698 {
3699   {
3700     SI opval = FLD (f_indir_pc__dword);
3701     SET_H_SR (FLD (f_operand2), opval);
3702     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3703   }
3704 {
3705   {
3706     BI opval = 0;
3707     CPU (h_xbit) = opval;
3708     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3709   }
3710   {
3711     BI opval = 0;
3712     SET_H_INSN_PREFIXED_P (opval);
3713     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3714   }
3715 }
3716 }
3717
3718 #undef FLD
3719 }
3720   NEXT (vpc);
3721
3722   CASE (sem, INSN_MOVE_C_SPRV32_P7) : /* move ${const32},${Pd} */
3723 {
3724   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3725   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3726 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3727   int UNUSED written = 0;
3728   IADDR UNUSED pc = abuf->addr;
3729   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3730
3731 {
3732   {
3733     SI opval = FLD (f_indir_pc__dword);
3734     SET_H_SR (FLD (f_operand2), opval);
3735     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3736   }
3737 {
3738   {
3739     BI opval = 0;
3740     CPU (h_xbit) = opval;
3741     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3742   }
3743   {
3744     BI opval = 0;
3745     SET_H_INSN_PREFIXED_P (opval);
3746     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3747   }
3748 }
3749 }
3750
3751 #undef FLD
3752 }
3753   NEXT (vpc);
3754
3755   CASE (sem, INSN_MOVE_C_SPRV32_P9) : /* move ${const32},${Pd} */
3756 {
3757   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3758   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3759 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3760   int UNUSED written = 0;
3761   IADDR UNUSED pc = abuf->addr;
3762   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3763
3764 {
3765   {
3766     SI opval = FLD (f_indir_pc__dword);
3767     SET_H_SR (FLD (f_operand2), opval);
3768     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3769   }
3770 {
3771   {
3772     BI opval = 0;
3773     CPU (h_xbit) = opval;
3774     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3775   }
3776   {
3777     BI opval = 0;
3778     SET_H_INSN_PREFIXED_P (opval);
3779     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3780   }
3781 }
3782 }
3783
3784 #undef FLD
3785 }
3786   NEXT (vpc);
3787
3788   CASE (sem, INSN_MOVE_C_SPRV32_P10) : /* move ${const32},${Pd} */
3789 {
3790   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3791   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3792 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3793   int UNUSED written = 0;
3794   IADDR UNUSED pc = abuf->addr;
3795   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3796
3797 {
3798   {
3799     SI opval = FLD (f_indir_pc__dword);
3800     SET_H_SR (FLD (f_operand2), opval);
3801     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3802   }
3803 {
3804   {
3805     BI opval = 0;
3806     CPU (h_xbit) = opval;
3807     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3808   }
3809   {
3810     BI opval = 0;
3811     SET_H_INSN_PREFIXED_P (opval);
3812     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3813   }
3814 }
3815 }
3816
3817 #undef FLD
3818 }
3819   NEXT (vpc);
3820
3821   CASE (sem, INSN_MOVE_C_SPRV32_P11) : /* move ${const32},${Pd} */
3822 {
3823   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3824   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3825 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3826   int UNUSED written = 0;
3827   IADDR UNUSED pc = abuf->addr;
3828   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3829
3830 {
3831   {
3832     SI opval = FLD (f_indir_pc__dword);
3833     SET_H_SR (FLD (f_operand2), opval);
3834     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3835   }
3836 {
3837   {
3838     BI opval = 0;
3839     CPU (h_xbit) = opval;
3840     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3841   }
3842   {
3843     BI opval = 0;
3844     SET_H_INSN_PREFIXED_P (opval);
3845     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3846   }
3847 }
3848 }
3849
3850 #undef FLD
3851 }
3852   NEXT (vpc);
3853
3854   CASE (sem, INSN_MOVE_C_SPRV32_P12) : /* move ${const32},${Pd} */
3855 {
3856   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3857   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3858 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3859   int UNUSED written = 0;
3860   IADDR UNUSED pc = abuf->addr;
3861   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3862
3863 {
3864   {
3865     SI opval = FLD (f_indir_pc__dword);
3866     SET_H_SR (FLD (f_operand2), opval);
3867     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3868   }
3869 {
3870   {
3871     BI opval = 0;
3872     CPU (h_xbit) = opval;
3873     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3874   }
3875   {
3876     BI opval = 0;
3877     SET_H_INSN_PREFIXED_P (opval);
3878     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3879   }
3880 }
3881 }
3882
3883 #undef FLD
3884 }
3885   NEXT (vpc);
3886
3887   CASE (sem, INSN_MOVE_C_SPRV32_P13) : /* move ${const32},${Pd} */
3888 {
3889   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3890   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3891 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3892   int UNUSED written = 0;
3893   IADDR UNUSED pc = abuf->addr;
3894   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3895
3896 {
3897   {
3898     SI opval = FLD (f_indir_pc__dword);
3899     SET_H_SR (FLD (f_operand2), opval);
3900     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3901   }
3902 {
3903   {
3904     BI opval = 0;
3905     CPU (h_xbit) = opval;
3906     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3907   }
3908   {
3909     BI opval = 0;
3910     SET_H_INSN_PREFIXED_P (opval);
3911     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3912   }
3913 }
3914 }
3915
3916 #undef FLD
3917 }
3918   NEXT (vpc);
3919
3920   CASE (sem, INSN_MOVE_C_SPRV32_P14) : /* move ${const32},${Pd} */
3921 {
3922   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3923   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3924 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3925   int UNUSED written = 0;
3926   IADDR UNUSED pc = abuf->addr;
3927   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3928
3929 {
3930   {
3931     SI opval = FLD (f_indir_pc__dword);
3932     SET_H_SR (FLD (f_operand2), opval);
3933     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3934   }
3935 {
3936   {
3937     BI opval = 0;
3938     CPU (h_xbit) = opval;
3939     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3940   }
3941   {
3942     BI opval = 0;
3943     SET_H_INSN_PREFIXED_P (opval);
3944     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3945   }
3946 }
3947 }
3948
3949 #undef FLD
3950 }
3951   NEXT (vpc);
3952
3953   CASE (sem, INSN_MOVE_C_SPRV32_P15) : /* move ${const32},${Pd} */
3954 {
3955   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3956   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3957 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3958   int UNUSED written = 0;
3959   IADDR UNUSED pc = abuf->addr;
3960   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3961
3962 {
3963   {
3964     SI opval = FLD (f_indir_pc__dword);
3965     SET_H_SR (FLD (f_operand2), opval);
3966     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3967   }
3968 {
3969   {
3970     BI opval = 0;
3971     CPU (h_xbit) = opval;
3972     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3973   }
3974   {
3975     BI opval = 0;
3976     SET_H_INSN_PREFIXED_P (opval);
3977     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3978   }
3979 }
3980 }
3981
3982 #undef FLD
3983 }
3984   NEXT (vpc);
3985
3986   CASE (sem, INSN_MOVE_SPR_MV32) : /* move ${Ps},[${Rd-sfield}${inc}] */
3987 {
3988   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3989   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3990 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
3991   int UNUSED written = 0;
3992   IADDR UNUSED pc = abuf->addr;
3993   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3994
3995 {
3996   SI tmp_rno;
3997   tmp_rno = FLD (f_operand2);
3998 if (EQSI (tmp_rno, 2)) {
3999 {
4000   SI tmp_addr;
4001   BI tmp_postinc;
4002   tmp_postinc = FLD (f_memmode);
4003   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4004 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4005 if (EQBI (CPU (h_pbit), 0)) {
4006 {
4007   {
4008     SI opval = GET_H_SR (FLD (f_operand2));
4009     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4010     written |= (1 << 13);
4011     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4012   }
4013   {
4014     BI opval = CPU (h_pbit);
4015     CPU (h_cbit) = opval;
4016     written |= (1 << 10);
4017     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4018   }
4019 }
4020 } else {
4021   {
4022     BI opval = 1;
4023     CPU (h_cbit) = opval;
4024     written |= (1 << 10);
4025     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4026   }
4027 }
4028 } else {
4029   {
4030     SI opval = GET_H_SR (FLD (f_operand2));
4031     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4032     written |= (1 << 13);
4033     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4034   }
4035 }
4036 if (NEBI (tmp_postinc, 0)) {
4037 {
4038 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4039   tmp_addr = ADDSI (tmp_addr, 4);
4040 }
4041   {
4042     SI opval = tmp_addr;
4043     SET_H_GR (FLD (f_operand1), opval);
4044     written |= (1 << 9);
4045     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4046   }
4047 }
4048 }
4049 }
4050 }
4051  else if (EQSI (tmp_rno, 3)) {
4052 {
4053   SI tmp_addr;
4054   BI tmp_postinc;
4055   tmp_postinc = FLD (f_memmode);
4056   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4057 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4058 if (EQBI (CPU (h_pbit), 0)) {
4059 {
4060   {
4061     QI opval = GET_H_SR (FLD (f_operand2));
4062     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4063     written |= (1 << 12);
4064     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4065   }
4066   {
4067     BI opval = CPU (h_pbit);
4068     CPU (h_cbit) = opval;
4069     written |= (1 << 10);
4070     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4071   }
4072 }
4073 } else {
4074   {
4075     BI opval = 1;
4076     CPU (h_cbit) = opval;
4077     written |= (1 << 10);
4078     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4079   }
4080 }
4081 } else {
4082   {
4083     QI opval = GET_H_SR (FLD (f_operand2));
4084     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4085     written |= (1 << 12);
4086     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4087   }
4088 }
4089 if (NEBI (tmp_postinc, 0)) {
4090 {
4091 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4092   tmp_addr = ADDSI (tmp_addr, 1);
4093 }
4094   {
4095     SI opval = tmp_addr;
4096     SET_H_GR (FLD (f_operand1), opval);
4097     written |= (1 << 9);
4098     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4099   }
4100 }
4101 }
4102 }
4103 }
4104  else if (EQSI (tmp_rno, 5)) {
4105 {
4106   SI tmp_addr;
4107   BI tmp_postinc;
4108   tmp_postinc = FLD (f_memmode);
4109   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4110 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4111 if (EQBI (CPU (h_pbit), 0)) {
4112 {
4113   {
4114     SI opval = GET_H_SR (FLD (f_operand2));
4115     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4116     written |= (1 << 13);
4117     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4118   }
4119   {
4120     BI opval = CPU (h_pbit);
4121     CPU (h_cbit) = opval;
4122     written |= (1 << 10);
4123     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4124   }
4125 }
4126 } else {
4127   {
4128     BI opval = 1;
4129     CPU (h_cbit) = opval;
4130     written |= (1 << 10);
4131     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4132   }
4133 }
4134 } else {
4135   {
4136     SI opval = GET_H_SR (FLD (f_operand2));
4137     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4138     written |= (1 << 13);
4139     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4140   }
4141 }
4142 if (NEBI (tmp_postinc, 0)) {
4143 {
4144 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4145   tmp_addr = ADDSI (tmp_addr, 4);
4146 }
4147   {
4148     SI opval = tmp_addr;
4149     SET_H_GR (FLD (f_operand1), opval);
4150     written |= (1 << 9);
4151     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4152   }
4153 }
4154 }
4155 }
4156 }
4157  else if (EQSI (tmp_rno, 6)) {
4158 {
4159   SI tmp_addr;
4160   BI tmp_postinc;
4161   tmp_postinc = FLD (f_memmode);
4162   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4163 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4164 if (EQBI (CPU (h_pbit), 0)) {
4165 {
4166   {
4167     SI opval = GET_H_SR (FLD (f_operand2));
4168     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4169     written |= (1 << 13);
4170     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4171   }
4172   {
4173     BI opval = CPU (h_pbit);
4174     CPU (h_cbit) = opval;
4175     written |= (1 << 10);
4176     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4177   }
4178 }
4179 } else {
4180   {
4181     BI opval = 1;
4182     CPU (h_cbit) = opval;
4183     written |= (1 << 10);
4184     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4185   }
4186 }
4187 } else {
4188   {
4189     SI opval = GET_H_SR (FLD (f_operand2));
4190     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4191     written |= (1 << 13);
4192     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4193   }
4194 }
4195 if (NEBI (tmp_postinc, 0)) {
4196 {
4197 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4198   tmp_addr = ADDSI (tmp_addr, 4);
4199 }
4200   {
4201     SI opval = tmp_addr;
4202     SET_H_GR (FLD (f_operand1), opval);
4203     written |= (1 << 9);
4204     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4205   }
4206 }
4207 }
4208 }
4209 }
4210  else if (EQSI (tmp_rno, 7)) {
4211 {
4212   SI tmp_addr;
4213   BI tmp_postinc;
4214   tmp_postinc = FLD (f_memmode);
4215   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4216 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4217 if (EQBI (CPU (h_pbit), 0)) {
4218 {
4219   {
4220     SI opval = GET_H_SR (FLD (f_operand2));
4221     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4222     written |= (1 << 13);
4223     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4224   }
4225   {
4226     BI opval = CPU (h_pbit);
4227     CPU (h_cbit) = opval;
4228     written |= (1 << 10);
4229     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4230   }
4231 }
4232 } else {
4233   {
4234     BI opval = 1;
4235     CPU (h_cbit) = opval;
4236     written |= (1 << 10);
4237     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4238   }
4239 }
4240 } else {
4241   {
4242     SI opval = GET_H_SR (FLD (f_operand2));
4243     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4244     written |= (1 << 13);
4245     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4246   }
4247 }
4248 if (NEBI (tmp_postinc, 0)) {
4249 {
4250 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4251   tmp_addr = ADDSI (tmp_addr, 4);
4252 }
4253   {
4254     SI opval = tmp_addr;
4255     SET_H_GR (FLD (f_operand1), opval);
4256     written |= (1 << 9);
4257     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4258   }
4259 }
4260 }
4261 }
4262 }
4263  else if (EQSI (tmp_rno, 9)) {
4264 {
4265   SI tmp_addr;
4266   BI tmp_postinc;
4267   tmp_postinc = FLD (f_memmode);
4268   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4269 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4270 if (EQBI (CPU (h_pbit), 0)) {
4271 {
4272   {
4273     SI opval = GET_H_SR (FLD (f_operand2));
4274     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4275     written |= (1 << 13);
4276     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4277   }
4278   {
4279     BI opval = CPU (h_pbit);
4280     CPU (h_cbit) = opval;
4281     written |= (1 << 10);
4282     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4283   }
4284 }
4285 } else {
4286   {
4287     BI opval = 1;
4288     CPU (h_cbit) = opval;
4289     written |= (1 << 10);
4290     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4291   }
4292 }
4293 } else {
4294   {
4295     SI opval = GET_H_SR (FLD (f_operand2));
4296     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4297     written |= (1 << 13);
4298     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4299   }
4300 }
4301 if (NEBI (tmp_postinc, 0)) {
4302 {
4303 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4304   tmp_addr = ADDSI (tmp_addr, 4);
4305 }
4306   {
4307     SI opval = tmp_addr;
4308     SET_H_GR (FLD (f_operand1), opval);
4309     written |= (1 << 9);
4310     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4311   }
4312 }
4313 }
4314 }
4315 }
4316  else if (EQSI (tmp_rno, 10)) {
4317 {
4318   SI tmp_addr;
4319   BI tmp_postinc;
4320   tmp_postinc = FLD (f_memmode);
4321   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4322 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4323 if (EQBI (CPU (h_pbit), 0)) {
4324 {
4325   {
4326     SI opval = GET_H_SR (FLD (f_operand2));
4327     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4328     written |= (1 << 13);
4329     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4330   }
4331   {
4332     BI opval = CPU (h_pbit);
4333     CPU (h_cbit) = opval;
4334     written |= (1 << 10);
4335     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4336   }
4337 }
4338 } else {
4339   {
4340     BI opval = 1;
4341     CPU (h_cbit) = opval;
4342     written |= (1 << 10);
4343     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4344   }
4345 }
4346 } else {
4347   {
4348     SI opval = GET_H_SR (FLD (f_operand2));
4349     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4350     written |= (1 << 13);
4351     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4352   }
4353 }
4354 if (NEBI (tmp_postinc, 0)) {
4355 {
4356 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4357   tmp_addr = ADDSI (tmp_addr, 4);
4358 }
4359   {
4360     SI opval = tmp_addr;
4361     SET_H_GR (FLD (f_operand1), opval);
4362     written |= (1 << 9);
4363     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4364   }
4365 }
4366 }
4367 }
4368 }
4369  else if (EQSI (tmp_rno, 11)) {
4370 {
4371   SI tmp_addr;
4372   BI tmp_postinc;
4373   tmp_postinc = FLD (f_memmode);
4374   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4375 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4376 if (EQBI (CPU (h_pbit), 0)) {
4377 {
4378   {
4379     SI opval = GET_H_SR (FLD (f_operand2));
4380     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4381     written |= (1 << 13);
4382     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4383   }
4384   {
4385     BI opval = CPU (h_pbit);
4386     CPU (h_cbit) = opval;
4387     written |= (1 << 10);
4388     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4389   }
4390 }
4391 } else {
4392   {
4393     BI opval = 1;
4394     CPU (h_cbit) = opval;
4395     written |= (1 << 10);
4396     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4397   }
4398 }
4399 } else {
4400   {
4401     SI opval = GET_H_SR (FLD (f_operand2));
4402     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4403     written |= (1 << 13);
4404     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4405   }
4406 }
4407 if (NEBI (tmp_postinc, 0)) {
4408 {
4409 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4410   tmp_addr = ADDSI (tmp_addr, 4);
4411 }
4412   {
4413     SI opval = tmp_addr;
4414     SET_H_GR (FLD (f_operand1), opval);
4415     written |= (1 << 9);
4416     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4417   }
4418 }
4419 }
4420 }
4421 }
4422  else if (EQSI (tmp_rno, 12)) {
4423 {
4424   SI tmp_addr;
4425   BI tmp_postinc;
4426   tmp_postinc = FLD (f_memmode);
4427   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4428 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4429 if (EQBI (CPU (h_pbit), 0)) {
4430 {
4431   {
4432     SI opval = GET_H_SR (FLD (f_operand2));
4433     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4434     written |= (1 << 13);
4435     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4436   }
4437   {
4438     BI opval = CPU (h_pbit);
4439     CPU (h_cbit) = opval;
4440     written |= (1 << 10);
4441     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4442   }
4443 }
4444 } else {
4445   {
4446     BI opval = 1;
4447     CPU (h_cbit) = opval;
4448     written |= (1 << 10);
4449     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4450   }
4451 }
4452 } else {
4453   {
4454     SI opval = GET_H_SR (FLD (f_operand2));
4455     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4456     written |= (1 << 13);
4457     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4458   }
4459 }
4460 if (NEBI (tmp_postinc, 0)) {
4461 {
4462 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4463   tmp_addr = ADDSI (tmp_addr, 4);
4464 }
4465   {
4466     SI opval = tmp_addr;
4467     SET_H_GR (FLD (f_operand1), opval);
4468     written |= (1 << 9);
4469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4470   }
4471 }
4472 }
4473 }
4474 }
4475  else if (EQSI (tmp_rno, 13)) {
4476 {
4477   SI tmp_addr;
4478   BI tmp_postinc;
4479   tmp_postinc = FLD (f_memmode);
4480   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4481 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4482 if (EQBI (CPU (h_pbit), 0)) {
4483 {
4484   {
4485     SI opval = GET_H_SR (FLD (f_operand2));
4486     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4487     written |= (1 << 13);
4488     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4489   }
4490   {
4491     BI opval = CPU (h_pbit);
4492     CPU (h_cbit) = opval;
4493     written |= (1 << 10);
4494     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4495   }
4496 }
4497 } else {
4498   {
4499     BI opval = 1;
4500     CPU (h_cbit) = opval;
4501     written |= (1 << 10);
4502     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4503   }
4504 }
4505 } else {
4506   {
4507     SI opval = GET_H_SR (FLD (f_operand2));
4508     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4509     written |= (1 << 13);
4510     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4511   }
4512 }
4513 if (NEBI (tmp_postinc, 0)) {
4514 {
4515 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4516   tmp_addr = ADDSI (tmp_addr, 4);
4517 }
4518   {
4519     SI opval = tmp_addr;
4520     SET_H_GR (FLD (f_operand1), opval);
4521     written |= (1 << 9);
4522     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4523   }
4524 }
4525 }
4526 }
4527 }
4528  else if (EQSI (tmp_rno, 14)) {
4529 {
4530   SI tmp_addr;
4531   BI tmp_postinc;
4532   tmp_postinc = FLD (f_memmode);
4533   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4534 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4535 if (EQBI (CPU (h_pbit), 0)) {
4536 {
4537   {
4538     SI opval = GET_H_SR (FLD (f_operand2));
4539     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4540     written |= (1 << 13);
4541     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4542   }
4543   {
4544     BI opval = CPU (h_pbit);
4545     CPU (h_cbit) = opval;
4546     written |= (1 << 10);
4547     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4548   }
4549 }
4550 } else {
4551   {
4552     BI opval = 1;
4553     CPU (h_cbit) = opval;
4554     written |= (1 << 10);
4555     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4556   }
4557 }
4558 } else {
4559   {
4560     SI opval = GET_H_SR (FLD (f_operand2));
4561     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4562     written |= (1 << 13);
4563     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4564   }
4565 }
4566 if (NEBI (tmp_postinc, 0)) {
4567 {
4568 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4569   tmp_addr = ADDSI (tmp_addr, 4);
4570 }
4571   {
4572     SI opval = tmp_addr;
4573     SET_H_GR (FLD (f_operand1), opval);
4574     written |= (1 << 9);
4575     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4576   }
4577 }
4578 }
4579 }
4580 }
4581  else if (EQSI (tmp_rno, 15)) {
4582 {
4583   SI tmp_addr;
4584   BI tmp_postinc;
4585   tmp_postinc = FLD (f_memmode);
4586   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4587 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4588 if (EQBI (CPU (h_pbit), 0)) {
4589 {
4590   {
4591     SI opval = GET_H_SR (FLD (f_operand2));
4592     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4593     written |= (1 << 13);
4594     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4595   }
4596   {
4597     BI opval = CPU (h_pbit);
4598     CPU (h_cbit) = opval;
4599     written |= (1 << 10);
4600     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4601   }
4602 }
4603 } else {
4604   {
4605     BI opval = 1;
4606     CPU (h_cbit) = opval;
4607     written |= (1 << 10);
4608     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4609   }
4610 }
4611 } else {
4612   {
4613     SI opval = GET_H_SR (FLD (f_operand2));
4614     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4615     written |= (1 << 13);
4616     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4617   }
4618 }
4619 if (NEBI (tmp_postinc, 0)) {
4620 {
4621 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4622   tmp_addr = ADDSI (tmp_addr, 4);
4623 }
4624   {
4625     SI opval = tmp_addr;
4626     SET_H_GR (FLD (f_operand1), opval);
4627     written |= (1 << 9);
4628     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4629   }
4630 }
4631 }
4632 }
4633 }
4634  else if (EQSI (tmp_rno, 0)) {
4635 {
4636   SI tmp_addr;
4637   BI tmp_postinc;
4638   tmp_postinc = FLD (f_memmode);
4639   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4640 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4641 if (EQBI (CPU (h_pbit), 0)) {
4642 {
4643   {
4644     QI opval = GET_H_SR (FLD (f_operand2));
4645     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4646     written |= (1 << 12);
4647     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4648   }
4649   {
4650     BI opval = CPU (h_pbit);
4651     CPU (h_cbit) = opval;
4652     written |= (1 << 10);
4653     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4654   }
4655 }
4656 } else {
4657   {
4658     BI opval = 1;
4659     CPU (h_cbit) = opval;
4660     written |= (1 << 10);
4661     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4662   }
4663 }
4664 } else {
4665   {
4666     QI opval = GET_H_SR (FLD (f_operand2));
4667     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4668     written |= (1 << 12);
4669     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4670   }
4671 }
4672 if (NEBI (tmp_postinc, 0)) {
4673 {
4674 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4675   tmp_addr = ADDSI (tmp_addr, 1);
4676 }
4677   {
4678     SI opval = tmp_addr;
4679     SET_H_GR (FLD (f_operand1), opval);
4680     written |= (1 << 9);
4681     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4682   }
4683 }
4684 }
4685 }
4686 }
4687  else if (EQSI (tmp_rno, 1)) {
4688 {
4689   SI tmp_addr;
4690   BI tmp_postinc;
4691   tmp_postinc = FLD (f_memmode);
4692   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4693 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4694 if (EQBI (CPU (h_pbit), 0)) {
4695 {
4696   {
4697     QI opval = GET_H_SR (FLD (f_operand2));
4698     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4699     written |= (1 << 12);
4700     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4701   }
4702   {
4703     BI opval = CPU (h_pbit);
4704     CPU (h_cbit) = opval;
4705     written |= (1 << 10);
4706     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4707   }
4708 }
4709 } else {
4710   {
4711     BI opval = 1;
4712     CPU (h_cbit) = opval;
4713     written |= (1 << 10);
4714     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4715   }
4716 }
4717 } else {
4718   {
4719     QI opval = GET_H_SR (FLD (f_operand2));
4720     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4721     written |= (1 << 12);
4722     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4723   }
4724 }
4725 if (NEBI (tmp_postinc, 0)) {
4726 {
4727 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4728   tmp_addr = ADDSI (tmp_addr, 1);
4729 }
4730   {
4731     SI opval = tmp_addr;
4732     SET_H_GR (FLD (f_operand1), opval);
4733     written |= (1 << 9);
4734     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4735   }
4736 }
4737 }
4738 }
4739 }
4740  else if (EQSI (tmp_rno, 4)) {
4741 {
4742   SI tmp_addr;
4743   BI tmp_postinc;
4744   tmp_postinc = FLD (f_memmode);
4745   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4746 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4747 if (EQBI (CPU (h_pbit), 0)) {
4748 {
4749   {
4750     HI opval = GET_H_SR (FLD (f_operand2));
4751     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4752     written |= (1 << 11);
4753     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4754   }
4755   {
4756     BI opval = CPU (h_pbit);
4757     CPU (h_cbit) = opval;
4758     written |= (1 << 10);
4759     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4760   }
4761 }
4762 } else {
4763   {
4764     BI opval = 1;
4765     CPU (h_cbit) = opval;
4766     written |= (1 << 10);
4767     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4768   }
4769 }
4770 } else {
4771   {
4772     HI opval = GET_H_SR (FLD (f_operand2));
4773     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4774     written |= (1 << 11);
4775     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4776   }
4777 }
4778 if (NEBI (tmp_postinc, 0)) {
4779 {
4780 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4781   tmp_addr = ADDSI (tmp_addr, 2);
4782 }
4783   {
4784     SI opval = tmp_addr;
4785     SET_H_GR (FLD (f_operand1), opval);
4786     written |= (1 << 9);
4787     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4788   }
4789 }
4790 }
4791 }
4792 }
4793  else if (EQSI (tmp_rno, 8)) {
4794 {
4795   SI tmp_addr;
4796   BI tmp_postinc;
4797   tmp_postinc = FLD (f_memmode);
4798   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4799 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4800 if (EQBI (CPU (h_pbit), 0)) {
4801 {
4802   {
4803     SI opval = GET_H_SR (FLD (f_operand2));
4804     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4805     written |= (1 << 13);
4806     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4807   }
4808   {
4809     BI opval = CPU (h_pbit);
4810     CPU (h_cbit) = opval;
4811     written |= (1 << 10);
4812     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4813   }
4814 }
4815 } else {
4816   {
4817     BI opval = 1;
4818     CPU (h_cbit) = opval;
4819     written |= (1 << 10);
4820     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4821   }
4822 }
4823 } else {
4824   {
4825     SI opval = GET_H_SR (FLD (f_operand2));
4826     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4827     written |= (1 << 13);
4828     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4829   }
4830 }
4831 if (NEBI (tmp_postinc, 0)) {
4832 {
4833 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4834   tmp_addr = ADDSI (tmp_addr, 4);
4835 }
4836   {
4837     SI opval = tmp_addr;
4838     SET_H_GR (FLD (f_operand1), opval);
4839     written |= (1 << 9);
4840     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4841   }
4842 }
4843 }
4844 }
4845 }
4846  else {
4847 cgen_rtx_error (current_cpu, "write from unimplemented special register");
4848 }
4849 {
4850   {
4851     BI opval = 0;
4852     CPU (h_xbit) = opval;
4853     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4854   }
4855   {
4856     BI opval = 0;
4857     SET_H_INSN_PREFIXED_P (opval);
4858     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4859   }
4860 }
4861 }
4862
4863   abuf->written = written;
4864 #undef FLD
4865 }
4866   NEXT (vpc);
4867
4868   CASE (sem, INSN_MOVE_SS_R) : /* move ${Ss},${Rd-sfield} */
4869 {
4870   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4871   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4872 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
4873   int UNUSED written = 0;
4874   IADDR UNUSED pc = abuf->addr;
4875   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4876
4877 {
4878   {
4879     SI opval = GET_H_SUPR (FLD (f_operand2));
4880     SET_H_GR (FLD (f_operand1), opval);
4881     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4882   }
4883 {
4884   {
4885     BI opval = 0;
4886     CPU (h_xbit) = opval;
4887     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4888   }
4889   {
4890     BI opval = 0;
4891     SET_H_INSN_PREFIXED_P (opval);
4892     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4893   }
4894 }
4895 }
4896
4897 #undef FLD
4898 }
4899   NEXT (vpc);
4900
4901   CASE (sem, INSN_MOVE_R_SS) : /* move ${Rs},${Sd} */
4902 {
4903   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4904   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4905 #define FLD(f) abuf->fields.sfmt_mcp.f
4906   int UNUSED written = 0;
4907   IADDR UNUSED pc = abuf->addr;
4908   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4909
4910 {
4911   {
4912     SI opval = GET_H_GR (FLD (f_operand1));
4913     SET_H_SUPR (FLD (f_operand2), opval);
4914     TRACE_RESULT (current_cpu, abuf, "supr", 'x', opval);
4915   }
4916 {
4917   {
4918     BI opval = 0;
4919     CPU (h_xbit) = opval;
4920     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4921   }
4922   {
4923     BI opval = 0;
4924     SET_H_INSN_PREFIXED_P (opval);
4925     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4926   }
4927 }
4928 }
4929
4930 #undef FLD
4931 }
4932   NEXT (vpc);
4933
4934   CASE (sem, INSN_MOVEM_R_M_V32) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
4935 {
4936   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4937   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4938 #define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
4939   int UNUSED written = 0;
4940   IADDR UNUSED pc = abuf->addr;
4941   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4942
4943 {
4944   SI tmp_addr;
4945   BI tmp_postinc;
4946   tmp_postinc = FLD (f_memmode);
4947 {
4948   SI tmp_dummy;
4949   tmp_dummy = GET_H_GR (FLD (f_operand2));
4950 }
4951   tmp_addr = GET_H_GR (FLD (f_operand1));
4952 {
4953 if (GESI (FLD (f_operand2), 0)) {
4954 {
4955   SI tmp_tmp;
4956   tmp_tmp = GET_H_GR (((UINT) 0));
4957   {
4958     SI opval = tmp_tmp;
4959     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4960     written |= (1 << 21);
4961     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4962   }
4963   tmp_addr = ADDSI (tmp_addr, 4);
4964 }
4965 }
4966 if (GESI (FLD (f_operand2), 1)) {
4967 {
4968   SI tmp_tmp;
4969   tmp_tmp = GET_H_GR (((UINT) 1));
4970   {
4971     SI opval = tmp_tmp;
4972     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4973     written |= (1 << 21);
4974     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4975   }
4976   tmp_addr = ADDSI (tmp_addr, 4);
4977 }
4978 }
4979 if (GESI (FLD (f_operand2), 2)) {
4980 {
4981   SI tmp_tmp;
4982   tmp_tmp = GET_H_GR (((UINT) 2));
4983   {
4984     SI opval = tmp_tmp;
4985     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4986     written |= (1 << 21);
4987     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4988   }
4989   tmp_addr = ADDSI (tmp_addr, 4);
4990 }
4991 }
4992 if (GESI (FLD (f_operand2), 3)) {
4993 {
4994   SI tmp_tmp;
4995   tmp_tmp = GET_H_GR (((UINT) 3));
4996   {
4997     SI opval = tmp_tmp;
4998     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4999     written |= (1 << 21);
5000     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5001   }
5002   tmp_addr = ADDSI (tmp_addr, 4);
5003 }
5004 }
5005 if (GESI (FLD (f_operand2), 4)) {
5006 {
5007   SI tmp_tmp;
5008   tmp_tmp = GET_H_GR (((UINT) 4));
5009   {
5010     SI opval = tmp_tmp;
5011     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5012     written |= (1 << 21);
5013     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5014   }
5015   tmp_addr = ADDSI (tmp_addr, 4);
5016 }
5017 }
5018 if (GESI (FLD (f_operand2), 5)) {
5019 {
5020   SI tmp_tmp;
5021   tmp_tmp = GET_H_GR (((UINT) 5));
5022   {
5023     SI opval = tmp_tmp;
5024     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5025     written |= (1 << 21);
5026     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5027   }
5028   tmp_addr = ADDSI (tmp_addr, 4);
5029 }
5030 }
5031 if (GESI (FLD (f_operand2), 6)) {
5032 {
5033   SI tmp_tmp;
5034   tmp_tmp = GET_H_GR (((UINT) 6));
5035   {
5036     SI opval = tmp_tmp;
5037     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5038     written |= (1 << 21);
5039     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5040   }
5041   tmp_addr = ADDSI (tmp_addr, 4);
5042 }
5043 }
5044 if (GESI (FLD (f_operand2), 7)) {
5045 {
5046   SI tmp_tmp;
5047   tmp_tmp = GET_H_GR (((UINT) 7));
5048   {
5049     SI opval = tmp_tmp;
5050     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5051     written |= (1 << 21);
5052     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5053   }
5054   tmp_addr = ADDSI (tmp_addr, 4);
5055 }
5056 }
5057 if (GESI (FLD (f_operand2), 8)) {
5058 {
5059   SI tmp_tmp;
5060   tmp_tmp = GET_H_GR (((UINT) 8));
5061   {
5062     SI opval = tmp_tmp;
5063     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5064     written |= (1 << 21);
5065     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5066   }
5067   tmp_addr = ADDSI (tmp_addr, 4);
5068 }
5069 }
5070 if (GESI (FLD (f_operand2), 9)) {
5071 {
5072   SI tmp_tmp;
5073   tmp_tmp = GET_H_GR (((UINT) 9));
5074   {
5075     SI opval = tmp_tmp;
5076     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5077     written |= (1 << 21);
5078     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5079   }
5080   tmp_addr = ADDSI (tmp_addr, 4);
5081 }
5082 }
5083 if (GESI (FLD (f_operand2), 10)) {
5084 {
5085   SI tmp_tmp;
5086   tmp_tmp = GET_H_GR (((UINT) 10));
5087   {
5088     SI opval = tmp_tmp;
5089     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5090     written |= (1 << 21);
5091     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5092   }
5093   tmp_addr = ADDSI (tmp_addr, 4);
5094 }
5095 }
5096 if (GESI (FLD (f_operand2), 11)) {
5097 {
5098   SI tmp_tmp;
5099   tmp_tmp = GET_H_GR (((UINT) 11));
5100   {
5101     SI opval = tmp_tmp;
5102     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5103     written |= (1 << 21);
5104     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5105   }
5106   tmp_addr = ADDSI (tmp_addr, 4);
5107 }
5108 }
5109 if (GESI (FLD (f_operand2), 12)) {
5110 {
5111   SI tmp_tmp;
5112   tmp_tmp = GET_H_GR (((UINT) 12));
5113   {
5114     SI opval = tmp_tmp;
5115     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5116     written |= (1 << 21);
5117     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5118   }
5119   tmp_addr = ADDSI (tmp_addr, 4);
5120 }
5121 }
5122 if (GESI (FLD (f_operand2), 13)) {
5123 {
5124   SI tmp_tmp;
5125   tmp_tmp = GET_H_GR (((UINT) 13));
5126   {
5127     SI opval = tmp_tmp;
5128     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5129     written |= (1 << 21);
5130     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5131   }
5132   tmp_addr = ADDSI (tmp_addr, 4);
5133 }
5134 }
5135 if (GESI (FLD (f_operand2), 14)) {
5136 {
5137   SI tmp_tmp;
5138   tmp_tmp = GET_H_GR (((UINT) 14));
5139   {
5140     SI opval = tmp_tmp;
5141     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5142     written |= (1 << 21);
5143     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5144   }
5145   tmp_addr = ADDSI (tmp_addr, 4);
5146 }
5147 }
5148 if (GESI (FLD (f_operand2), 15)) {
5149 {
5150   SI tmp_tmp;
5151   tmp_tmp = GET_H_GR (((UINT) 15));
5152   {
5153     SI opval = tmp_tmp;
5154     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5155     written |= (1 << 21);
5156     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5157   }
5158   tmp_addr = ADDSI (tmp_addr, 4);
5159 }
5160 }
5161 }
5162 if (NEBI (tmp_postinc, 0)) {
5163   {
5164     SI opval = tmp_addr;
5165     SET_H_GR (FLD (f_operand1), opval);
5166     written |= (1 << 20);
5167     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5168   }
5169 }
5170 {
5171   {
5172     BI opval = 0;
5173     CPU (h_xbit) = opval;
5174     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5175   }
5176   {
5177     BI opval = 0;
5178     SET_H_INSN_PREFIXED_P (opval);
5179     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5180   }
5181 }
5182 }
5183
5184   abuf->written = written;
5185 #undef FLD
5186 }
5187   NEXT (vpc);
5188
5189   CASE (sem, INSN_MOVEM_M_R_V32) : /* movem [${Rs}${inc}],${Rd} */
5190 {
5191   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5192   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5193 #define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
5194   int UNUSED written = 0;
5195   IADDR UNUSED pc = abuf->addr;
5196   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5197
5198 {
5199   SI tmp_addr;
5200   BI tmp_postinc;
5201   tmp_postinc = FLD (f_memmode);
5202   tmp_addr = GET_H_GR (FLD (f_operand1));
5203 {
5204   SI tmp_dummy;
5205   tmp_dummy = GET_H_GR (FLD (f_operand2));
5206 }
5207 {
5208 if (GESI (FLD (f_operand2), 0)) {
5209 {
5210   SI tmp_tmp;
5211   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5212   {
5213     SI opval = tmp_tmp;
5214     SET_H_GR (((UINT) 0), opval);
5215     written |= (1 << 6);
5216     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5217   }
5218   tmp_addr = ADDSI (tmp_addr, 4);
5219 }
5220 }
5221 if (GESI (FLD (f_operand2), 1)) {
5222 {
5223   SI tmp_tmp;
5224   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5225   {
5226     SI opval = tmp_tmp;
5227     SET_H_GR (((UINT) 1), opval);
5228     written |= (1 << 7);
5229     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5230   }
5231   tmp_addr = ADDSI (tmp_addr, 4);
5232 }
5233 }
5234 if (GESI (FLD (f_operand2), 2)) {
5235 {
5236   SI tmp_tmp;
5237   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5238   {
5239     SI opval = tmp_tmp;
5240     SET_H_GR (((UINT) 2), opval);
5241     written |= (1 << 14);
5242     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5243   }
5244   tmp_addr = ADDSI (tmp_addr, 4);
5245 }
5246 }
5247 if (GESI (FLD (f_operand2), 3)) {
5248 {
5249   SI tmp_tmp;
5250   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5251   {
5252     SI opval = tmp_tmp;
5253     SET_H_GR (((UINT) 3), opval);
5254     written |= (1 << 15);
5255     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5256   }
5257   tmp_addr = ADDSI (tmp_addr, 4);
5258 }
5259 }
5260 if (GESI (FLD (f_operand2), 4)) {
5261 {
5262   SI tmp_tmp;
5263   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5264   {
5265     SI opval = tmp_tmp;
5266     SET_H_GR (((UINT) 4), opval);
5267     written |= (1 << 16);
5268     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5269   }
5270   tmp_addr = ADDSI (tmp_addr, 4);
5271 }
5272 }
5273 if (GESI (FLD (f_operand2), 5)) {
5274 {
5275   SI tmp_tmp;
5276   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5277   {
5278     SI opval = tmp_tmp;
5279     SET_H_GR (((UINT) 5), opval);
5280     written |= (1 << 17);
5281     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5282   }
5283   tmp_addr = ADDSI (tmp_addr, 4);
5284 }
5285 }
5286 if (GESI (FLD (f_operand2), 6)) {
5287 {
5288   SI tmp_tmp;
5289   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5290   {
5291     SI opval = tmp_tmp;
5292     SET_H_GR (((UINT) 6), opval);
5293     written |= (1 << 18);
5294     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5295   }
5296   tmp_addr = ADDSI (tmp_addr, 4);
5297 }
5298 }
5299 if (GESI (FLD (f_operand2), 7)) {
5300 {
5301   SI tmp_tmp;
5302   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5303   {
5304     SI opval = tmp_tmp;
5305     SET_H_GR (((UINT) 7), opval);
5306     written |= (1 << 19);
5307     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5308   }
5309   tmp_addr = ADDSI (tmp_addr, 4);
5310 }
5311 }
5312 if (GESI (FLD (f_operand2), 8)) {
5313 {
5314   SI tmp_tmp;
5315   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5316   {
5317     SI opval = tmp_tmp;
5318     SET_H_GR (((UINT) 8), opval);
5319     written |= (1 << 20);
5320     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5321   }
5322   tmp_addr = ADDSI (tmp_addr, 4);
5323 }
5324 }
5325 if (GESI (FLD (f_operand2), 9)) {
5326 {
5327   SI tmp_tmp;
5328   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5329   {
5330     SI opval = tmp_tmp;
5331     SET_H_GR (((UINT) 9), opval);
5332     written |= (1 << 21);
5333     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5334   }
5335   tmp_addr = ADDSI (tmp_addr, 4);
5336 }
5337 }
5338 if (GESI (FLD (f_operand2), 10)) {
5339 {
5340   SI tmp_tmp;
5341   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5342   {
5343     SI opval = tmp_tmp;
5344     SET_H_GR (((UINT) 10), opval);
5345     written |= (1 << 8);
5346     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5347   }
5348   tmp_addr = ADDSI (tmp_addr, 4);
5349 }
5350 }
5351 if (GESI (FLD (f_operand2), 11)) {
5352 {
5353   SI tmp_tmp;
5354   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5355   {
5356     SI opval = tmp_tmp;
5357     SET_H_GR (((UINT) 11), opval);
5358     written |= (1 << 9);
5359     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5360   }
5361   tmp_addr = ADDSI (tmp_addr, 4);
5362 }
5363 }
5364 if (GESI (FLD (f_operand2), 12)) {
5365 {
5366   SI tmp_tmp;
5367   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5368   {
5369     SI opval = tmp_tmp;
5370     SET_H_GR (((UINT) 12), opval);
5371     written |= (1 << 10);
5372     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5373   }
5374   tmp_addr = ADDSI (tmp_addr, 4);
5375 }
5376 }
5377 if (GESI (FLD (f_operand2), 13)) {
5378 {
5379   SI tmp_tmp;
5380   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5381   {
5382     SI opval = tmp_tmp;
5383     SET_H_GR (((UINT) 13), opval);
5384     written |= (1 << 11);
5385     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5386   }
5387   tmp_addr = ADDSI (tmp_addr, 4);
5388 }
5389 }
5390 if (GESI (FLD (f_operand2), 14)) {
5391 {
5392   SI tmp_tmp;
5393   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5394   {
5395     SI opval = tmp_tmp;
5396     SET_H_GR (((UINT) 14), opval);
5397     written |= (1 << 12);
5398     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5399   }
5400   tmp_addr = ADDSI (tmp_addr, 4);
5401 }
5402 }
5403 if (GESI (FLD (f_operand2), 15)) {
5404 {
5405   SI tmp_tmp;
5406   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5407   {
5408     SI opval = tmp_tmp;
5409     SET_H_GR (((UINT) 15), opval);
5410     written |= (1 << 13);
5411     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5412   }
5413   tmp_addr = ADDSI (tmp_addr, 4);
5414 }
5415 }
5416 }
5417 if (NEBI (tmp_postinc, 0)) {
5418   {
5419     SI opval = tmp_addr;
5420     SET_H_GR (FLD (f_operand1), opval);
5421     written |= (1 << 5);
5422     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5423   }
5424 }
5425 {
5426   {
5427     BI opval = 0;
5428     CPU (h_xbit) = opval;
5429     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5430   }
5431   {
5432     BI opval = 0;
5433     SET_H_INSN_PREFIXED_P (opval);
5434     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5435   }
5436 }
5437 }
5438
5439   abuf->written = written;
5440 #undef FLD
5441 }
5442   NEXT (vpc);
5443
5444   CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
5445 {
5446   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5447   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5448 #define FLD(f) abuf->fields.sfmt_addc_m.f
5449   int UNUSED written = 0;
5450   IADDR UNUSED pc = abuf->addr;
5451   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5452
5453 {
5454   QI tmp_tmpopd;
5455   QI tmp_tmpops;
5456   BI tmp_carry;
5457   QI tmp_newval;
5458   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5459   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5460   tmp_carry = CPU (h_cbit);
5461   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5462 {
5463   SI tmp_oldregval;
5464   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5465   {
5466     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5467     SET_H_GR (FLD (f_operand2), opval);
5468     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5469   }
5470 }
5471 {
5472   {
5473     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5474     CPU (h_cbit) = opval;
5475     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5476   }
5477   {
5478     BI opval = LTQI (tmp_newval, 0);
5479     CPU (h_nbit) = opval;
5480     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5481   }
5482   {
5483     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5484     CPU (h_zbit) = opval;
5485     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5486   }
5487   {
5488     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5489     CPU (h_vbit) = opval;
5490     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5491   }
5492 {
5493   {
5494     BI opval = 0;
5495     CPU (h_xbit) = opval;
5496     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5497   }
5498   {
5499     BI opval = 0;
5500     SET_H_INSN_PREFIXED_P (opval);
5501     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5502   }
5503 }
5504 }
5505 }
5506
5507 #undef FLD
5508 }
5509   NEXT (vpc);
5510
5511   CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
5512 {
5513   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5514   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5515 #define FLD(f) abuf->fields.sfmt_addc_m.f
5516   int UNUSED written = 0;
5517   IADDR UNUSED pc = abuf->addr;
5518   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5519
5520 {
5521   HI tmp_tmpopd;
5522   HI tmp_tmpops;
5523   BI tmp_carry;
5524   HI tmp_newval;
5525   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5526   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5527   tmp_carry = CPU (h_cbit);
5528   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5529 {
5530   SI tmp_oldregval;
5531   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5532   {
5533     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5534     SET_H_GR (FLD (f_operand2), opval);
5535     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5536   }
5537 }
5538 {
5539   {
5540     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5541     CPU (h_cbit) = opval;
5542     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5543   }
5544   {
5545     BI opval = LTHI (tmp_newval, 0);
5546     CPU (h_nbit) = opval;
5547     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5548   }
5549   {
5550     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5551     CPU (h_zbit) = opval;
5552     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5553   }
5554   {
5555     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5556     CPU (h_vbit) = opval;
5557     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5558   }
5559 {
5560   {
5561     BI opval = 0;
5562     CPU (h_xbit) = opval;
5563     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5564   }
5565   {
5566     BI opval = 0;
5567     SET_H_INSN_PREFIXED_P (opval);
5568     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5569   }
5570 }
5571 }
5572 }
5573
5574 #undef FLD
5575 }
5576   NEXT (vpc);
5577
5578   CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
5579 {
5580   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5581   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5582 #define FLD(f) abuf->fields.sfmt_addc_m.f
5583   int UNUSED written = 0;
5584   IADDR UNUSED pc = abuf->addr;
5585   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5586
5587 {
5588   SI tmp_tmpopd;
5589   SI tmp_tmpops;
5590   BI tmp_carry;
5591   SI tmp_newval;
5592   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5593   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5594   tmp_carry = CPU (h_cbit);
5595   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5596   {
5597     SI opval = tmp_newval;
5598     SET_H_GR (FLD (f_operand2), opval);
5599     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5600   }
5601 {
5602   {
5603     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5604     CPU (h_cbit) = opval;
5605     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5606   }
5607   {
5608     BI opval = LTSI (tmp_newval, 0);
5609     CPU (h_nbit) = opval;
5610     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5611   }
5612   {
5613     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5614     CPU (h_zbit) = opval;
5615     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5616   }
5617   {
5618     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5619     CPU (h_vbit) = opval;
5620     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5621   }
5622 {
5623   {
5624     BI opval = 0;
5625     CPU (h_xbit) = opval;
5626     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5627   }
5628   {
5629     BI opval = 0;
5630     SET_H_INSN_PREFIXED_P (opval);
5631     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5632   }
5633 }
5634 }
5635 }
5636
5637 #undef FLD
5638 }
5639   NEXT (vpc);
5640
5641   CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
5642 {
5643   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5644   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5645 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5646   int UNUSED written = 0;
5647   IADDR UNUSED pc = abuf->addr;
5648   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5649
5650 {
5651   QI tmp_tmpopd;
5652   QI tmp_tmpops;
5653   BI tmp_carry;
5654   QI tmp_newval;
5655   tmp_tmpops = ({   SI tmp_addr;
5656   QI tmp_tmp_mem;
5657   BI tmp_postinc;
5658   tmp_postinc = FLD (f_memmode);
5659 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5660 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
5661 ; if (NEBI (tmp_postinc, 0)) {
5662 {
5663 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5664   tmp_addr = ADDSI (tmp_addr, 1);
5665 }
5666   {
5667     SI opval = tmp_addr;
5668     SET_H_GR (FLD (f_operand1), opval);
5669     written |= (1 << 12);
5670     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5671   }
5672 }
5673 }
5674 ; tmp_tmp_mem; });
5675   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5676   tmp_carry = CPU (h_cbit);
5677   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5678 {
5679   SI tmp_oldregval;
5680   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5681   {
5682     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5683     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5684     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5685   }
5686 }
5687 {
5688   {
5689     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5690     CPU (h_cbit) = opval;
5691     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5692   }
5693   {
5694     BI opval = LTQI (tmp_newval, 0);
5695     CPU (h_nbit) = opval;
5696     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5697   }
5698   {
5699     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5700     CPU (h_zbit) = opval;
5701     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5702   }
5703   {
5704     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5705     CPU (h_vbit) = opval;
5706     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5707   }
5708 {
5709   {
5710     BI opval = 0;
5711     CPU (h_xbit) = opval;
5712     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5713   }
5714   {
5715     BI opval = 0;
5716     SET_H_INSN_PREFIXED_P (opval);
5717     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5718   }
5719 }
5720 }
5721 }
5722
5723   abuf->written = written;
5724 #undef FLD
5725 }
5726   NEXT (vpc);
5727
5728   CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
5729 {
5730   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5731   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5732 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5733   int UNUSED written = 0;
5734   IADDR UNUSED pc = abuf->addr;
5735   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5736
5737 {
5738   HI tmp_tmpopd;
5739   HI tmp_tmpops;
5740   BI tmp_carry;
5741   HI tmp_newval;
5742   tmp_tmpops = ({   SI tmp_addr;
5743   HI tmp_tmp_mem;
5744   BI tmp_postinc;
5745   tmp_postinc = FLD (f_memmode);
5746 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5747 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
5748 ; if (NEBI (tmp_postinc, 0)) {
5749 {
5750 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5751   tmp_addr = ADDSI (tmp_addr, 2);
5752 }
5753   {
5754     SI opval = tmp_addr;
5755     SET_H_GR (FLD (f_operand1), opval);
5756     written |= (1 << 12);
5757     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5758   }
5759 }
5760 }
5761 ; tmp_tmp_mem; });
5762   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5763   tmp_carry = CPU (h_cbit);
5764   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5765 {
5766   SI tmp_oldregval;
5767   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5768   {
5769     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5770     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5771     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5772   }
5773 }
5774 {
5775   {
5776     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5777     CPU (h_cbit) = opval;
5778     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5779   }
5780   {
5781     BI opval = LTHI (tmp_newval, 0);
5782     CPU (h_nbit) = opval;
5783     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5784   }
5785   {
5786     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5787     CPU (h_zbit) = opval;
5788     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5789   }
5790   {
5791     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5792     CPU (h_vbit) = opval;
5793     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5794   }
5795 {
5796   {
5797     BI opval = 0;
5798     CPU (h_xbit) = opval;
5799     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5800   }
5801   {
5802     BI opval = 0;
5803     SET_H_INSN_PREFIXED_P (opval);
5804     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5805   }
5806 }
5807 }
5808 }
5809
5810   abuf->written = written;
5811 #undef FLD
5812 }
5813   NEXT (vpc);
5814
5815   CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
5816 {
5817   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5818   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5819 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5820   int UNUSED written = 0;
5821   IADDR UNUSED pc = abuf->addr;
5822   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5823
5824 {
5825   SI tmp_tmpopd;
5826   SI tmp_tmpops;
5827   BI tmp_carry;
5828   SI tmp_newval;
5829   tmp_tmpops = ({   SI tmp_addr;
5830   SI tmp_tmp_mem;
5831   BI tmp_postinc;
5832   tmp_postinc = FLD (f_memmode);
5833 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5834 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
5835 ; if (NEBI (tmp_postinc, 0)) {
5836 {
5837 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5838   tmp_addr = ADDSI (tmp_addr, 4);
5839 }
5840   {
5841     SI opval = tmp_addr;
5842     SET_H_GR (FLD (f_operand1), opval);
5843     written |= (1 << 11);
5844     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5845   }
5846 }
5847 }
5848 ; tmp_tmp_mem; });
5849   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5850   tmp_carry = CPU (h_cbit);
5851   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5852   {
5853     SI opval = tmp_newval;
5854     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5855     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5856   }
5857 {
5858   {
5859     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5860     CPU (h_cbit) = opval;
5861     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5862   }
5863   {
5864     BI opval = LTSI (tmp_newval, 0);
5865     CPU (h_nbit) = opval;
5866     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5867   }
5868   {
5869     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5870     CPU (h_zbit) = opval;
5871     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5872   }
5873   {
5874     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5875     CPU (h_vbit) = opval;
5876     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5877   }
5878 {
5879   {
5880     BI opval = 0;
5881     CPU (h_xbit) = opval;
5882     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5883   }
5884   {
5885     BI opval = 0;
5886     SET_H_INSN_PREFIXED_P (opval);
5887     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5888   }
5889 }
5890 }
5891 }
5892
5893   abuf->written = written;
5894 #undef FLD
5895 }
5896   NEXT (vpc);
5897
5898   CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
5899 {
5900   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5901   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5902 #define FLD(f) abuf->fields.sfmt_addcbr.f
5903   int UNUSED written = 0;
5904   IADDR UNUSED pc = abuf->addr;
5905   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5906
5907 {
5908   QI tmp_tmpopd;
5909   QI tmp_tmpops;
5910   BI tmp_carry;
5911   QI tmp_newval;
5912   tmp_tmpops = FLD (f_indir_pc__byte);
5913   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5914   tmp_carry = CPU (h_cbit);
5915   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5916 {
5917   SI tmp_oldregval;
5918   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5919   {
5920     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5921     SET_H_GR (FLD (f_operand2), opval);
5922     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5923   }
5924 }
5925 {
5926   {
5927     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5928     CPU (h_cbit) = opval;
5929     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5930   }
5931   {
5932     BI opval = LTQI (tmp_newval, 0);
5933     CPU (h_nbit) = opval;
5934     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5935   }
5936   {
5937     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5938     CPU (h_zbit) = opval;
5939     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5940   }
5941   {
5942     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5943     CPU (h_vbit) = opval;
5944     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5945   }
5946 {
5947   {
5948     BI opval = 0;
5949     CPU (h_xbit) = opval;
5950     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5951   }
5952   {
5953     BI opval = 0;
5954     SET_H_INSN_PREFIXED_P (opval);
5955     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5956   }
5957 }
5958 }
5959 }
5960
5961 #undef FLD
5962 }
5963   NEXT (vpc);
5964
5965   CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
5966 {
5967   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5968   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5969 #define FLD(f) abuf->fields.sfmt_addcwr.f
5970   int UNUSED written = 0;
5971   IADDR UNUSED pc = abuf->addr;
5972   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5973
5974 {
5975   HI tmp_tmpopd;
5976   HI tmp_tmpops;
5977   BI tmp_carry;
5978   HI tmp_newval;
5979   tmp_tmpops = FLD (f_indir_pc__word);
5980   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5981   tmp_carry = CPU (h_cbit);
5982   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5983 {
5984   SI tmp_oldregval;
5985   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5986   {
5987     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5988     SET_H_GR (FLD (f_operand2), opval);
5989     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5990   }
5991 }
5992 {
5993   {
5994     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5995     CPU (h_cbit) = opval;
5996     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5997   }
5998   {
5999     BI opval = LTHI (tmp_newval, 0);
6000     CPU (h_nbit) = opval;
6001     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6002   }
6003   {
6004     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6005     CPU (h_zbit) = opval;
6006     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6007   }
6008   {
6009     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
6010     CPU (h_vbit) = opval;
6011     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6012   }
6013 {
6014   {
6015     BI opval = 0;
6016     CPU (h_xbit) = opval;
6017     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6018   }
6019   {
6020     BI opval = 0;
6021     SET_H_INSN_PREFIXED_P (opval);
6022     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6023   }
6024 }
6025 }
6026 }
6027
6028 #undef FLD
6029 }
6030   NEXT (vpc);
6031
6032   CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
6033 {
6034   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6035   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6036 #define FLD(f) abuf->fields.sfmt_addcdr.f
6037   int UNUSED written = 0;
6038   IADDR UNUSED pc = abuf->addr;
6039   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
6040
6041 {
6042   SI tmp_tmpopd;
6043   SI tmp_tmpops;
6044   BI tmp_carry;
6045   SI tmp_newval;
6046   tmp_tmpops = FLD (f_indir_pc__dword);
6047   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6048   tmp_carry = CPU (h_cbit);
6049   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6050   {
6051     SI opval = tmp_newval;
6052     SET_H_GR (FLD (f_operand2), opval);
6053     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6054   }
6055 {
6056   {
6057     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6058     CPU (h_cbit) = opval;
6059     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6060   }
6061   {
6062     BI opval = LTSI (tmp_newval, 0);
6063     CPU (h_nbit) = opval;
6064     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6065   }
6066   {
6067     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6068     CPU (h_zbit) = opval;
6069     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6070   }
6071   {
6072     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6073     CPU (h_vbit) = opval;
6074     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6075   }
6076 {
6077   {
6078     BI opval = 0;
6079     CPU (h_xbit) = opval;
6080     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6081   }
6082   {
6083     BI opval = 0;
6084     SET_H_INSN_PREFIXED_P (opval);
6085     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6086   }
6087 }
6088 }
6089 }
6090
6091 #undef FLD
6092 }
6093   NEXT (vpc);
6094
6095   CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
6096 {
6097   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6098   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6099 #define FLD(f) abuf->fields.sfmt_addc_m.f
6100   int UNUSED written = 0;
6101   IADDR UNUSED pc = abuf->addr;
6102   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6103
6104 {
6105   SI tmp_tmpopd;
6106   SI tmp_tmpops;
6107   BI tmp_carry;
6108   SI tmp_newval;
6109   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6110   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6111   tmp_carry = CPU (h_cbit);
6112   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6113   {
6114     SI opval = tmp_newval;
6115     SET_H_GR (FLD (f_operand2), opval);
6116     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6117   }
6118 {
6119   {
6120     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6121     CPU (h_cbit) = opval;
6122     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6123   }
6124   {
6125     BI opval = LTSI (tmp_newval, 0);
6126     CPU (h_nbit) = opval;
6127     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6128   }
6129   {
6130     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6131     CPU (h_zbit) = opval;
6132     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6133   }
6134   {
6135     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6136     CPU (h_vbit) = opval;
6137     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6138   }
6139 {
6140   {
6141     BI opval = 0;
6142     CPU (h_xbit) = opval;
6143     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6144   }
6145   {
6146     BI opval = 0;
6147     SET_H_INSN_PREFIXED_P (opval);
6148     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6149   }
6150 }
6151 }
6152 }
6153
6154 #undef FLD
6155 }
6156   NEXT (vpc);
6157
6158   CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
6159 {
6160   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6161   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6162 #define FLD(f) abuf->fields.sfmt_addc_m.f
6163   int UNUSED written = 0;
6164   IADDR UNUSED pc = abuf->addr;
6165   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6166
6167 {
6168   SI tmp_tmpopd;
6169   SI tmp_tmpops;
6170   BI tmp_carry;
6171   SI tmp_newval;
6172   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6173   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6174   tmp_carry = CPU (h_cbit);
6175   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6176   {
6177     SI opval = tmp_newval;
6178     SET_H_GR (FLD (f_operand2), opval);
6179     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6180   }
6181 {
6182   {
6183     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6184     CPU (h_cbit) = opval;
6185     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6186   }
6187   {
6188     BI opval = LTSI (tmp_newval, 0);
6189     CPU (h_nbit) = opval;
6190     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6191   }
6192   {
6193     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6194     CPU (h_zbit) = opval;
6195     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6196   }
6197   {
6198     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6199     CPU (h_vbit) = opval;
6200     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6201   }
6202 {
6203   {
6204     BI opval = 0;
6205     CPU (h_xbit) = opval;
6206     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6207   }
6208   {
6209     BI opval = 0;
6210     SET_H_INSN_PREFIXED_P (opval);
6211     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6212   }
6213 }
6214 }
6215 }
6216
6217 #undef FLD
6218 }
6219   NEXT (vpc);
6220
6221   CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
6222 {
6223   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6224   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6225 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6226   int UNUSED written = 0;
6227   IADDR UNUSED pc = abuf->addr;
6228   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6229
6230 {
6231   SI tmp_tmpopd;
6232   SI tmp_tmpops;
6233   BI tmp_carry;
6234   SI tmp_newval;
6235   tmp_tmpops = EXTQISI (({   SI tmp_addr;
6236   QI tmp_tmp_mem;
6237   BI tmp_postinc;
6238   tmp_postinc = FLD (f_memmode);
6239 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6240 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6241 ; if (NEBI (tmp_postinc, 0)) {
6242 {
6243 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6244   tmp_addr = ADDSI (tmp_addr, 1);
6245 }
6246   {
6247     SI opval = tmp_addr;
6248     SET_H_GR (FLD (f_operand1), opval);
6249     written |= (1 << 11);
6250     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6251   }
6252 }
6253 }
6254 ; tmp_tmp_mem; }));
6255   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6256   tmp_carry = CPU (h_cbit);
6257   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6258   {
6259     SI opval = tmp_newval;
6260     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6261     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6262   }
6263 {
6264   {
6265     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6266     CPU (h_cbit) = opval;
6267     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6268   }
6269   {
6270     BI opval = LTSI (tmp_newval, 0);
6271     CPU (h_nbit) = opval;
6272     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6273   }
6274   {
6275     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6276     CPU (h_zbit) = opval;
6277     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6278   }
6279   {
6280     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6281     CPU (h_vbit) = opval;
6282     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6283   }
6284 {
6285   {
6286     BI opval = 0;
6287     CPU (h_xbit) = opval;
6288     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6289   }
6290   {
6291     BI opval = 0;
6292     SET_H_INSN_PREFIXED_P (opval);
6293     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6294   }
6295 }
6296 }
6297 }
6298
6299   abuf->written = written;
6300 #undef FLD
6301 }
6302   NEXT (vpc);
6303
6304   CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
6305 {
6306   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6307   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6308 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6309   int UNUSED written = 0;
6310   IADDR UNUSED pc = abuf->addr;
6311   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6312
6313 {
6314   SI tmp_tmpopd;
6315   SI tmp_tmpops;
6316   BI tmp_carry;
6317   SI tmp_newval;
6318   tmp_tmpops = EXTHISI (({   SI tmp_addr;
6319   HI tmp_tmp_mem;
6320   BI tmp_postinc;
6321   tmp_postinc = FLD (f_memmode);
6322 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6323 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6324 ; if (NEBI (tmp_postinc, 0)) {
6325 {
6326 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6327   tmp_addr = ADDSI (tmp_addr, 2);
6328 }
6329   {
6330     SI opval = tmp_addr;
6331     SET_H_GR (FLD (f_operand1), opval);
6332     written |= (1 << 11);
6333     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6334   }
6335 }
6336 }
6337 ; tmp_tmp_mem; }));
6338   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6339   tmp_carry = CPU (h_cbit);
6340   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6341   {
6342     SI opval = tmp_newval;
6343     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6344     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6345   }
6346 {
6347   {
6348     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6349     CPU (h_cbit) = opval;
6350     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6351   }
6352   {
6353     BI opval = LTSI (tmp_newval, 0);
6354     CPU (h_nbit) = opval;
6355     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6356   }
6357   {
6358     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6359     CPU (h_zbit) = opval;
6360     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6361   }
6362   {
6363     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6364     CPU (h_vbit) = opval;
6365     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6366   }
6367 {
6368   {
6369     BI opval = 0;
6370     CPU (h_xbit) = opval;
6371     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6372   }
6373   {
6374     BI opval = 0;
6375     SET_H_INSN_PREFIXED_P (opval);
6376     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6377   }
6378 }
6379 }
6380 }
6381
6382   abuf->written = written;
6383 #undef FLD
6384 }
6385   NEXT (vpc);
6386
6387   CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
6388 {
6389   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6390   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6391 #define FLD(f) abuf->fields.sfmt_addcbr.f
6392   int UNUSED written = 0;
6393   IADDR UNUSED pc = abuf->addr;
6394   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6395
6396 {
6397   SI tmp_tmpopd;
6398   SI tmp_tmpops;
6399   BI tmp_carry;
6400   SI tmp_newval;
6401   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6402   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6403   tmp_carry = CPU (h_cbit);
6404   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6405   {
6406     SI opval = tmp_newval;
6407     SET_H_GR (FLD (f_operand2), opval);
6408     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6409   }
6410 {
6411   {
6412     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6413     CPU (h_cbit) = opval;
6414     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6415   }
6416   {
6417     BI opval = LTSI (tmp_newval, 0);
6418     CPU (h_nbit) = opval;
6419     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6420   }
6421   {
6422     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6423     CPU (h_zbit) = opval;
6424     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6425   }
6426   {
6427     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6428     CPU (h_vbit) = opval;
6429     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6430   }
6431 {
6432   {
6433     BI opval = 0;
6434     CPU (h_xbit) = opval;
6435     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6436   }
6437   {
6438     BI opval = 0;
6439     SET_H_INSN_PREFIXED_P (opval);
6440     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6441   }
6442 }
6443 }
6444 }
6445
6446 #undef FLD
6447 }
6448   NEXT (vpc);
6449
6450   CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
6451 {
6452   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6453   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6454 #define FLD(f) abuf->fields.sfmt_addcwr.f
6455   int UNUSED written = 0;
6456   IADDR UNUSED pc = abuf->addr;
6457   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6458
6459 {
6460   SI tmp_tmpopd;
6461   SI tmp_tmpops;
6462   BI tmp_carry;
6463   SI tmp_newval;
6464   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6465   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6466   tmp_carry = CPU (h_cbit);
6467   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6468   {
6469     SI opval = tmp_newval;
6470     SET_H_GR (FLD (f_operand2), opval);
6471     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6472   }
6473 {
6474   {
6475     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6476     CPU (h_cbit) = opval;
6477     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6478   }
6479   {
6480     BI opval = LTSI (tmp_newval, 0);
6481     CPU (h_nbit) = opval;
6482     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6483   }
6484   {
6485     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6486     CPU (h_zbit) = opval;
6487     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6488   }
6489   {
6490     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6491     CPU (h_vbit) = opval;
6492     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6493   }
6494 {
6495   {
6496     BI opval = 0;
6497     CPU (h_xbit) = opval;
6498     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6499   }
6500   {
6501     BI opval = 0;
6502     SET_H_INSN_PREFIXED_P (opval);
6503     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6504   }
6505 }
6506 }
6507 }
6508
6509 #undef FLD
6510 }
6511   NEXT (vpc);
6512
6513   CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
6514 {
6515   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6516   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6517 #define FLD(f) abuf->fields.sfmt_addc_m.f
6518   int UNUSED written = 0;
6519   IADDR UNUSED pc = abuf->addr;
6520   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6521
6522 {
6523   SI tmp_tmpopd;
6524   SI tmp_tmpops;
6525   BI tmp_carry;
6526   SI tmp_newval;
6527   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6528   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6529   tmp_carry = CPU (h_cbit);
6530   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6531   {
6532     SI opval = tmp_newval;
6533     SET_H_GR (FLD (f_operand2), opval);
6534     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6535   }
6536 {
6537   {
6538     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6539     CPU (h_cbit) = opval;
6540     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6541   }
6542   {
6543     BI opval = LTSI (tmp_newval, 0);
6544     CPU (h_nbit) = opval;
6545     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6546   }
6547   {
6548     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6549     CPU (h_zbit) = opval;
6550     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6551   }
6552   {
6553     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6554     CPU (h_vbit) = opval;
6555     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6556   }
6557 {
6558   {
6559     BI opval = 0;
6560     CPU (h_xbit) = opval;
6561     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6562   }
6563   {
6564     BI opval = 0;
6565     SET_H_INSN_PREFIXED_P (opval);
6566     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6567   }
6568 }
6569 }
6570 }
6571
6572 #undef FLD
6573 }
6574   NEXT (vpc);
6575
6576   CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
6577 {
6578   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6579   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6580 #define FLD(f) abuf->fields.sfmt_addc_m.f
6581   int UNUSED written = 0;
6582   IADDR UNUSED pc = abuf->addr;
6583   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6584
6585 {
6586   SI tmp_tmpopd;
6587   SI tmp_tmpops;
6588   BI tmp_carry;
6589   SI tmp_newval;
6590   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6591   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6592   tmp_carry = CPU (h_cbit);
6593   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6594   {
6595     SI opval = tmp_newval;
6596     SET_H_GR (FLD (f_operand2), opval);
6597     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6598   }
6599 {
6600   {
6601     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6602     CPU (h_cbit) = opval;
6603     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6604   }
6605   {
6606     BI opval = LTSI (tmp_newval, 0);
6607     CPU (h_nbit) = opval;
6608     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6609   }
6610   {
6611     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6612     CPU (h_zbit) = opval;
6613     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6614   }
6615   {
6616     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6617     CPU (h_vbit) = opval;
6618     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6619   }
6620 {
6621   {
6622     BI opval = 0;
6623     CPU (h_xbit) = opval;
6624     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6625   }
6626   {
6627     BI opval = 0;
6628     SET_H_INSN_PREFIXED_P (opval);
6629     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6630   }
6631 }
6632 }
6633 }
6634
6635 #undef FLD
6636 }
6637   NEXT (vpc);
6638
6639   CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
6640 {
6641   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6642   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6643 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6644   int UNUSED written = 0;
6645   IADDR UNUSED pc = abuf->addr;
6646   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6647
6648 {
6649   SI tmp_tmpopd;
6650   SI tmp_tmpops;
6651   BI tmp_carry;
6652   SI tmp_newval;
6653   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
6654   QI tmp_tmp_mem;
6655   BI tmp_postinc;
6656   tmp_postinc = FLD (f_memmode);
6657 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6658 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6659 ; if (NEBI (tmp_postinc, 0)) {
6660 {
6661 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6662   tmp_addr = ADDSI (tmp_addr, 1);
6663 }
6664   {
6665     SI opval = tmp_addr;
6666     SET_H_GR (FLD (f_operand1), opval);
6667     written |= (1 << 11);
6668     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6669   }
6670 }
6671 }
6672 ; tmp_tmp_mem; }));
6673   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6674   tmp_carry = CPU (h_cbit);
6675   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6676   {
6677     SI opval = tmp_newval;
6678     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6679     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6680   }
6681 {
6682   {
6683     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6684     CPU (h_cbit) = opval;
6685     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6686   }
6687   {
6688     BI opval = LTSI (tmp_newval, 0);
6689     CPU (h_nbit) = opval;
6690     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6691   }
6692   {
6693     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6694     CPU (h_zbit) = opval;
6695     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6696   }
6697   {
6698     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6699     CPU (h_vbit) = opval;
6700     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6701   }
6702 {
6703   {
6704     BI opval = 0;
6705     CPU (h_xbit) = opval;
6706     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6707   }
6708   {
6709     BI opval = 0;
6710     SET_H_INSN_PREFIXED_P (opval);
6711     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6712   }
6713 }
6714 }
6715 }
6716
6717   abuf->written = written;
6718 #undef FLD
6719 }
6720   NEXT (vpc);
6721
6722   CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
6723 {
6724   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6725   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6726 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6727   int UNUSED written = 0;
6728   IADDR UNUSED pc = abuf->addr;
6729   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6730
6731 {
6732   SI tmp_tmpopd;
6733   SI tmp_tmpops;
6734   BI tmp_carry;
6735   SI tmp_newval;
6736   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
6737   HI tmp_tmp_mem;
6738   BI tmp_postinc;
6739   tmp_postinc = FLD (f_memmode);
6740 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6741 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6742 ; if (NEBI (tmp_postinc, 0)) {
6743 {
6744 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6745   tmp_addr = ADDSI (tmp_addr, 2);
6746 }
6747   {
6748     SI opval = tmp_addr;
6749     SET_H_GR (FLD (f_operand1), opval);
6750     written |= (1 << 11);
6751     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6752   }
6753 }
6754 }
6755 ; tmp_tmp_mem; }));
6756   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6757   tmp_carry = CPU (h_cbit);
6758   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6759   {
6760     SI opval = tmp_newval;
6761     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6762     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6763   }
6764 {
6765   {
6766     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6767     CPU (h_cbit) = opval;
6768     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6769   }
6770   {
6771     BI opval = LTSI (tmp_newval, 0);
6772     CPU (h_nbit) = opval;
6773     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6774   }
6775   {
6776     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6777     CPU (h_zbit) = opval;
6778     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6779   }
6780   {
6781     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6782     CPU (h_vbit) = opval;
6783     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6784   }
6785 {
6786   {
6787     BI opval = 0;
6788     CPU (h_xbit) = opval;
6789     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6790   }
6791   {
6792     BI opval = 0;
6793     SET_H_INSN_PREFIXED_P (opval);
6794     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6795   }
6796 }
6797 }
6798 }
6799
6800   abuf->written = written;
6801 #undef FLD
6802 }
6803   NEXT (vpc);
6804
6805   CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
6806 {
6807   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6808   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6809 #define FLD(f) abuf->fields.sfmt_addcbr.f
6810   int UNUSED written = 0;
6811   IADDR UNUSED pc = abuf->addr;
6812   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6813
6814 {
6815   SI tmp_tmpopd;
6816   SI tmp_tmpops;
6817   BI tmp_carry;
6818   SI tmp_newval;
6819   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6820   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6821   tmp_carry = CPU (h_cbit);
6822   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6823   {
6824     SI opval = tmp_newval;
6825     SET_H_GR (FLD (f_operand2), opval);
6826     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6827   }
6828 {
6829   {
6830     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6831     CPU (h_cbit) = opval;
6832     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6833   }
6834   {
6835     BI opval = LTSI (tmp_newval, 0);
6836     CPU (h_nbit) = opval;
6837     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6838   }
6839   {
6840     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6841     CPU (h_zbit) = opval;
6842     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6843   }
6844   {
6845     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6846     CPU (h_vbit) = opval;
6847     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6848   }
6849 {
6850   {
6851     BI opval = 0;
6852     CPU (h_xbit) = opval;
6853     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6854   }
6855   {
6856     BI opval = 0;
6857     SET_H_INSN_PREFIXED_P (opval);
6858     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6859   }
6860 }
6861 }
6862 }
6863
6864 #undef FLD
6865 }
6866   NEXT (vpc);
6867
6868   CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
6869 {
6870   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6871   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6872 #define FLD(f) abuf->fields.sfmt_addcwr.f
6873   int UNUSED written = 0;
6874   IADDR UNUSED pc = abuf->addr;
6875   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6876
6877 {
6878   SI tmp_tmpopd;
6879   SI tmp_tmpops;
6880   BI tmp_carry;
6881   SI tmp_newval;
6882   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6883   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6884   tmp_carry = CPU (h_cbit);
6885   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6886   {
6887     SI opval = tmp_newval;
6888     SET_H_GR (FLD (f_operand2), opval);
6889     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6890   }
6891 {
6892   {
6893     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6894     CPU (h_cbit) = opval;
6895     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6896   }
6897   {
6898     BI opval = LTSI (tmp_newval, 0);
6899     CPU (h_nbit) = opval;
6900     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6901   }
6902   {
6903     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6904     CPU (h_zbit) = opval;
6905     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6906   }
6907   {
6908     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6909     CPU (h_vbit) = opval;
6910     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6911   }
6912 {
6913   {
6914     BI opval = 0;
6915     CPU (h_xbit) = opval;
6916     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6917   }
6918   {
6919     BI opval = 0;
6920     SET_H_INSN_PREFIXED_P (opval);
6921     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6922   }
6923 }
6924 }
6925 }
6926
6927 #undef FLD
6928 }
6929   NEXT (vpc);
6930
6931   CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
6932 {
6933   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6934   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6935 #define FLD(f) abuf->fields.sfmt_addc_m.f
6936   int UNUSED written = 0;
6937   IADDR UNUSED pc = abuf->addr;
6938   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6939
6940 {
6941   QI tmp_tmpopd;
6942   QI tmp_tmpops;
6943   BI tmp_carry;
6944   QI tmp_newval;
6945   tmp_tmpops = GET_H_GR (FLD (f_operand1));
6946   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6947   tmp_carry = CPU (h_cbit);
6948   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6949 {
6950   SI tmp_oldregval;
6951   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
6952   {
6953     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
6954     SET_H_GR (FLD (f_operand2), opval);
6955     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6956   }
6957 }
6958 {
6959   {
6960     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
6961     CPU (h_cbit) = opval;
6962     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6963   }
6964   {
6965     BI opval = LTQI (tmp_newval, 0);
6966     CPU (h_nbit) = opval;
6967     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6968   }
6969   {
6970     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6971     CPU (h_zbit) = opval;
6972     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6973   }
6974   {
6975     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
6976     CPU (h_vbit) = opval;
6977     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6978   }
6979 {
6980   {
6981     BI opval = 0;
6982     CPU (h_xbit) = opval;
6983     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6984   }
6985   {
6986     BI opval = 0;
6987     SET_H_INSN_PREFIXED_P (opval);
6988     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6989   }
6990 }
6991 }
6992 }
6993
6994 #undef FLD
6995 }
6996   NEXT (vpc);
6997
6998   CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
6999 {
7000   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7001   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7002 #define FLD(f) abuf->fields.sfmt_addc_m.f
7003   int UNUSED written = 0;
7004   IADDR UNUSED pc = abuf->addr;
7005   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7006
7007 {
7008   HI tmp_tmpopd;
7009   HI tmp_tmpops;
7010   BI tmp_carry;
7011   HI tmp_newval;
7012   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7013   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7014   tmp_carry = CPU (h_cbit);
7015   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7016 {
7017   SI tmp_oldregval;
7018   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7019   {
7020     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7021     SET_H_GR (FLD (f_operand2), opval);
7022     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7023   }
7024 }
7025 {
7026   {
7027     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7028     CPU (h_cbit) = opval;
7029     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7030   }
7031   {
7032     BI opval = LTHI (tmp_newval, 0);
7033     CPU (h_nbit) = opval;
7034     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7035   }
7036   {
7037     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7038     CPU (h_zbit) = opval;
7039     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7040   }
7041   {
7042     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7043     CPU (h_vbit) = opval;
7044     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7045   }
7046 {
7047   {
7048     BI opval = 0;
7049     CPU (h_xbit) = opval;
7050     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7051   }
7052   {
7053     BI opval = 0;
7054     SET_H_INSN_PREFIXED_P (opval);
7055     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7056   }
7057 }
7058 }
7059 }
7060
7061 #undef FLD
7062 }
7063   NEXT (vpc);
7064
7065   CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
7066 {
7067   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7068   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7069 #define FLD(f) abuf->fields.sfmt_addc_m.f
7070   int UNUSED written = 0;
7071   IADDR UNUSED pc = abuf->addr;
7072   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7073
7074 {
7075   SI tmp_tmpopd;
7076   SI tmp_tmpops;
7077   BI tmp_carry;
7078   SI tmp_newval;
7079   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7080   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7081   tmp_carry = CPU (h_cbit);
7082   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7083   {
7084     SI opval = tmp_newval;
7085     SET_H_GR (FLD (f_operand2), opval);
7086     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7087   }
7088 {
7089   {
7090     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7091     CPU (h_cbit) = opval;
7092     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7093   }
7094   {
7095     BI opval = LTSI (tmp_newval, 0);
7096     CPU (h_nbit) = opval;
7097     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7098   }
7099   {
7100     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7101     CPU (h_zbit) = opval;
7102     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7103   }
7104   {
7105     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7106     CPU (h_vbit) = opval;
7107     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7108   }
7109 {
7110   {
7111     BI opval = 0;
7112     CPU (h_xbit) = opval;
7113     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7114   }
7115   {
7116     BI opval = 0;
7117     SET_H_INSN_PREFIXED_P (opval);
7118     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7119   }
7120 }
7121 }
7122 }
7123
7124 #undef FLD
7125 }
7126   NEXT (vpc);
7127
7128   CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
7129 {
7130   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7131   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7132 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7133   int UNUSED written = 0;
7134   IADDR UNUSED pc = abuf->addr;
7135   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7136
7137 {
7138   QI tmp_tmpopd;
7139   QI tmp_tmpops;
7140   BI tmp_carry;
7141   QI tmp_newval;
7142   tmp_tmpops = ({   SI tmp_addr;
7143   QI tmp_tmp_mem;
7144   BI tmp_postinc;
7145   tmp_postinc = FLD (f_memmode);
7146 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7147 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7148 ; if (NEBI (tmp_postinc, 0)) {
7149 {
7150 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7151   tmp_addr = ADDSI (tmp_addr, 1);
7152 }
7153   {
7154     SI opval = tmp_addr;
7155     SET_H_GR (FLD (f_operand1), opval);
7156     written |= (1 << 12);
7157     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7158   }
7159 }
7160 }
7161 ; tmp_tmp_mem; });
7162   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7163   tmp_carry = CPU (h_cbit);
7164   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7165 {
7166   SI tmp_oldregval;
7167   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7168   {
7169     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7170     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7171     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7172   }
7173 }
7174 {
7175   {
7176     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7177     CPU (h_cbit) = opval;
7178     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7179   }
7180   {
7181     BI opval = LTQI (tmp_newval, 0);
7182     CPU (h_nbit) = opval;
7183     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7184   }
7185   {
7186     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7187     CPU (h_zbit) = opval;
7188     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7189   }
7190   {
7191     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7192     CPU (h_vbit) = opval;
7193     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7194   }
7195 {
7196   {
7197     BI opval = 0;
7198     CPU (h_xbit) = opval;
7199     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7200   }
7201   {
7202     BI opval = 0;
7203     SET_H_INSN_PREFIXED_P (opval);
7204     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7205   }
7206 }
7207 }
7208 }
7209
7210   abuf->written = written;
7211 #undef FLD
7212 }
7213   NEXT (vpc);
7214
7215   CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
7216 {
7217   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7218   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7219 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7220   int UNUSED written = 0;
7221   IADDR UNUSED pc = abuf->addr;
7222   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7223
7224 {
7225   HI tmp_tmpopd;
7226   HI tmp_tmpops;
7227   BI tmp_carry;
7228   HI tmp_newval;
7229   tmp_tmpops = ({   SI tmp_addr;
7230   HI tmp_tmp_mem;
7231   BI tmp_postinc;
7232   tmp_postinc = FLD (f_memmode);
7233 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7234 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7235 ; if (NEBI (tmp_postinc, 0)) {
7236 {
7237 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7238   tmp_addr = ADDSI (tmp_addr, 2);
7239 }
7240   {
7241     SI opval = tmp_addr;
7242     SET_H_GR (FLD (f_operand1), opval);
7243     written |= (1 << 12);
7244     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7245   }
7246 }
7247 }
7248 ; tmp_tmp_mem; });
7249   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7250   tmp_carry = CPU (h_cbit);
7251   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7252 {
7253   SI tmp_oldregval;
7254   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7255   {
7256     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7257     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7258     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7259   }
7260 }
7261 {
7262   {
7263     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7264     CPU (h_cbit) = opval;
7265     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7266   }
7267   {
7268     BI opval = LTHI (tmp_newval, 0);
7269     CPU (h_nbit) = opval;
7270     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7271   }
7272   {
7273     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7274     CPU (h_zbit) = opval;
7275     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7276   }
7277   {
7278     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7279     CPU (h_vbit) = opval;
7280     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7281   }
7282 {
7283   {
7284     BI opval = 0;
7285     CPU (h_xbit) = opval;
7286     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7287   }
7288   {
7289     BI opval = 0;
7290     SET_H_INSN_PREFIXED_P (opval);
7291     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7292   }
7293 }
7294 }
7295 }
7296
7297   abuf->written = written;
7298 #undef FLD
7299 }
7300   NEXT (vpc);
7301
7302   CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
7303 {
7304   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7305   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7306 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7307   int UNUSED written = 0;
7308   IADDR UNUSED pc = abuf->addr;
7309   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7310
7311 {
7312   SI tmp_tmpopd;
7313   SI tmp_tmpops;
7314   BI tmp_carry;
7315   SI tmp_newval;
7316   tmp_tmpops = ({   SI tmp_addr;
7317   SI tmp_tmp_mem;
7318   BI tmp_postinc;
7319   tmp_postinc = FLD (f_memmode);
7320 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7321 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
7322 ; if (NEBI (tmp_postinc, 0)) {
7323 {
7324 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7325   tmp_addr = ADDSI (tmp_addr, 4);
7326 }
7327   {
7328     SI opval = tmp_addr;
7329     SET_H_GR (FLD (f_operand1), opval);
7330     written |= (1 << 11);
7331     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7332   }
7333 }
7334 }
7335 ; tmp_tmp_mem; });
7336   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7337   tmp_carry = CPU (h_cbit);
7338   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7339   {
7340     SI opval = tmp_newval;
7341     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7342     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7343   }
7344 {
7345   {
7346     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7347     CPU (h_cbit) = opval;
7348     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7349   }
7350   {
7351     BI opval = LTSI (tmp_newval, 0);
7352     CPU (h_nbit) = opval;
7353     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7354   }
7355   {
7356     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7357     CPU (h_zbit) = opval;
7358     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7359   }
7360   {
7361     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7362     CPU (h_vbit) = opval;
7363     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7364   }
7365 {
7366   {
7367     BI opval = 0;
7368     CPU (h_xbit) = opval;
7369     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7370   }
7371   {
7372     BI opval = 0;
7373     SET_H_INSN_PREFIXED_P (opval);
7374     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7375   }
7376 }
7377 }
7378 }
7379
7380   abuf->written = written;
7381 #undef FLD
7382 }
7383   NEXT (vpc);
7384
7385   CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
7386 {
7387   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7388   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7389 #define FLD(f) abuf->fields.sfmt_addcbr.f
7390   int UNUSED written = 0;
7391   IADDR UNUSED pc = abuf->addr;
7392   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7393
7394 {
7395   QI tmp_tmpopd;
7396   QI tmp_tmpops;
7397   BI tmp_carry;
7398   QI tmp_newval;
7399   tmp_tmpops = FLD (f_indir_pc__byte);
7400   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7401   tmp_carry = CPU (h_cbit);
7402   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7403 {
7404   SI tmp_oldregval;
7405   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7406   {
7407     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7408     SET_H_GR (FLD (f_operand2), opval);
7409     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7410   }
7411 }
7412 {
7413   {
7414     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7415     CPU (h_cbit) = opval;
7416     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7417   }
7418   {
7419     BI opval = LTQI (tmp_newval, 0);
7420     CPU (h_nbit) = opval;
7421     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7422   }
7423   {
7424     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7425     CPU (h_zbit) = opval;
7426     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7427   }
7428   {
7429     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7430     CPU (h_vbit) = opval;
7431     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7432   }
7433 {
7434   {
7435     BI opval = 0;
7436     CPU (h_xbit) = opval;
7437     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7438   }
7439   {
7440     BI opval = 0;
7441     SET_H_INSN_PREFIXED_P (opval);
7442     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7443   }
7444 }
7445 }
7446 }
7447
7448 #undef FLD
7449 }
7450   NEXT (vpc);
7451
7452   CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
7453 {
7454   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7455   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7456 #define FLD(f) abuf->fields.sfmt_addcwr.f
7457   int UNUSED written = 0;
7458   IADDR UNUSED pc = abuf->addr;
7459   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7460
7461 {
7462   HI tmp_tmpopd;
7463   HI tmp_tmpops;
7464   BI tmp_carry;
7465   HI tmp_newval;
7466   tmp_tmpops = FLD (f_indir_pc__word);
7467   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7468   tmp_carry = CPU (h_cbit);
7469   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7470 {
7471   SI tmp_oldregval;
7472   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7473   {
7474     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7475     SET_H_GR (FLD (f_operand2), opval);
7476     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7477   }
7478 }
7479 {
7480   {
7481     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7482     CPU (h_cbit) = opval;
7483     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7484   }
7485   {
7486     BI opval = LTHI (tmp_newval, 0);
7487     CPU (h_nbit) = opval;
7488     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7489   }
7490   {
7491     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7492     CPU (h_zbit) = opval;
7493     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7494   }
7495   {
7496     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7497     CPU (h_vbit) = opval;
7498     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7499   }
7500 {
7501   {
7502     BI opval = 0;
7503     CPU (h_xbit) = opval;
7504     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7505   }
7506   {
7507     BI opval = 0;
7508     SET_H_INSN_PREFIXED_P (opval);
7509     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7510   }
7511 }
7512 }
7513 }
7514
7515 #undef FLD
7516 }
7517   NEXT (vpc);
7518
7519   CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
7520 {
7521   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7522   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7523 #define FLD(f) abuf->fields.sfmt_addcdr.f
7524   int UNUSED written = 0;
7525   IADDR UNUSED pc = abuf->addr;
7526   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
7527
7528 {
7529   SI tmp_tmpopd;
7530   SI tmp_tmpops;
7531   BI tmp_carry;
7532   SI tmp_newval;
7533   tmp_tmpops = FLD (f_indir_pc__dword);
7534   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7535   tmp_carry = CPU (h_cbit);
7536   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7537   {
7538     SI opval = tmp_newval;
7539     SET_H_GR (FLD (f_operand2), opval);
7540     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7541   }
7542 {
7543   {
7544     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7545     CPU (h_cbit) = opval;
7546     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7547   }
7548   {
7549     BI opval = LTSI (tmp_newval, 0);
7550     CPU (h_nbit) = opval;
7551     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7552   }
7553   {
7554     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7555     CPU (h_zbit) = opval;
7556     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7557   }
7558   {
7559     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7560     CPU (h_vbit) = opval;
7561     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7562   }
7563 {
7564   {
7565     BI opval = 0;
7566     CPU (h_xbit) = opval;
7567     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7568   }
7569   {
7570     BI opval = 0;
7571     SET_H_INSN_PREFIXED_P (opval);
7572     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7573   }
7574 }
7575 }
7576 }
7577
7578 #undef FLD
7579 }
7580   NEXT (vpc);
7581
7582   CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
7583 {
7584   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7585   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7586 #define FLD(f) abuf->fields.sfmt_addc_m.f
7587   int UNUSED written = 0;
7588   IADDR UNUSED pc = abuf->addr;
7589   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7590
7591 {
7592   SI tmp_tmpopd;
7593   SI tmp_tmpops;
7594   BI tmp_carry;
7595   SI tmp_newval;
7596   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
7597   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7598   tmp_carry = CPU (h_cbit);
7599   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7600   {
7601     SI opval = tmp_newval;
7602     SET_H_GR (FLD (f_operand2), opval);
7603     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7604   }
7605 {
7606   {
7607     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7608     CPU (h_cbit) = opval;
7609     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7610   }
7611   {
7612     BI opval = LTSI (tmp_newval, 0);
7613     CPU (h_nbit) = opval;
7614     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7615   }
7616   {
7617     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7618     CPU (h_zbit) = opval;
7619     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7620   }
7621   {
7622     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7623     CPU (h_vbit) = opval;
7624     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7625   }
7626 {
7627   {
7628     BI opval = 0;
7629     CPU (h_xbit) = opval;
7630     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7631   }
7632   {
7633     BI opval = 0;
7634     SET_H_INSN_PREFIXED_P (opval);
7635     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7636   }
7637 }
7638 }
7639 }
7640
7641 #undef FLD
7642 }
7643   NEXT (vpc);
7644
7645   CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
7646 {
7647   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7648   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7649 #define FLD(f) abuf->fields.sfmt_addc_m.f
7650   int UNUSED written = 0;
7651   IADDR UNUSED pc = abuf->addr;
7652   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7653
7654 {
7655   SI tmp_tmpopd;
7656   SI tmp_tmpops;
7657   BI tmp_carry;
7658   SI tmp_newval;
7659   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
7660   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7661   tmp_carry = CPU (h_cbit);
7662   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7663   {
7664     SI opval = tmp_newval;
7665     SET_H_GR (FLD (f_operand2), opval);
7666     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7667   }
7668 {
7669   {
7670     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7671     CPU (h_cbit) = opval;
7672     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7673   }
7674   {
7675     BI opval = LTSI (tmp_newval, 0);
7676     CPU (h_nbit) = opval;
7677     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7678   }
7679   {
7680     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7681     CPU (h_zbit) = opval;
7682     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7683   }
7684   {
7685     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7686     CPU (h_vbit) = opval;
7687     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7688   }
7689 {
7690   {
7691     BI opval = 0;
7692     CPU (h_xbit) = opval;
7693     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7694   }
7695   {
7696     BI opval = 0;
7697     SET_H_INSN_PREFIXED_P (opval);
7698     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7699   }
7700 }
7701 }
7702 }
7703
7704 #undef FLD
7705 }
7706   NEXT (vpc);
7707
7708   CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
7709 {
7710   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7711   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7712 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7713   int UNUSED written = 0;
7714   IADDR UNUSED pc = abuf->addr;
7715   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7716
7717 {
7718   SI tmp_tmpopd;
7719   SI tmp_tmpops;
7720   BI tmp_carry;
7721   SI tmp_newval;
7722   tmp_tmpops = EXTQISI (({   SI tmp_addr;
7723   QI tmp_tmp_mem;
7724   BI tmp_postinc;
7725   tmp_postinc = FLD (f_memmode);
7726 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7727 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7728 ; if (NEBI (tmp_postinc, 0)) {
7729 {
7730 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7731   tmp_addr = ADDSI (tmp_addr, 1);
7732 }
7733   {
7734     SI opval = tmp_addr;
7735     SET_H_GR (FLD (f_operand1), opval);
7736     written |= (1 << 11);
7737     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7738   }
7739 }
7740 }
7741 ; tmp_tmp_mem; }));
7742   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7743   tmp_carry = CPU (h_cbit);
7744   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7745   {
7746     SI opval = tmp_newval;
7747     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7748     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7749   }
7750 {
7751   {
7752     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7753     CPU (h_cbit) = opval;
7754     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7755   }
7756   {
7757     BI opval = LTSI (tmp_newval, 0);
7758     CPU (h_nbit) = opval;
7759     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7760   }
7761   {
7762     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7763     CPU (h_zbit) = opval;
7764     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7765   }
7766   {
7767     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7768     CPU (h_vbit) = opval;
7769     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7770   }
7771 {
7772   {
7773     BI opval = 0;
7774     CPU (h_xbit) = opval;
7775     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7776   }
7777   {
7778     BI opval = 0;
7779     SET_H_INSN_PREFIXED_P (opval);
7780     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7781   }
7782 }
7783 }
7784 }
7785
7786   abuf->written = written;
7787 #undef FLD
7788 }
7789   NEXT (vpc);
7790
7791   CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
7792 {
7793   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7794   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7795 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7796   int UNUSED written = 0;
7797   IADDR UNUSED pc = abuf->addr;
7798   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7799
7800 {
7801   SI tmp_tmpopd;
7802   SI tmp_tmpops;
7803   BI tmp_carry;
7804   SI tmp_newval;
7805   tmp_tmpops = EXTHISI (({   SI tmp_addr;
7806   HI tmp_tmp_mem;
7807   BI tmp_postinc;
7808   tmp_postinc = FLD (f_memmode);
7809 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7810 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7811 ; if (NEBI (tmp_postinc, 0)) {
7812 {
7813 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7814   tmp_addr = ADDSI (tmp_addr, 2);
7815 }
7816   {
7817     SI opval = tmp_addr;
7818     SET_H_GR (FLD (f_operand1), opval);
7819     written |= (1 << 11);
7820     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7821   }
7822 }
7823 }
7824 ; tmp_tmp_mem; }));
7825   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7826   tmp_carry = CPU (h_cbit);
7827   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7828   {
7829     SI opval = tmp_newval;
7830     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7831     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7832   }
7833 {
7834   {
7835     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7836     CPU (h_cbit) = opval;
7837     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7838   }
7839   {
7840     BI opval = LTSI (tmp_newval, 0);
7841     CPU (h_nbit) = opval;
7842     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7843   }
7844   {
7845     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7846     CPU (h_zbit) = opval;
7847     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7848   }
7849   {
7850     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7851     CPU (h_vbit) = opval;
7852     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7853   }
7854 {
7855   {
7856     BI opval = 0;
7857     CPU (h_xbit) = opval;
7858     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7859   }
7860   {
7861     BI opval = 0;
7862     SET_H_INSN_PREFIXED_P (opval);
7863     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7864   }
7865 }
7866 }
7867 }
7868
7869   abuf->written = written;
7870 #undef FLD
7871 }
7872   NEXT (vpc);
7873
7874   CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
7875 {
7876   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7877   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7878 #define FLD(f) abuf->fields.sfmt_addcbr.f
7879   int UNUSED written = 0;
7880   IADDR UNUSED pc = abuf->addr;
7881   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7882
7883 {
7884   SI tmp_tmpopd;
7885   SI tmp_tmpops;
7886   BI tmp_carry;
7887   SI tmp_newval;
7888   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
7889   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7890   tmp_carry = CPU (h_cbit);
7891   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7892   {
7893     SI opval = tmp_newval;
7894     SET_H_GR (FLD (f_operand2), opval);
7895     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7896   }
7897 {
7898   {
7899     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7900     CPU (h_cbit) = opval;
7901     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7902   }
7903   {
7904     BI opval = LTSI (tmp_newval, 0);
7905     CPU (h_nbit) = opval;
7906     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7907   }
7908   {
7909     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7910     CPU (h_zbit) = opval;
7911     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7912   }
7913   {
7914     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7915     CPU (h_vbit) = opval;
7916     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7917   }
7918 {
7919   {
7920     BI opval = 0;
7921     CPU (h_xbit) = opval;
7922     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7923   }
7924   {
7925     BI opval = 0;
7926     SET_H_INSN_PREFIXED_P (opval);
7927     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7928   }
7929 }
7930 }
7931 }
7932
7933 #undef FLD
7934 }
7935   NEXT (vpc);
7936
7937   CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
7938 {
7939   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7940   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7941 #define FLD(f) abuf->fields.sfmt_addcwr.f
7942   int UNUSED written = 0;
7943   IADDR UNUSED pc = abuf->addr;
7944   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7945
7946 {
7947   SI tmp_tmpopd;
7948   SI tmp_tmpops;
7949   BI tmp_carry;
7950   SI tmp_newval;
7951   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
7952   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7953   tmp_carry = CPU (h_cbit);
7954   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7955   {
7956     SI opval = tmp_newval;
7957     SET_H_GR (FLD (f_operand2), opval);
7958     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7959   }
7960 {
7961   {
7962     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7963     CPU (h_cbit) = opval;
7964     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7965   }
7966   {
7967     BI opval = LTSI (tmp_newval, 0);
7968     CPU (h_nbit) = opval;
7969     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7970   }
7971   {
7972     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7973     CPU (h_zbit) = opval;
7974     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7975   }
7976   {
7977     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7978     CPU (h_vbit) = opval;
7979     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7980   }
7981 {
7982   {
7983     BI opval = 0;
7984     CPU (h_xbit) = opval;
7985     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7986   }
7987   {
7988     BI opval = 0;
7989     SET_H_INSN_PREFIXED_P (opval);
7990     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7991   }
7992 }
7993 }
7994 }
7995
7996 #undef FLD
7997 }
7998   NEXT (vpc);
7999
8000   CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
8001 {
8002   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8003   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8004 #define FLD(f) abuf->fields.sfmt_addc_m.f
8005   int UNUSED written = 0;
8006   IADDR UNUSED pc = abuf->addr;
8007   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8008
8009 {
8010   SI tmp_tmpopd;
8011   SI tmp_tmpops;
8012   BI tmp_carry;
8013   SI tmp_newval;
8014   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
8015   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8016   tmp_carry = CPU (h_cbit);
8017   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8018   {
8019     SI opval = tmp_newval;
8020     SET_H_GR (FLD (f_operand2), opval);
8021     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8022   }
8023 {
8024   {
8025     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8026     CPU (h_cbit) = opval;
8027     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8028   }
8029   {
8030     BI opval = LTSI (tmp_newval, 0);
8031     CPU (h_nbit) = opval;
8032     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8033   }
8034   {
8035     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8036     CPU (h_zbit) = opval;
8037     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8038   }
8039   {
8040     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8041     CPU (h_vbit) = opval;
8042     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8043   }
8044 {
8045   {
8046     BI opval = 0;
8047     CPU (h_xbit) = opval;
8048     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8049   }
8050   {
8051     BI opval = 0;
8052     SET_H_INSN_PREFIXED_P (opval);
8053     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8054   }
8055 }
8056 }
8057 }
8058
8059 #undef FLD
8060 }
8061   NEXT (vpc);
8062
8063   CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
8064 {
8065   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8066   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8067 #define FLD(f) abuf->fields.sfmt_addc_m.f
8068   int UNUSED written = 0;
8069   IADDR UNUSED pc = abuf->addr;
8070   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8071
8072 {
8073   SI tmp_tmpopd;
8074   SI tmp_tmpops;
8075   BI tmp_carry;
8076   SI tmp_newval;
8077   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
8078   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8079   tmp_carry = CPU (h_cbit);
8080   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8081   {
8082     SI opval = tmp_newval;
8083     SET_H_GR (FLD (f_operand2), opval);
8084     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8085   }
8086 {
8087   {
8088     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8089     CPU (h_cbit) = opval;
8090     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8091   }
8092   {
8093     BI opval = LTSI (tmp_newval, 0);
8094     CPU (h_nbit) = opval;
8095     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8096   }
8097   {
8098     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8099     CPU (h_zbit) = opval;
8100     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8101   }
8102   {
8103     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8104     CPU (h_vbit) = opval;
8105     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8106   }
8107 {
8108   {
8109     BI opval = 0;
8110     CPU (h_xbit) = opval;
8111     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8112   }
8113   {
8114     BI opval = 0;
8115     SET_H_INSN_PREFIXED_P (opval);
8116     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8117   }
8118 }
8119 }
8120 }
8121
8122 #undef FLD
8123 }
8124   NEXT (vpc);
8125
8126   CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
8127 {
8128   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8129   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8130 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8131   int UNUSED written = 0;
8132   IADDR UNUSED pc = abuf->addr;
8133   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8134
8135 {
8136   SI tmp_tmpopd;
8137   SI tmp_tmpops;
8138   BI tmp_carry;
8139   SI tmp_newval;
8140   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
8141   QI tmp_tmp_mem;
8142   BI tmp_postinc;
8143   tmp_postinc = FLD (f_memmode);
8144 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8145 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8146 ; if (NEBI (tmp_postinc, 0)) {
8147 {
8148 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8149   tmp_addr = ADDSI (tmp_addr, 1);
8150 }
8151   {
8152     SI opval = tmp_addr;
8153     SET_H_GR (FLD (f_operand1), opval);
8154     written |= (1 << 11);
8155     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8156   }
8157 }
8158 }
8159 ; tmp_tmp_mem; }));
8160   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8161   tmp_carry = CPU (h_cbit);
8162   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8163   {
8164     SI opval = tmp_newval;
8165     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8166     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8167   }
8168 {
8169   {
8170     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8171     CPU (h_cbit) = opval;
8172     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8173   }
8174   {
8175     BI opval = LTSI (tmp_newval, 0);
8176     CPU (h_nbit) = opval;
8177     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8178   }
8179   {
8180     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8181     CPU (h_zbit) = opval;
8182     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8183   }
8184   {
8185     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8186     CPU (h_vbit) = opval;
8187     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8188   }
8189 {
8190   {
8191     BI opval = 0;
8192     CPU (h_xbit) = opval;
8193     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8194   }
8195   {
8196     BI opval = 0;
8197     SET_H_INSN_PREFIXED_P (opval);
8198     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8199   }
8200 }
8201 }
8202 }
8203
8204   abuf->written = written;
8205 #undef FLD
8206 }
8207   NEXT (vpc);
8208
8209   CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
8210 {
8211   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8212   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8213 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8214   int UNUSED written = 0;
8215   IADDR UNUSED pc = abuf->addr;
8216   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8217
8218 {
8219   SI tmp_tmpopd;
8220   SI tmp_tmpops;
8221   BI tmp_carry;
8222   SI tmp_newval;
8223   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
8224   HI tmp_tmp_mem;
8225   BI tmp_postinc;
8226   tmp_postinc = FLD (f_memmode);
8227 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8228 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8229 ; if (NEBI (tmp_postinc, 0)) {
8230 {
8231 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8232   tmp_addr = ADDSI (tmp_addr, 2);
8233 }
8234   {
8235     SI opval = tmp_addr;
8236     SET_H_GR (FLD (f_operand1), opval);
8237     written |= (1 << 11);
8238     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8239   }
8240 }
8241 }
8242 ; tmp_tmp_mem; }));
8243   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8244   tmp_carry = CPU (h_cbit);
8245   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8246   {
8247     SI opval = tmp_newval;
8248     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8249     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8250   }
8251 {
8252   {
8253     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8254     CPU (h_cbit) = opval;
8255     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8256   }
8257   {
8258     BI opval = LTSI (tmp_newval, 0);
8259     CPU (h_nbit) = opval;
8260     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8261   }
8262   {
8263     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8264     CPU (h_zbit) = opval;
8265     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8266   }
8267   {
8268     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8269     CPU (h_vbit) = opval;
8270     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8271   }
8272 {
8273   {
8274     BI opval = 0;
8275     CPU (h_xbit) = opval;
8276     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8277   }
8278   {
8279     BI opval = 0;
8280     SET_H_INSN_PREFIXED_P (opval);
8281     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8282   }
8283 }
8284 }
8285 }
8286
8287   abuf->written = written;
8288 #undef FLD
8289 }
8290   NEXT (vpc);
8291
8292   CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
8293 {
8294   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8295   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8296 #define FLD(f) abuf->fields.sfmt_addcbr.f
8297   int UNUSED written = 0;
8298   IADDR UNUSED pc = abuf->addr;
8299   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8300
8301 {
8302   SI tmp_tmpopd;
8303   SI tmp_tmpops;
8304   BI tmp_carry;
8305   SI tmp_newval;
8306   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
8307   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8308   tmp_carry = CPU (h_cbit);
8309   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8310   {
8311     SI opval = tmp_newval;
8312     SET_H_GR (FLD (f_operand2), opval);
8313     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8314   }
8315 {
8316   {
8317     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8318     CPU (h_cbit) = opval;
8319     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8320   }
8321   {
8322     BI opval = LTSI (tmp_newval, 0);
8323     CPU (h_nbit) = opval;
8324     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8325   }
8326   {
8327     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8328     CPU (h_zbit) = opval;
8329     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8330   }
8331   {
8332     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8333     CPU (h_vbit) = opval;
8334     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8335   }
8336 {
8337   {
8338     BI opval = 0;
8339     CPU (h_xbit) = opval;
8340     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8341   }
8342   {
8343     BI opval = 0;
8344     SET_H_INSN_PREFIXED_P (opval);
8345     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8346   }
8347 }
8348 }
8349 }
8350
8351 #undef FLD
8352 }
8353   NEXT (vpc);
8354
8355   CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
8356 {
8357   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8358   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8359 #define FLD(f) abuf->fields.sfmt_addcwr.f
8360   int UNUSED written = 0;
8361   IADDR UNUSED pc = abuf->addr;
8362   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8363
8364 {
8365   SI tmp_tmpopd;
8366   SI tmp_tmpops;
8367   BI tmp_carry;
8368   SI tmp_newval;
8369   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
8370   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8371   tmp_carry = CPU (h_cbit);
8372   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8373   {
8374     SI opval = tmp_newval;
8375     SET_H_GR (FLD (f_operand2), opval);
8376     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8377   }
8378 {
8379   {
8380     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8381     CPU (h_cbit) = opval;
8382     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8383   }
8384   {
8385     BI opval = LTSI (tmp_newval, 0);
8386     CPU (h_nbit) = opval;
8387     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8388   }
8389   {
8390     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8391     CPU (h_zbit) = opval;
8392     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8393   }
8394   {
8395     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8396     CPU (h_vbit) = opval;
8397     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8398   }
8399 {
8400   {
8401     BI opval = 0;
8402     CPU (h_xbit) = opval;
8403     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8404   }
8405   {
8406     BI opval = 0;
8407     SET_H_INSN_PREFIXED_P (opval);
8408     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8409   }
8410 }
8411 }
8412 }
8413
8414 #undef FLD
8415 }
8416   NEXT (vpc);
8417
8418   CASE (sem, INSN_ADDC_R) : /* addc $Rs,$Rd */
8419 {
8420   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8421   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8422 #define FLD(f) abuf->fields.sfmt_addc_m.f
8423   int UNUSED written = 0;
8424   IADDR UNUSED pc = abuf->addr;
8425   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8426
8427 {
8428 CPU (h_xbit) = 1;
8429 {
8430   SI tmp_tmpopd;
8431   SI tmp_tmpops;
8432   BI tmp_carry;
8433   SI tmp_newval;
8434   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8435   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8436   tmp_carry = CPU (h_cbit);
8437   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8438   {
8439     SI opval = tmp_newval;
8440     SET_H_GR (FLD (f_operand2), opval);
8441     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8442   }
8443 {
8444   {
8445     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8446     CPU (h_cbit) = opval;
8447     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8448   }
8449   {
8450     BI opval = LTSI (tmp_newval, 0);
8451     CPU (h_nbit) = opval;
8452     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8453   }
8454   {
8455     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8456     CPU (h_zbit) = opval;
8457     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8458   }
8459   {
8460     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8461     CPU (h_vbit) = opval;
8462     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8463   }
8464 {
8465   {
8466     BI opval = 0;
8467     CPU (h_xbit) = opval;
8468     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8469   }
8470   {
8471     BI opval = 0;
8472     SET_H_INSN_PREFIXED_P (opval);
8473     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8474   }
8475 }
8476 }
8477 }
8478 }
8479
8480 #undef FLD
8481 }
8482   NEXT (vpc);
8483
8484   CASE (sem, INSN_ADDC_M) : /* addc [${Rs}${inc}],${Rd} */
8485 {
8486   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8487   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8488 #define FLD(f) abuf->fields.sfmt_addc_m.f
8489   int UNUSED written = 0;
8490   IADDR UNUSED pc = abuf->addr;
8491   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8492
8493 {
8494 CPU (h_xbit) = 1;
8495 {
8496   SI tmp_tmpopd;
8497   SI tmp_tmpops;
8498   BI tmp_carry;
8499   SI tmp_newval;
8500   tmp_tmpops = ({   SI tmp_addr;
8501   SI tmp_tmp_mem;
8502   BI tmp_postinc;
8503   tmp_postinc = FLD (f_memmode);
8504 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8505 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
8506 ; if (NEBI (tmp_postinc, 0)) {
8507 {
8508 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8509   tmp_addr = ADDSI (tmp_addr, 4);
8510 }
8511   {
8512     SI opval = tmp_addr;
8513     SET_H_GR (FLD (f_operand1), opval);
8514     written |= (1 << 10);
8515     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8516   }
8517 }
8518 }
8519 ; tmp_tmp_mem; });
8520   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8521   tmp_carry = CPU (h_cbit);
8522   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8523   {
8524     SI opval = tmp_newval;
8525     SET_H_GR (FLD (f_operand2), opval);
8526     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8527   }
8528 {
8529   {
8530     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8531     CPU (h_cbit) = opval;
8532     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8533   }
8534   {
8535     BI opval = LTSI (tmp_newval, 0);
8536     CPU (h_nbit) = opval;
8537     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8538   }
8539   {
8540     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8541     CPU (h_zbit) = opval;
8542     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8543   }
8544   {
8545     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8546     CPU (h_vbit) = opval;
8547     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8548   }
8549 {
8550   {
8551     BI opval = 0;
8552     CPU (h_xbit) = opval;
8553     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8554   }
8555   {
8556     BI opval = 0;
8557     SET_H_INSN_PREFIXED_P (opval);
8558     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8559   }
8560 }
8561 }
8562 }
8563 }
8564
8565   abuf->written = written;
8566 #undef FLD
8567 }
8568   NEXT (vpc);
8569
8570   CASE (sem, INSN_ADDC_C) : /* addc ${const32},${Rd} */
8571 {
8572   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8573   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8574 #define FLD(f) abuf->fields.sfmt_addcdr.f
8575   int UNUSED written = 0;
8576   IADDR UNUSED pc = abuf->addr;
8577   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
8578
8579 {
8580 CPU (h_xbit) = 1;
8581 {
8582   SI tmp_tmpopd;
8583   SI tmp_tmpops;
8584   BI tmp_carry;
8585   SI tmp_newval;
8586   tmp_tmpops = FLD (f_indir_pc__dword);
8587   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8588   tmp_carry = CPU (h_cbit);
8589   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8590   {
8591     SI opval = tmp_newval;
8592     SET_H_GR (FLD (f_operand2), opval);
8593     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8594   }
8595 {
8596   {
8597     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8598     CPU (h_cbit) = opval;
8599     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8600   }
8601   {
8602     BI opval = LTSI (tmp_newval, 0);
8603     CPU (h_nbit) = opval;
8604     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8605   }
8606   {
8607     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8608     CPU (h_zbit) = opval;
8609     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8610   }
8611   {
8612     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8613     CPU (h_vbit) = opval;
8614     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8615   }
8616 {
8617   {
8618     BI opval = 0;
8619     CPU (h_xbit) = opval;
8620     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8621   }
8622   {
8623     BI opval = 0;
8624     SET_H_INSN_PREFIXED_P (opval);
8625     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8626   }
8627 }
8628 }
8629 }
8630 }
8631
8632 #undef FLD
8633 }
8634   NEXT (vpc);
8635
8636   CASE (sem, INSN_LAPC_D) : /* lapc.d ${const32-pcrel},${Rd} */
8637 {
8638   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8639   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8640 #define FLD(f) abuf->fields.sfmt_lapc_d.f
8641   int UNUSED written = 0;
8642   IADDR UNUSED pc = abuf->addr;
8643   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
8644
8645 {
8646   {
8647     SI opval = FLD (i_const32_pcrel);
8648     SET_H_GR (FLD (f_operand2), opval);
8649     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8650   }
8651 {
8652   {
8653     BI opval = 0;
8654     CPU (h_xbit) = opval;
8655     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8656   }
8657   {
8658     BI opval = 0;
8659     SET_H_INSN_PREFIXED_P (opval);
8660     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8661   }
8662 }
8663 }
8664
8665 #undef FLD
8666 }
8667   NEXT (vpc);
8668
8669   CASE (sem, INSN_LAPCQ) : /* lapcq ${qo},${Rd} */
8670 {
8671   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8672   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8673 #define FLD(f) abuf->fields.sfmt_lapcq.f
8674   int UNUSED written = 0;
8675   IADDR UNUSED pc = abuf->addr;
8676   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8677
8678 {
8679   {
8680     SI opval = FLD (i_qo);
8681     SET_H_GR (FLD (f_operand2), opval);
8682     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8683   }
8684 {
8685   {
8686     BI opval = 0;
8687     CPU (h_xbit) = opval;
8688     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8689   }
8690   {
8691     BI opval = 0;
8692     SET_H_INSN_PREFIXED_P (opval);
8693     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8694   }
8695 }
8696 }
8697
8698 #undef FLD
8699 }
8700   NEXT (vpc);
8701
8702   CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
8703 {
8704   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8705   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8706 #define FLD(f) abuf->fields.sfmt_addc_m.f
8707   int UNUSED written = 0;
8708   IADDR UNUSED pc = abuf->addr;
8709   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8710
8711 {
8712   {
8713     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
8714     SET_H_GR (FLD (f_operand1), opval);
8715     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8716   }
8717 {
8718   {
8719     BI opval = 0;
8720     CPU (h_xbit) = opval;
8721     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8722   }
8723   {
8724     BI opval = 0;
8725     SET_H_INSN_PREFIXED_P (opval);
8726     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8727   }
8728 }
8729 }
8730
8731 #undef FLD
8732 }
8733   NEXT (vpc);
8734
8735   CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
8736 {
8737   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8738   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8739 #define FLD(f) abuf->fields.sfmt_addc_m.f
8740   int UNUSED written = 0;
8741   IADDR UNUSED pc = abuf->addr;
8742   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8743
8744 {
8745   {
8746     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
8747     SET_H_GR (FLD (f_operand1), opval);
8748     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8749   }
8750 {
8751   {
8752     BI opval = 0;
8753     CPU (h_xbit) = opval;
8754     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8755   }
8756   {
8757     BI opval = 0;
8758     SET_H_INSN_PREFIXED_P (opval);
8759     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8760   }
8761 }
8762 }
8763
8764 #undef FLD
8765 }
8766   NEXT (vpc);
8767
8768   CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
8769 {
8770   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8771   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8772 #define FLD(f) abuf->fields.sfmt_addc_m.f
8773   int UNUSED written = 0;
8774   IADDR UNUSED pc = abuf->addr;
8775   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8776
8777 {
8778   {
8779     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
8780     SET_H_GR (FLD (f_operand1), opval);
8781     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8782   }
8783 {
8784   {
8785     BI opval = 0;
8786     CPU (h_xbit) = opval;
8787     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8788   }
8789   {
8790     BI opval = 0;
8791     SET_H_INSN_PREFIXED_P (opval);
8792     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8793   }
8794 }
8795 }
8796
8797 #undef FLD
8798 }
8799   NEXT (vpc);
8800
8801   CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
8802 {
8803   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8804   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8805 #define FLD(f) abuf->fields.sfmt_addc_m.f
8806   int UNUSED written = 0;
8807   IADDR UNUSED pc = abuf->addr;
8808   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8809
8810 {
8811   QI tmp_tmpopd;
8812   QI tmp_tmpops;
8813   BI tmp_carry;
8814   QI tmp_newval;
8815   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8816   tmp_tmpopd = 0;
8817   tmp_carry = CPU (h_cbit);
8818   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8819 {
8820   SI tmp_oldregval;
8821   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
8822   {
8823     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
8824     SET_H_GR (FLD (f_operand2), opval);
8825     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8826   }
8827 }
8828 {
8829   {
8830     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
8831     CPU (h_cbit) = opval;
8832     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8833   }
8834   {
8835     BI opval = LTQI (tmp_newval, 0);
8836     CPU (h_nbit) = opval;
8837     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8838   }
8839   {
8840     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8841     CPU (h_zbit) = opval;
8842     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8843   }
8844   {
8845     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
8846     CPU (h_vbit) = opval;
8847     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8848   }
8849 {
8850   {
8851     BI opval = 0;
8852     CPU (h_xbit) = opval;
8853     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8854   }
8855   {
8856     BI opval = 0;
8857     SET_H_INSN_PREFIXED_P (opval);
8858     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8859   }
8860 }
8861 }
8862 }
8863
8864 #undef FLD
8865 }
8866   NEXT (vpc);
8867
8868   CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
8869 {
8870   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8871   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8872 #define FLD(f) abuf->fields.sfmt_addc_m.f
8873   int UNUSED written = 0;
8874   IADDR UNUSED pc = abuf->addr;
8875   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8876
8877 {
8878   HI tmp_tmpopd;
8879   HI tmp_tmpops;
8880   BI tmp_carry;
8881   HI tmp_newval;
8882   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8883   tmp_tmpopd = 0;
8884   tmp_carry = CPU (h_cbit);
8885   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8886 {
8887   SI tmp_oldregval;
8888   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
8889   {
8890     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
8891     SET_H_GR (FLD (f_operand2), opval);
8892     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8893   }
8894 }
8895 {
8896   {
8897     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
8898     CPU (h_cbit) = opval;
8899     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8900   }
8901   {
8902     BI opval = LTHI (tmp_newval, 0);
8903     CPU (h_nbit) = opval;
8904     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8905   }
8906   {
8907     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8908     CPU (h_zbit) = opval;
8909     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8910   }
8911   {
8912     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
8913     CPU (h_vbit) = opval;
8914     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8915   }
8916 {
8917   {
8918     BI opval = 0;
8919     CPU (h_xbit) = opval;
8920     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8921   }
8922   {
8923     BI opval = 0;
8924     SET_H_INSN_PREFIXED_P (opval);
8925     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8926   }
8927 }
8928 }
8929 }
8930
8931 #undef FLD
8932 }
8933   NEXT (vpc);
8934
8935   CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
8936 {
8937   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8938   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8939 #define FLD(f) abuf->fields.sfmt_addc_m.f
8940   int UNUSED written = 0;
8941   IADDR UNUSED pc = abuf->addr;
8942   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8943
8944 {
8945   SI tmp_tmpopd;
8946   SI tmp_tmpops;
8947   BI tmp_carry;
8948   SI tmp_newval;
8949   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8950   tmp_tmpopd = 0;
8951   tmp_carry = CPU (h_cbit);
8952   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8953   {
8954     SI opval = tmp_newval;
8955     SET_H_GR (FLD (f_operand2), opval);
8956     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8957   }
8958 {
8959   {
8960     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8961     CPU (h_cbit) = opval;
8962     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8963   }
8964   {
8965     BI opval = LTSI (tmp_newval, 0);
8966     CPU (h_nbit) = opval;
8967     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8968   }
8969   {
8970     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8971     CPU (h_zbit) = opval;
8972     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8973   }
8974   {
8975     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8976     CPU (h_vbit) = opval;
8977     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8978   }
8979 {
8980   {
8981     BI opval = 0;
8982     CPU (h_xbit) = opval;
8983     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8984   }
8985   {
8986     BI opval = 0;
8987     SET_H_INSN_PREFIXED_P (opval);
8988     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8989   }
8990 }
8991 }
8992 }
8993
8994 #undef FLD
8995 }
8996   NEXT (vpc);
8997
8998   CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
8999 {
9000   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9001   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9002 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9003   int UNUSED written = 0;
9004   IADDR UNUSED pc = abuf->addr;
9005   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9006
9007 {
9008   QI tmp_tmpd;
9009   tmp_tmpd = ({   SI tmp_addr;
9010   QI tmp_tmp_mem;
9011   BI tmp_postinc;
9012   tmp_postinc = FLD (f_memmode);
9013 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9014 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
9015 ; if (NEBI (tmp_postinc, 0)) {
9016 {
9017 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9018   tmp_addr = ADDSI (tmp_addr, 1);
9019 }
9020   {
9021     SI opval = tmp_addr;
9022     SET_H_GR (FLD (f_operand1), opval);
9023     written |= (1 << 8);
9024     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9025   }
9026 }
9027 }
9028 ; tmp_tmp_mem; });
9029 {
9030   QI tmp_tmpopd;
9031   QI tmp_tmpops;
9032   BI tmp_carry;
9033   QI tmp_newval;
9034   tmp_tmpops = 0;
9035   tmp_tmpopd = tmp_tmpd;
9036   tmp_carry = CPU (h_cbit);
9037   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9038 ((void) 0); /*nop*/
9039 {
9040   {
9041     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
9042     CPU (h_cbit) = opval;
9043     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9044   }
9045   {
9046     BI opval = LTQI (tmp_newval, 0);
9047     CPU (h_nbit) = opval;
9048     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9049   }
9050   {
9051     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9052     CPU (h_zbit) = opval;
9053     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9054   }
9055   {
9056     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
9057     CPU (h_vbit) = opval;
9058     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9059   }
9060 {
9061   {
9062     BI opval = 0;
9063     CPU (h_xbit) = opval;
9064     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9065   }
9066   {
9067     BI opval = 0;
9068     SET_H_INSN_PREFIXED_P (opval);
9069     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9070   }
9071 }
9072 }
9073 }
9074 }
9075
9076   abuf->written = written;
9077 #undef FLD
9078 }
9079   NEXT (vpc);
9080
9081   CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
9082 {
9083   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9084   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9085 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9086   int UNUSED written = 0;
9087   IADDR UNUSED pc = abuf->addr;
9088   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9089
9090 {
9091   HI tmp_tmpd;
9092   tmp_tmpd = ({   SI tmp_addr;
9093   HI tmp_tmp_mem;
9094   BI tmp_postinc;
9095   tmp_postinc = FLD (f_memmode);
9096 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9097 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
9098 ; if (NEBI (tmp_postinc, 0)) {
9099 {
9100 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9101   tmp_addr = ADDSI (tmp_addr, 2);
9102 }
9103   {
9104     SI opval = tmp_addr;
9105     SET_H_GR (FLD (f_operand1), opval);
9106     written |= (1 << 8);
9107     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9108   }
9109 }
9110 }
9111 ; tmp_tmp_mem; });
9112 {
9113   HI tmp_tmpopd;
9114   HI tmp_tmpops;
9115   BI tmp_carry;
9116   HI tmp_newval;
9117   tmp_tmpops = 0;
9118   tmp_tmpopd = tmp_tmpd;
9119   tmp_carry = CPU (h_cbit);
9120   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9121 ((void) 0); /*nop*/
9122 {
9123   {
9124     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
9125     CPU (h_cbit) = opval;
9126     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9127   }
9128   {
9129     BI opval = LTHI (tmp_newval, 0);
9130     CPU (h_nbit) = opval;
9131     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9132   }
9133   {
9134     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9135     CPU (h_zbit) = opval;
9136     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9137   }
9138   {
9139     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
9140     CPU (h_vbit) = opval;
9141     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9142   }
9143 {
9144   {
9145     BI opval = 0;
9146     CPU (h_xbit) = opval;
9147     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9148   }
9149   {
9150     BI opval = 0;
9151     SET_H_INSN_PREFIXED_P (opval);
9152     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9153   }
9154 }
9155 }
9156 }
9157 }
9158
9159   abuf->written = written;
9160 #undef FLD
9161 }
9162   NEXT (vpc);
9163
9164   CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
9165 {
9166   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9167   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9168 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9169   int UNUSED written = 0;
9170   IADDR UNUSED pc = abuf->addr;
9171   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9172
9173 {
9174   SI tmp_tmpd;
9175   tmp_tmpd = ({   SI tmp_addr;
9176   SI tmp_tmp_mem;
9177   BI tmp_postinc;
9178   tmp_postinc = FLD (f_memmode);
9179 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9180 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
9181 ; if (NEBI (tmp_postinc, 0)) {
9182 {
9183 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9184   tmp_addr = ADDSI (tmp_addr, 4);
9185 }
9186   {
9187     SI opval = tmp_addr;
9188     SET_H_GR (FLD (f_operand1), opval);
9189     written |= (1 << 8);
9190     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9191   }
9192 }
9193 }
9194 ; tmp_tmp_mem; });
9195 {
9196   SI tmp_tmpopd;
9197   SI tmp_tmpops;
9198   BI tmp_carry;
9199   SI tmp_newval;
9200   tmp_tmpops = 0;
9201   tmp_tmpopd = tmp_tmpd;
9202   tmp_carry = CPU (h_cbit);
9203   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9204 ((void) 0); /*nop*/
9205 {
9206   {
9207     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
9208     CPU (h_cbit) = opval;
9209     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9210   }
9211   {
9212     BI opval = LTSI (tmp_newval, 0);
9213     CPU (h_nbit) = opval;
9214     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9215   }
9216   {
9217     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9218     CPU (h_zbit) = opval;
9219     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9220   }
9221   {
9222     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
9223     CPU (h_vbit) = opval;
9224     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9225   }
9226 {
9227   {
9228     BI opval = 0;
9229     CPU (h_xbit) = opval;
9230     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9231   }
9232   {
9233     BI opval = 0;
9234     SET_H_INSN_PREFIXED_P (opval);
9235     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9236   }
9237 }
9238 }
9239 }
9240 }
9241
9242   abuf->written = written;
9243 #undef FLD
9244 }
9245   NEXT (vpc);
9246
9247   CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
9248 {
9249   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9250   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9251 #define FLD(f) abuf->fields.sfmt_addc_m.f
9252   int UNUSED written = 0;
9253   IADDR UNUSED pc = abuf->addr;
9254   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9255
9256 {
9257   QI tmp_tmpd;
9258   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9259 {
9260   SI tmp_addr;
9261   BI tmp_postinc;
9262   tmp_postinc = FLD (f_memmode);
9263   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9264 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9265 if (EQBI (CPU (h_pbit), 0)) {
9266 {
9267   {
9268     QI opval = tmp_tmpd;
9269     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9270     written |= (1 << 10);
9271     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9272   }
9273   {
9274     BI opval = CPU (h_pbit);
9275     CPU (h_cbit) = opval;
9276     written |= (1 << 9);
9277     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9278   }
9279 }
9280 } else {
9281   {
9282     BI opval = 1;
9283     CPU (h_cbit) = opval;
9284     written |= (1 << 9);
9285     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9286   }
9287 }
9288 } else {
9289   {
9290     QI opval = tmp_tmpd;
9291     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9292     written |= (1 << 10);
9293     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9294   }
9295 }
9296 if (NEBI (tmp_postinc, 0)) {
9297 {
9298 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9299   tmp_addr = ADDSI (tmp_addr, 1);
9300 }
9301   {
9302     SI opval = tmp_addr;
9303     SET_H_GR (FLD (f_operand1), opval);
9304     written |= (1 << 8);
9305     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9306   }
9307 }
9308 }
9309 }
9310 {
9311   {
9312     BI opval = 0;
9313     CPU (h_xbit) = opval;
9314     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9315   }
9316   {
9317     BI opval = 0;
9318     SET_H_INSN_PREFIXED_P (opval);
9319     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9320   }
9321 }
9322 }
9323
9324   abuf->written = written;
9325 #undef FLD
9326 }
9327   NEXT (vpc);
9328
9329   CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
9330 {
9331   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9332   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9333 #define FLD(f) abuf->fields.sfmt_addc_m.f
9334   int UNUSED written = 0;
9335   IADDR UNUSED pc = abuf->addr;
9336   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9337
9338 {
9339   HI tmp_tmpd;
9340   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9341 {
9342   SI tmp_addr;
9343   BI tmp_postinc;
9344   tmp_postinc = FLD (f_memmode);
9345   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9346 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9347 if (EQBI (CPU (h_pbit), 0)) {
9348 {
9349   {
9350     HI opval = tmp_tmpd;
9351     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9352     written |= (1 << 10);
9353     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9354   }
9355   {
9356     BI opval = CPU (h_pbit);
9357     CPU (h_cbit) = opval;
9358     written |= (1 << 9);
9359     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9360   }
9361 }
9362 } else {
9363   {
9364     BI opval = 1;
9365     CPU (h_cbit) = opval;
9366     written |= (1 << 9);
9367     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9368   }
9369 }
9370 } else {
9371   {
9372     HI opval = tmp_tmpd;
9373     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9374     written |= (1 << 10);
9375     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9376   }
9377 }
9378 if (NEBI (tmp_postinc, 0)) {
9379 {
9380 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9381   tmp_addr = ADDSI (tmp_addr, 2);
9382 }
9383   {
9384     SI opval = tmp_addr;
9385     SET_H_GR (FLD (f_operand1), opval);
9386     written |= (1 << 8);
9387     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9388   }
9389 }
9390 }
9391 }
9392 {
9393   {
9394     BI opval = 0;
9395     CPU (h_xbit) = opval;
9396     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9397   }
9398   {
9399     BI opval = 0;
9400     SET_H_INSN_PREFIXED_P (opval);
9401     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9402   }
9403 }
9404 }
9405
9406   abuf->written = written;
9407 #undef FLD
9408 }
9409   NEXT (vpc);
9410
9411   CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
9412 {
9413   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9414   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9415 #define FLD(f) abuf->fields.sfmt_addc_m.f
9416   int UNUSED written = 0;
9417   IADDR UNUSED pc = abuf->addr;
9418   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9419
9420 {
9421   SI tmp_tmpd;
9422   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9423 {
9424   SI tmp_addr;
9425   BI tmp_postinc;
9426   tmp_postinc = FLD (f_memmode);
9427   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9428 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9429 if (EQBI (CPU (h_pbit), 0)) {
9430 {
9431   {
9432     SI opval = tmp_tmpd;
9433     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9434     written |= (1 << 10);
9435     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9436   }
9437   {
9438     BI opval = CPU (h_pbit);
9439     CPU (h_cbit) = opval;
9440     written |= (1 << 9);
9441     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9442   }
9443 }
9444 } else {
9445   {
9446     BI opval = 1;
9447     CPU (h_cbit) = opval;
9448     written |= (1 << 9);
9449     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9450   }
9451 }
9452 } else {
9453   {
9454     SI opval = tmp_tmpd;
9455     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9456     written |= (1 << 10);
9457     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9458   }
9459 }
9460 if (NEBI (tmp_postinc, 0)) {
9461 {
9462 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9463   tmp_addr = ADDSI (tmp_addr, 4);
9464 }
9465   {
9466     SI opval = tmp_addr;
9467     SET_H_GR (FLD (f_operand1), opval);
9468     written |= (1 << 8);
9469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9470   }
9471 }
9472 }
9473 }
9474 {
9475   {
9476     BI opval = 0;
9477     CPU (h_xbit) = opval;
9478     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9479   }
9480   {
9481     BI opval = 0;
9482     SET_H_INSN_PREFIXED_P (opval);
9483     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9484   }
9485 }
9486 }
9487
9488   abuf->written = written;
9489 #undef FLD
9490 }
9491   NEXT (vpc);
9492
9493   CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
9494 {
9495   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9496   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9497 #define FLD(f) abuf->fields.sfmt_muls_b.f
9498   int UNUSED written = 0;
9499   IADDR UNUSED pc = abuf->addr;
9500   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9501
9502 {
9503   DI tmp_src1;
9504   DI tmp_src2;
9505   DI tmp_tmpr;
9506   tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9507   tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9508   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9509   {
9510     SI opval = TRUNCDISI (tmp_tmpr);
9511     SET_H_GR (FLD (f_operand2), opval);
9512     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9513   }
9514   {
9515     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9516     SET_H_SR (((UINT) 7), opval);
9517     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9518   }
9519 {
9520   {
9521     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9522     CPU (h_cbit) = opval;
9523     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9524   }
9525   {
9526     BI opval = LTDI (tmp_tmpr, 0);
9527     CPU (h_nbit) = opval;
9528     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9529   }
9530   {
9531     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9532     CPU (h_zbit) = opval;
9533     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9534   }
9535   {
9536     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9537     CPU (h_vbit) = opval;
9538     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9539   }
9540 {
9541   {
9542     BI opval = 0;
9543     CPU (h_xbit) = opval;
9544     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9545   }
9546   {
9547     BI opval = 0;
9548     SET_H_INSN_PREFIXED_P (opval);
9549     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9550   }
9551 }
9552 }
9553 }
9554
9555 #undef FLD
9556 }
9557   NEXT (vpc);
9558
9559   CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
9560 {
9561   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9562   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9563 #define FLD(f) abuf->fields.sfmt_muls_b.f
9564   int UNUSED written = 0;
9565   IADDR UNUSED pc = abuf->addr;
9566   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9567
9568 {
9569   DI tmp_src1;
9570   DI tmp_src2;
9571   DI tmp_tmpr;
9572   tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9573   tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9574   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9575   {
9576     SI opval = TRUNCDISI (tmp_tmpr);
9577     SET_H_GR (FLD (f_operand2), opval);
9578     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9579   }
9580   {
9581     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9582     SET_H_SR (((UINT) 7), opval);
9583     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9584   }
9585 {
9586   {
9587     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9588     CPU (h_cbit) = opval;
9589     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9590   }
9591   {
9592     BI opval = LTDI (tmp_tmpr, 0);
9593     CPU (h_nbit) = opval;
9594     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9595   }
9596   {
9597     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9598     CPU (h_zbit) = opval;
9599     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9600   }
9601   {
9602     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9603     CPU (h_vbit) = opval;
9604     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9605   }
9606 {
9607   {
9608     BI opval = 0;
9609     CPU (h_xbit) = opval;
9610     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9611   }
9612   {
9613     BI opval = 0;
9614     SET_H_INSN_PREFIXED_P (opval);
9615     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9616   }
9617 }
9618 }
9619 }
9620
9621 #undef FLD
9622 }
9623   NEXT (vpc);
9624
9625   CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
9626 {
9627   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9628   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9629 #define FLD(f) abuf->fields.sfmt_muls_b.f
9630   int UNUSED written = 0;
9631   IADDR UNUSED pc = abuf->addr;
9632   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9633
9634 {
9635   DI tmp_src1;
9636   DI tmp_src2;
9637   DI tmp_tmpr;
9638   tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9639   tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9640   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9641   {
9642     SI opval = TRUNCDISI (tmp_tmpr);
9643     SET_H_GR (FLD (f_operand2), opval);
9644     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9645   }
9646   {
9647     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9648     SET_H_SR (((UINT) 7), opval);
9649     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9650   }
9651 {
9652   {
9653     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9654     CPU (h_cbit) = opval;
9655     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9656   }
9657   {
9658     BI opval = LTDI (tmp_tmpr, 0);
9659     CPU (h_nbit) = opval;
9660     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9661   }
9662   {
9663     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9664     CPU (h_zbit) = opval;
9665     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9666   }
9667   {
9668     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9669     CPU (h_vbit) = opval;
9670     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9671   }
9672 {
9673   {
9674     BI opval = 0;
9675     CPU (h_xbit) = opval;
9676     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9677   }
9678   {
9679     BI opval = 0;
9680     SET_H_INSN_PREFIXED_P (opval);
9681     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9682   }
9683 }
9684 }
9685 }
9686
9687 #undef FLD
9688 }
9689   NEXT (vpc);
9690
9691   CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
9692 {
9693   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9694   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9695 #define FLD(f) abuf->fields.sfmt_muls_b.f
9696   int UNUSED written = 0;
9697   IADDR UNUSED pc = abuf->addr;
9698   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9699
9700 {
9701   DI tmp_src1;
9702   DI tmp_src2;
9703   DI tmp_tmpr;
9704   tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9705   tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9706   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9707   {
9708     SI opval = TRUNCDISI (tmp_tmpr);
9709     SET_H_GR (FLD (f_operand2), opval);
9710     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9711   }
9712   {
9713     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9714     SET_H_SR (((UINT) 7), opval);
9715     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9716   }
9717 {
9718   {
9719     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9720     CPU (h_cbit) = opval;
9721     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9722   }
9723   {
9724     BI opval = LTDI (tmp_tmpr, 0);
9725     CPU (h_nbit) = opval;
9726     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9727   }
9728   {
9729     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9730     CPU (h_zbit) = opval;
9731     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9732   }
9733   {
9734     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9735     CPU (h_vbit) = opval;
9736     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9737   }
9738 {
9739   {
9740     BI opval = 0;
9741     CPU (h_xbit) = opval;
9742     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9743   }
9744   {
9745     BI opval = 0;
9746     SET_H_INSN_PREFIXED_P (opval);
9747     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9748   }
9749 }
9750 }
9751 }
9752
9753 #undef FLD
9754 }
9755   NEXT (vpc);
9756
9757   CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
9758 {
9759   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9760   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9761 #define FLD(f) abuf->fields.sfmt_muls_b.f
9762   int UNUSED written = 0;
9763   IADDR UNUSED pc = abuf->addr;
9764   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9765
9766 {
9767   DI tmp_src1;
9768   DI tmp_src2;
9769   DI tmp_tmpr;
9770   tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9771   tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9772   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9773   {
9774     SI opval = TRUNCDISI (tmp_tmpr);
9775     SET_H_GR (FLD (f_operand2), opval);
9776     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9777   }
9778   {
9779     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9780     SET_H_SR (((UINT) 7), opval);
9781     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9782   }
9783 {
9784   {
9785     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9786     CPU (h_cbit) = opval;
9787     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9788   }
9789   {
9790     BI opval = LTDI (tmp_tmpr, 0);
9791     CPU (h_nbit) = opval;
9792     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9793   }
9794   {
9795     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9796     CPU (h_zbit) = opval;
9797     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9798   }
9799   {
9800     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9801     CPU (h_vbit) = opval;
9802     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9803   }
9804 {
9805   {
9806     BI opval = 0;
9807     CPU (h_xbit) = opval;
9808     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9809   }
9810   {
9811     BI opval = 0;
9812     SET_H_INSN_PREFIXED_P (opval);
9813     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9814   }
9815 }
9816 }
9817 }
9818
9819 #undef FLD
9820 }
9821   NEXT (vpc);
9822
9823   CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
9824 {
9825   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9826   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9827 #define FLD(f) abuf->fields.sfmt_muls_b.f
9828   int UNUSED written = 0;
9829   IADDR UNUSED pc = abuf->addr;
9830   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9831
9832 {
9833   DI tmp_src1;
9834   DI tmp_src2;
9835   DI tmp_tmpr;
9836   tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9837   tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9838   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9839   {
9840     SI opval = TRUNCDISI (tmp_tmpr);
9841     SET_H_GR (FLD (f_operand2), opval);
9842     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9843   }
9844   {
9845     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9846     SET_H_SR (((UINT) 7), opval);
9847     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9848   }
9849 {
9850   {
9851     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9852     CPU (h_cbit) = opval;
9853     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9854   }
9855   {
9856     BI opval = LTDI (tmp_tmpr, 0);
9857     CPU (h_nbit) = opval;
9858     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9859   }
9860   {
9861     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9862     CPU (h_zbit) = opval;
9863     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9864   }
9865   {
9866     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9867     CPU (h_vbit) = opval;
9868     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9869   }
9870 {
9871   {
9872     BI opval = 0;
9873     CPU (h_xbit) = opval;
9874     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9875   }
9876   {
9877     BI opval = 0;
9878     SET_H_INSN_PREFIXED_P (opval);
9879     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9880   }
9881 }
9882 }
9883 }
9884
9885 #undef FLD
9886 }
9887   NEXT (vpc);
9888
9889   CASE (sem, INSN_MCP) : /* mcp $Ps,$Rd */
9890 {
9891   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9892   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9893 #define FLD(f) abuf->fields.sfmt_mcp.f
9894   int UNUSED written = 0;
9895   IADDR UNUSED pc = abuf->addr;
9896   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9897
9898 {
9899 CPU (h_xbit) = 1;
9900 CPU (h_zbit) = 1;
9901 {
9902   SI tmp_tmpopd;
9903   SI tmp_tmpops;
9904   BI tmp_carry;
9905   SI tmp_newval;
9906   tmp_tmpops = GET_H_SR (FLD (f_operand2));
9907   tmp_tmpopd = GET_H_GR (FLD (f_operand1));
9908   tmp_carry = CPU (h_rbit);
9909   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9910   {
9911     SI opval = tmp_newval;
9912     SET_H_GR (FLD (f_operand1), opval);
9913     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9914   }
9915 {
9916   {
9917     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
9918     CPU (h_rbit) = opval;
9919     TRACE_RESULT (current_cpu, abuf, "rbit", 'x', opval);
9920   }
9921   {
9922     BI opval = LTSI (tmp_newval, 0);
9923     CPU (h_nbit) = opval;
9924     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9925   }
9926   {
9927     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9928     CPU (h_zbit) = opval;
9929     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9930   }
9931   {
9932     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
9933     CPU (h_vbit) = opval;
9934     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9935   }
9936 {
9937   {
9938     BI opval = 0;
9939     CPU (h_xbit) = opval;
9940     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9941   }
9942   {
9943     BI opval = 0;
9944     SET_H_INSN_PREFIXED_P (opval);
9945     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9946   }
9947 }
9948 }
9949 }
9950 }
9951
9952 #undef FLD
9953 }
9954   NEXT (vpc);
9955
9956   CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
9957 {
9958   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9959   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9960 #define FLD(f) abuf->fields.sfmt_muls_b.f
9961   int UNUSED written = 0;
9962   IADDR UNUSED pc = abuf->addr;
9963   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9964
9965 {
9966   SI tmp_tmp;
9967   SI tmp_tmps;
9968   SI tmp_tmpd;
9969   tmp_tmps = GET_H_GR (FLD (f_operand1));
9970   tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
9971   tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
9972   {
9973     SI opval = tmp_tmpd;
9974     SET_H_GR (FLD (f_operand2), opval);
9975     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9976   }
9977 {
9978   {
9979     BI opval = LTSI (tmp_tmpd, 0);
9980     CPU (h_nbit) = opval;
9981     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9982   }
9983   {
9984     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9985     CPU (h_zbit) = opval;
9986     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9987   }
9988 SET_H_CBIT_MOVE (0);
9989 SET_H_VBIT_MOVE (0);
9990 {
9991   {
9992     BI opval = 0;
9993     CPU (h_xbit) = opval;
9994     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9995   }
9996   {
9997     BI opval = 0;
9998     SET_H_INSN_PREFIXED_P (opval);
9999     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10000   }
10001 }
10002 }
10003 }
10004
10005 #undef FLD
10006 }
10007   NEXT (vpc);
10008
10009   CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
10010 {
10011   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10012   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10013 #define FLD(f) abuf->fields.sfmt_muls_b.f
10014   int UNUSED written = 0;
10015   IADDR UNUSED pc = abuf->addr;
10016   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10017
10018 {
10019   SI tmp_tmpd;
10020   tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
10021   {
10022     SI opval = tmp_tmpd;
10023     SET_H_GR (FLD (f_operand2), opval);
10024     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10025   }
10026 {
10027   {
10028     BI opval = LTSI (tmp_tmpd, 0);
10029     CPU (h_nbit) = opval;
10030     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10031   }
10032   {
10033     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10034     CPU (h_zbit) = opval;
10035     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10036   }
10037 SET_H_CBIT_MOVE (0);
10038 SET_H_VBIT_MOVE (0);
10039 {
10040   {
10041     BI opval = 0;
10042     CPU (h_xbit) = opval;
10043     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10044   }
10045   {
10046     BI opval = 0;
10047     SET_H_INSN_PREFIXED_P (opval);
10048     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10049   }
10050 }
10051 }
10052 }
10053
10054 #undef FLD
10055 }
10056   NEXT (vpc);
10057
10058   CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
10059 {
10060   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10061   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10062 #define FLD(f) abuf->fields.sfmt_addc_m.f
10063   int UNUSED written = 0;
10064   IADDR UNUSED pc = abuf->addr;
10065   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10066
10067 {
10068   QI tmp_tmpd;
10069   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10070 {
10071   SI tmp_oldregval;
10072   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10073   {
10074     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10075     SET_H_GR (FLD (f_operand2), opval);
10076     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10077   }
10078 }
10079 {
10080   {
10081     BI opval = LTQI (tmp_tmpd, 0);
10082     CPU (h_nbit) = opval;
10083     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10084   }
10085   {
10086     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10087     CPU (h_zbit) = opval;
10088     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10089   }
10090 SET_H_CBIT_MOVE (0);
10091 SET_H_VBIT_MOVE (0);
10092 {
10093   {
10094     BI opval = 0;
10095     CPU (h_xbit) = opval;
10096     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10097   }
10098   {
10099     BI opval = 0;
10100     SET_H_INSN_PREFIXED_P (opval);
10101     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10102   }
10103 }
10104 }
10105 }
10106
10107 #undef FLD
10108 }
10109   NEXT (vpc);
10110
10111   CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
10112 {
10113   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10114   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10115 #define FLD(f) abuf->fields.sfmt_addc_m.f
10116   int UNUSED written = 0;
10117   IADDR UNUSED pc = abuf->addr;
10118   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10119
10120 {
10121   HI tmp_tmpd;
10122   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10123 {
10124   SI tmp_oldregval;
10125   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10126   {
10127     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10128     SET_H_GR (FLD (f_operand2), opval);
10129     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10130   }
10131 }
10132 {
10133   {
10134     BI opval = LTHI (tmp_tmpd, 0);
10135     CPU (h_nbit) = opval;
10136     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10137   }
10138   {
10139     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10140     CPU (h_zbit) = opval;
10141     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10142   }
10143 SET_H_CBIT_MOVE (0);
10144 SET_H_VBIT_MOVE (0);
10145 {
10146   {
10147     BI opval = 0;
10148     CPU (h_xbit) = opval;
10149     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10150   }
10151   {
10152     BI opval = 0;
10153     SET_H_INSN_PREFIXED_P (opval);
10154     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10155   }
10156 }
10157 }
10158 }
10159
10160 #undef FLD
10161 }
10162   NEXT (vpc);
10163
10164   CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
10165 {
10166   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10167   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10168 #define FLD(f) abuf->fields.sfmt_addc_m.f
10169   int UNUSED written = 0;
10170   IADDR UNUSED pc = abuf->addr;
10171   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10172
10173 {
10174   SI tmp_tmpd;
10175   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10176   {
10177     SI opval = tmp_tmpd;
10178     SET_H_GR (FLD (f_operand2), opval);
10179     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10180   }
10181 {
10182   {
10183     BI opval = LTSI (tmp_tmpd, 0);
10184     CPU (h_nbit) = opval;
10185     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10186   }
10187   {
10188     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10189     CPU (h_zbit) = opval;
10190     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10191   }
10192 SET_H_CBIT_MOVE (0);
10193 SET_H_VBIT_MOVE (0);
10194 {
10195   {
10196     BI opval = 0;
10197     CPU (h_xbit) = opval;
10198     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10199   }
10200   {
10201     BI opval = 0;
10202     SET_H_INSN_PREFIXED_P (opval);
10203     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10204   }
10205 }
10206 }
10207 }
10208
10209 #undef FLD
10210 }
10211   NEXT (vpc);
10212
10213   CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
10214 {
10215   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10216   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10217 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10218   int UNUSED written = 0;
10219   IADDR UNUSED pc = abuf->addr;
10220   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10221
10222 {
10223   QI tmp_tmpd;
10224   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10225   QI tmp_tmp_mem;
10226   BI tmp_postinc;
10227   tmp_postinc = FLD (f_memmode);
10228 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10229 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10230 ; if (NEBI (tmp_postinc, 0)) {
10231 {
10232 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10233   tmp_addr = ADDSI (tmp_addr, 1);
10234 }
10235   {
10236     SI opval = tmp_addr;
10237     SET_H_GR (FLD (f_operand1), opval);
10238     written |= (1 << 11);
10239     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10240   }
10241 }
10242 }
10243 ; tmp_tmp_mem; }));
10244 {
10245   SI tmp_oldregval;
10246   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10247   {
10248     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10249     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10250     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10251   }
10252 }
10253 {
10254   {
10255     BI opval = LTQI (tmp_tmpd, 0);
10256     CPU (h_nbit) = opval;
10257     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10258   }
10259   {
10260     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10261     CPU (h_zbit) = opval;
10262     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10263   }
10264 SET_H_CBIT_MOVE (0);
10265 SET_H_VBIT_MOVE (0);
10266 {
10267   {
10268     BI opval = 0;
10269     CPU (h_xbit) = opval;
10270     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10271   }
10272   {
10273     BI opval = 0;
10274     SET_H_INSN_PREFIXED_P (opval);
10275     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10276   }
10277 }
10278 }
10279 }
10280
10281   abuf->written = written;
10282 #undef FLD
10283 }
10284   NEXT (vpc);
10285
10286   CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
10287 {
10288   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10289   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10290 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10291   int UNUSED written = 0;
10292   IADDR UNUSED pc = abuf->addr;
10293   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10294
10295 {
10296   HI tmp_tmpd;
10297   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10298   HI tmp_tmp_mem;
10299   BI tmp_postinc;
10300   tmp_postinc = FLD (f_memmode);
10301 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10302 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10303 ; if (NEBI (tmp_postinc, 0)) {
10304 {
10305 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10306   tmp_addr = ADDSI (tmp_addr, 2);
10307 }
10308   {
10309     SI opval = tmp_addr;
10310     SET_H_GR (FLD (f_operand1), opval);
10311     written |= (1 << 11);
10312     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10313   }
10314 }
10315 }
10316 ; tmp_tmp_mem; }));
10317 {
10318   SI tmp_oldregval;
10319   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10320   {
10321     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10322     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10323     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10324   }
10325 }
10326 {
10327   {
10328     BI opval = LTHI (tmp_tmpd, 0);
10329     CPU (h_nbit) = opval;
10330     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10331   }
10332   {
10333     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10334     CPU (h_zbit) = opval;
10335     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10336   }
10337 SET_H_CBIT_MOVE (0);
10338 SET_H_VBIT_MOVE (0);
10339 {
10340   {
10341     BI opval = 0;
10342     CPU (h_xbit) = opval;
10343     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10344   }
10345   {
10346     BI opval = 0;
10347     SET_H_INSN_PREFIXED_P (opval);
10348     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10349   }
10350 }
10351 }
10352 }
10353
10354   abuf->written = written;
10355 #undef FLD
10356 }
10357   NEXT (vpc);
10358
10359   CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
10360 {
10361   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10362   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10363 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10364   int UNUSED written = 0;
10365   IADDR UNUSED pc = abuf->addr;
10366   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10367
10368 {
10369   SI tmp_tmpd;
10370   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10371   SI tmp_tmp_mem;
10372   BI tmp_postinc;
10373   tmp_postinc = FLD (f_memmode);
10374 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10375 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10376 ; if (NEBI (tmp_postinc, 0)) {
10377 {
10378 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10379   tmp_addr = ADDSI (tmp_addr, 4);
10380 }
10381   {
10382     SI opval = tmp_addr;
10383     SET_H_GR (FLD (f_operand1), opval);
10384     written |= (1 << 10);
10385     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10386   }
10387 }
10388 }
10389 ; tmp_tmp_mem; }));
10390   {
10391     SI opval = tmp_tmpd;
10392     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10393     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10394   }
10395 {
10396   {
10397     BI opval = LTSI (tmp_tmpd, 0);
10398     CPU (h_nbit) = opval;
10399     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10400   }
10401   {
10402     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10403     CPU (h_zbit) = opval;
10404     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10405   }
10406 SET_H_CBIT_MOVE (0);
10407 SET_H_VBIT_MOVE (0);
10408 {
10409   {
10410     BI opval = 0;
10411     CPU (h_xbit) = opval;
10412     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10413   }
10414   {
10415     BI opval = 0;
10416     SET_H_INSN_PREFIXED_P (opval);
10417     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10418   }
10419 }
10420 }
10421 }
10422
10423   abuf->written = written;
10424 #undef FLD
10425 }
10426   NEXT (vpc);
10427
10428   CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
10429 {
10430   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10431   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10432 #define FLD(f) abuf->fields.sfmt_addcbr.f
10433   int UNUSED written = 0;
10434   IADDR UNUSED pc = abuf->addr;
10435   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10436
10437 {
10438   QI tmp_tmpd;
10439   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10440 {
10441   SI tmp_oldregval;
10442   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10443   {
10444     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10445     SET_H_GR (FLD (f_operand2), opval);
10446     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10447   }
10448 }
10449 {
10450   {
10451     BI opval = LTQI (tmp_tmpd, 0);
10452     CPU (h_nbit) = opval;
10453     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10454   }
10455   {
10456     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10457     CPU (h_zbit) = opval;
10458     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10459   }
10460 SET_H_CBIT_MOVE (0);
10461 SET_H_VBIT_MOVE (0);
10462 {
10463   {
10464     BI opval = 0;
10465     CPU (h_xbit) = opval;
10466     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10467   }
10468   {
10469     BI opval = 0;
10470     SET_H_INSN_PREFIXED_P (opval);
10471     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10472   }
10473 }
10474 }
10475 }
10476
10477 #undef FLD
10478 }
10479   NEXT (vpc);
10480
10481   CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
10482 {
10483   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10484   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10485 #define FLD(f) abuf->fields.sfmt_addcwr.f
10486   int UNUSED written = 0;
10487   IADDR UNUSED pc = abuf->addr;
10488   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10489
10490 {
10491   HI tmp_tmpd;
10492   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10493 {
10494   SI tmp_oldregval;
10495   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10496   {
10497     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10498     SET_H_GR (FLD (f_operand2), opval);
10499     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10500   }
10501 }
10502 {
10503   {
10504     BI opval = LTHI (tmp_tmpd, 0);
10505     CPU (h_nbit) = opval;
10506     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10507   }
10508   {
10509     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10510     CPU (h_zbit) = opval;
10511     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10512   }
10513 SET_H_CBIT_MOVE (0);
10514 SET_H_VBIT_MOVE (0);
10515 {
10516   {
10517     BI opval = 0;
10518     CPU (h_xbit) = opval;
10519     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10520   }
10521   {
10522     BI opval = 0;
10523     SET_H_INSN_PREFIXED_P (opval);
10524     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10525   }
10526 }
10527 }
10528 }
10529
10530 #undef FLD
10531 }
10532   NEXT (vpc);
10533
10534   CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
10535 {
10536   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10537   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10538 #define FLD(f) abuf->fields.sfmt_addcdr.f
10539   int UNUSED written = 0;
10540   IADDR UNUSED pc = abuf->addr;
10541   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10542
10543 {
10544   SI tmp_tmpd;
10545   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10546   {
10547     SI opval = tmp_tmpd;
10548     SET_H_GR (FLD (f_operand2), opval);
10549     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10550   }
10551 {
10552   {
10553     BI opval = LTSI (tmp_tmpd, 0);
10554     CPU (h_nbit) = opval;
10555     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10556   }
10557   {
10558     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10559     CPU (h_zbit) = opval;
10560     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10561   }
10562 SET_H_CBIT_MOVE (0);
10563 SET_H_VBIT_MOVE (0);
10564 {
10565   {
10566     BI opval = 0;
10567     CPU (h_xbit) = opval;
10568     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10569   }
10570   {
10571     BI opval = 0;
10572     SET_H_INSN_PREFIXED_P (opval);
10573     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10574   }
10575 }
10576 }
10577 }
10578
10579 #undef FLD
10580 }
10581   NEXT (vpc);
10582
10583   CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
10584 {
10585   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10586   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10587 #define FLD(f) abuf->fields.sfmt_andq.f
10588   int UNUSED written = 0;
10589   IADDR UNUSED pc = abuf->addr;
10590   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10591
10592 {
10593   SI tmp_tmpd;
10594   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10595   {
10596     SI opval = tmp_tmpd;
10597     SET_H_GR (FLD (f_operand2), opval);
10598     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10599   }
10600 {
10601   {
10602     BI opval = LTSI (tmp_tmpd, 0);
10603     CPU (h_nbit) = opval;
10604     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10605   }
10606   {
10607     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10608     CPU (h_zbit) = opval;
10609     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10610   }
10611 SET_H_CBIT_MOVE (0);
10612 SET_H_VBIT_MOVE (0);
10613 {
10614   {
10615     BI opval = 0;
10616     CPU (h_xbit) = opval;
10617     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10618   }
10619   {
10620     BI opval = 0;
10621     SET_H_INSN_PREFIXED_P (opval);
10622     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10623   }
10624 }
10625 }
10626 }
10627
10628 #undef FLD
10629 }
10630   NEXT (vpc);
10631
10632   CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
10633 {
10634   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10635   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10636 #define FLD(f) abuf->fields.sfmt_addc_m.f
10637   int UNUSED written = 0;
10638   IADDR UNUSED pc = abuf->addr;
10639   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10640
10641 {
10642   QI tmp_tmpd;
10643   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10644 {
10645   SI tmp_oldregval;
10646   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10647   {
10648     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10649     SET_H_GR (FLD (f_operand2), opval);
10650     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10651   }
10652 }
10653 {
10654   {
10655     BI opval = LTQI (tmp_tmpd, 0);
10656     CPU (h_nbit) = opval;
10657     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10658   }
10659   {
10660     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10661     CPU (h_zbit) = opval;
10662     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10663   }
10664 SET_H_CBIT_MOVE (0);
10665 SET_H_VBIT_MOVE (0);
10666 {
10667   {
10668     BI opval = 0;
10669     CPU (h_xbit) = opval;
10670     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10671   }
10672   {
10673     BI opval = 0;
10674     SET_H_INSN_PREFIXED_P (opval);
10675     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10676   }
10677 }
10678 }
10679 }
10680
10681 #undef FLD
10682 }
10683   NEXT (vpc);
10684
10685   CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
10686 {
10687   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10688   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10689 #define FLD(f) abuf->fields.sfmt_addc_m.f
10690   int UNUSED written = 0;
10691   IADDR UNUSED pc = abuf->addr;
10692   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10693
10694 {
10695   HI tmp_tmpd;
10696   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10697 {
10698   SI tmp_oldregval;
10699   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10700   {
10701     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10702     SET_H_GR (FLD (f_operand2), opval);
10703     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10704   }
10705 }
10706 {
10707   {
10708     BI opval = LTHI (tmp_tmpd, 0);
10709     CPU (h_nbit) = opval;
10710     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10711   }
10712   {
10713     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10714     CPU (h_zbit) = opval;
10715     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10716   }
10717 SET_H_CBIT_MOVE (0);
10718 SET_H_VBIT_MOVE (0);
10719 {
10720   {
10721     BI opval = 0;
10722     CPU (h_xbit) = opval;
10723     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10724   }
10725   {
10726     BI opval = 0;
10727     SET_H_INSN_PREFIXED_P (opval);
10728     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10729   }
10730 }
10731 }
10732 }
10733
10734 #undef FLD
10735 }
10736   NEXT (vpc);
10737
10738   CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
10739 {
10740   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10741   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10742 #define FLD(f) abuf->fields.sfmt_addc_m.f
10743   int UNUSED written = 0;
10744   IADDR UNUSED pc = abuf->addr;
10745   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10746
10747 {
10748   SI tmp_tmpd;
10749   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10750   {
10751     SI opval = tmp_tmpd;
10752     SET_H_GR (FLD (f_operand2), opval);
10753     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10754   }
10755 {
10756   {
10757     BI opval = LTSI (tmp_tmpd, 0);
10758     CPU (h_nbit) = opval;
10759     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10760   }
10761   {
10762     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10763     CPU (h_zbit) = opval;
10764     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10765   }
10766 SET_H_CBIT_MOVE (0);
10767 SET_H_VBIT_MOVE (0);
10768 {
10769   {
10770     BI opval = 0;
10771     CPU (h_xbit) = opval;
10772     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10773   }
10774   {
10775     BI opval = 0;
10776     SET_H_INSN_PREFIXED_P (opval);
10777     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10778   }
10779 }
10780 }
10781 }
10782
10783 #undef FLD
10784 }
10785   NEXT (vpc);
10786
10787   CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
10788 {
10789   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10790   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10791 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10792   int UNUSED written = 0;
10793   IADDR UNUSED pc = abuf->addr;
10794   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10795
10796 {
10797   QI tmp_tmpd;
10798   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10799   QI tmp_tmp_mem;
10800   BI tmp_postinc;
10801   tmp_postinc = FLD (f_memmode);
10802 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10803 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10804 ; if (NEBI (tmp_postinc, 0)) {
10805 {
10806 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10807   tmp_addr = ADDSI (tmp_addr, 1);
10808 }
10809   {
10810     SI opval = tmp_addr;
10811     SET_H_GR (FLD (f_operand1), opval);
10812     written |= (1 << 11);
10813     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10814   }
10815 }
10816 }
10817 ; tmp_tmp_mem; }));
10818 {
10819   SI tmp_oldregval;
10820   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10821   {
10822     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10823     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10824     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10825   }
10826 }
10827 {
10828   {
10829     BI opval = LTQI (tmp_tmpd, 0);
10830     CPU (h_nbit) = opval;
10831     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10832   }
10833   {
10834     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10835     CPU (h_zbit) = opval;
10836     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10837   }
10838 SET_H_CBIT_MOVE (0);
10839 SET_H_VBIT_MOVE (0);
10840 {
10841   {
10842     BI opval = 0;
10843     CPU (h_xbit) = opval;
10844     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10845   }
10846   {
10847     BI opval = 0;
10848     SET_H_INSN_PREFIXED_P (opval);
10849     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10850   }
10851 }
10852 }
10853 }
10854
10855   abuf->written = written;
10856 #undef FLD
10857 }
10858   NEXT (vpc);
10859
10860   CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
10861 {
10862   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10863   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10864 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10865   int UNUSED written = 0;
10866   IADDR UNUSED pc = abuf->addr;
10867   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10868
10869 {
10870   HI tmp_tmpd;
10871   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10872   HI tmp_tmp_mem;
10873   BI tmp_postinc;
10874   tmp_postinc = FLD (f_memmode);
10875 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10876 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10877 ; if (NEBI (tmp_postinc, 0)) {
10878 {
10879 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10880   tmp_addr = ADDSI (tmp_addr, 2);
10881 }
10882   {
10883     SI opval = tmp_addr;
10884     SET_H_GR (FLD (f_operand1), opval);
10885     written |= (1 << 11);
10886     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10887   }
10888 }
10889 }
10890 ; tmp_tmp_mem; }));
10891 {
10892   SI tmp_oldregval;
10893   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10894   {
10895     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10896     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10897     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10898   }
10899 }
10900 {
10901   {
10902     BI opval = LTHI (tmp_tmpd, 0);
10903     CPU (h_nbit) = opval;
10904     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10905   }
10906   {
10907     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10908     CPU (h_zbit) = opval;
10909     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10910   }
10911 SET_H_CBIT_MOVE (0);
10912 SET_H_VBIT_MOVE (0);
10913 {
10914   {
10915     BI opval = 0;
10916     CPU (h_xbit) = opval;
10917     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10918   }
10919   {
10920     BI opval = 0;
10921     SET_H_INSN_PREFIXED_P (opval);
10922     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10923   }
10924 }
10925 }
10926 }
10927
10928   abuf->written = written;
10929 #undef FLD
10930 }
10931   NEXT (vpc);
10932
10933   CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
10934 {
10935   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10936   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10937 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10938   int UNUSED written = 0;
10939   IADDR UNUSED pc = abuf->addr;
10940   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10941
10942 {
10943   SI tmp_tmpd;
10944   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10945   SI tmp_tmp_mem;
10946   BI tmp_postinc;
10947   tmp_postinc = FLD (f_memmode);
10948 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10949 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10950 ; if (NEBI (tmp_postinc, 0)) {
10951 {
10952 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10953   tmp_addr = ADDSI (tmp_addr, 4);
10954 }
10955   {
10956     SI opval = tmp_addr;
10957     SET_H_GR (FLD (f_operand1), opval);
10958     written |= (1 << 10);
10959     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10960   }
10961 }
10962 }
10963 ; tmp_tmp_mem; }));
10964   {
10965     SI opval = tmp_tmpd;
10966     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10967     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10968   }
10969 {
10970   {
10971     BI opval = LTSI (tmp_tmpd, 0);
10972     CPU (h_nbit) = opval;
10973     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10974   }
10975   {
10976     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10977     CPU (h_zbit) = opval;
10978     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10979   }
10980 SET_H_CBIT_MOVE (0);
10981 SET_H_VBIT_MOVE (0);
10982 {
10983   {
10984     BI opval = 0;
10985     CPU (h_xbit) = opval;
10986     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10987   }
10988   {
10989     BI opval = 0;
10990     SET_H_INSN_PREFIXED_P (opval);
10991     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10992   }
10993 }
10994 }
10995 }
10996
10997   abuf->written = written;
10998 #undef FLD
10999 }
11000   NEXT (vpc);
11001
11002   CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
11003 {
11004   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11005   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11006 #define FLD(f) abuf->fields.sfmt_addcbr.f
11007   int UNUSED written = 0;
11008   IADDR UNUSED pc = abuf->addr;
11009   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
11010
11011 {
11012   QI tmp_tmpd;
11013   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
11014 {
11015   SI tmp_oldregval;
11016   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11017   {
11018     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11019     SET_H_GR (FLD (f_operand2), opval);
11020     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11021   }
11022 }
11023 {
11024   {
11025     BI opval = LTQI (tmp_tmpd, 0);
11026     CPU (h_nbit) = opval;
11027     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11028   }
11029   {
11030     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11031     CPU (h_zbit) = opval;
11032     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11033   }
11034 SET_H_CBIT_MOVE (0);
11035 SET_H_VBIT_MOVE (0);
11036 {
11037   {
11038     BI opval = 0;
11039     CPU (h_xbit) = opval;
11040     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11041   }
11042   {
11043     BI opval = 0;
11044     SET_H_INSN_PREFIXED_P (opval);
11045     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11046   }
11047 }
11048 }
11049 }
11050
11051 #undef FLD
11052 }
11053   NEXT (vpc);
11054
11055   CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
11056 {
11057   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11058   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11059 #define FLD(f) abuf->fields.sfmt_addcwr.f
11060   int UNUSED written = 0;
11061   IADDR UNUSED pc = abuf->addr;
11062   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
11063
11064 {
11065   HI tmp_tmpd;
11066   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
11067 {
11068   SI tmp_oldregval;
11069   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11070   {
11071     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11072     SET_H_GR (FLD (f_operand2), opval);
11073     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11074   }
11075 }
11076 {
11077   {
11078     BI opval = LTHI (tmp_tmpd, 0);
11079     CPU (h_nbit) = opval;
11080     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11081   }
11082   {
11083     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11084     CPU (h_zbit) = opval;
11085     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11086   }
11087 SET_H_CBIT_MOVE (0);
11088 SET_H_VBIT_MOVE (0);
11089 {
11090   {
11091     BI opval = 0;
11092     CPU (h_xbit) = opval;
11093     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11094   }
11095   {
11096     BI opval = 0;
11097     SET_H_INSN_PREFIXED_P (opval);
11098     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11099   }
11100 }
11101 }
11102 }
11103
11104 #undef FLD
11105 }
11106   NEXT (vpc);
11107
11108   CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
11109 {
11110   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11111   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11112 #define FLD(f) abuf->fields.sfmt_addcdr.f
11113   int UNUSED written = 0;
11114   IADDR UNUSED pc = abuf->addr;
11115   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
11116
11117 {
11118   SI tmp_tmpd;
11119   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
11120   {
11121     SI opval = tmp_tmpd;
11122     SET_H_GR (FLD (f_operand2), opval);
11123     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11124   }
11125 {
11126   {
11127     BI opval = LTSI (tmp_tmpd, 0);
11128     CPU (h_nbit) = opval;
11129     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11130   }
11131   {
11132     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11133     CPU (h_zbit) = opval;
11134     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11135   }
11136 SET_H_CBIT_MOVE (0);
11137 SET_H_VBIT_MOVE (0);
11138 {
11139   {
11140     BI opval = 0;
11141     CPU (h_xbit) = opval;
11142     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11143   }
11144   {
11145     BI opval = 0;
11146     SET_H_INSN_PREFIXED_P (opval);
11147     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11148   }
11149 }
11150 }
11151 }
11152
11153 #undef FLD
11154 }
11155   NEXT (vpc);
11156
11157   CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
11158 {
11159   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11160   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11161 #define FLD(f) abuf->fields.sfmt_andq.f
11162   int UNUSED written = 0;
11163   IADDR UNUSED pc = abuf->addr;
11164   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11165
11166 {
11167   SI tmp_tmpd;
11168   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
11169   {
11170     SI opval = tmp_tmpd;
11171     SET_H_GR (FLD (f_operand2), opval);
11172     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11173   }
11174 {
11175   {
11176     BI opval = LTSI (tmp_tmpd, 0);
11177     CPU (h_nbit) = opval;
11178     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11179   }
11180   {
11181     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11182     CPU (h_zbit) = opval;
11183     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11184   }
11185 SET_H_CBIT_MOVE (0);
11186 SET_H_VBIT_MOVE (0);
11187 {
11188   {
11189     BI opval = 0;
11190     CPU (h_xbit) = opval;
11191     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11192   }
11193   {
11194     BI opval = 0;
11195     SET_H_INSN_PREFIXED_P (opval);
11196     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11197   }
11198 }
11199 }
11200 }
11201
11202 #undef FLD
11203 }
11204   NEXT (vpc);
11205
11206   CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
11207 {
11208   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11209   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11210 #define FLD(f) abuf->fields.sfmt_muls_b.f
11211   int UNUSED written = 0;
11212   IADDR UNUSED pc = abuf->addr;
11213   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11214
11215 {
11216   SI tmp_tmpd;
11217   tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
11218   {
11219     SI opval = tmp_tmpd;
11220     SET_H_GR (FLD (f_operand2), opval);
11221     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11222   }
11223 {
11224   {
11225     BI opval = LTSI (tmp_tmpd, 0);
11226     CPU (h_nbit) = opval;
11227     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11228   }
11229   {
11230     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11231     CPU (h_zbit) = opval;
11232     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11233   }
11234 SET_H_CBIT_MOVE (0);
11235 SET_H_VBIT_MOVE (0);
11236 {
11237   {
11238     BI opval = 0;
11239     CPU (h_xbit) = opval;
11240     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11241   }
11242   {
11243     BI opval = 0;
11244     SET_H_INSN_PREFIXED_P (opval);
11245     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11246   }
11247 }
11248 }
11249 }
11250
11251 #undef FLD
11252 }
11253   NEXT (vpc);
11254
11255   CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
11256 {
11257   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11258   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11259 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
11260   int UNUSED written = 0;
11261   IADDR UNUSED pc = abuf->addr;
11262   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11263
11264 {
11265   SI tmp_tmps;
11266   SI tmp_tmpd;
11267   tmp_tmps = GET_H_GR (FLD (f_operand1));
11268   tmp_tmpd = ({   SI tmp_tmpcode;
11269   SI tmp_tmpval;
11270   SI tmp_tmpres;
11271   tmp_tmpcode = FLD (f_operand2);
11272 ;   tmp_tmpval = tmp_tmps;
11273 ; if (EQSI (tmp_tmpcode, 0)) {
11274   tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
11275 }
11276  else if (EQSI (tmp_tmpcode, 1)) {
11277   tmp_tmpres = ({   SI tmp_tmpr;
11278   tmp_tmpr = tmp_tmpval;
11279 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11280 }
11281  else if (EQSI (tmp_tmpcode, 2)) {
11282   tmp_tmpres = ({   SI tmp_tmpb;
11283   tmp_tmpb = tmp_tmpval;
11284 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11285 }
11286  else if (EQSI (tmp_tmpcode, 3)) {
11287   tmp_tmpres = ({   SI tmp_tmpr;
11288   tmp_tmpr = ({   SI tmp_tmpb;
11289   tmp_tmpb = tmp_tmpval;
11290 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11291 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11292 }
11293  else if (EQSI (tmp_tmpcode, 4)) {
11294   tmp_tmpres = ({   SI tmp_tmpb;
11295   tmp_tmpb = tmp_tmpval;
11296 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11297 }
11298  else if (EQSI (tmp_tmpcode, 5)) {
11299   tmp_tmpres = ({   SI tmp_tmpr;
11300   tmp_tmpr = ({   SI tmp_tmpb;
11301   tmp_tmpb = tmp_tmpval;
11302 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11303 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11304 }
11305  else if (EQSI (tmp_tmpcode, 6)) {
11306   tmp_tmpres = ({   SI tmp_tmpb;
11307   tmp_tmpb = ({   SI tmp_tmpb;
11308   tmp_tmpb = tmp_tmpval;
11309 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11310 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11311 }
11312  else if (EQSI (tmp_tmpcode, 7)) {
11313   tmp_tmpres = ({   SI tmp_tmpr;
11314   tmp_tmpr = ({   SI tmp_tmpb;
11315   tmp_tmpb = ({   SI tmp_tmpb;
11316   tmp_tmpb = tmp_tmpval;
11317 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11318 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11319 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11320 }
11321  else if (EQSI (tmp_tmpcode, 8)) {
11322   tmp_tmpres = INVSI (tmp_tmpval);
11323 }
11324  else if (EQSI (tmp_tmpcode, 9)) {
11325   tmp_tmpres = ({   SI tmp_tmpr;
11326   tmp_tmpr = INVSI (tmp_tmpval);
11327 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11328 }
11329  else if (EQSI (tmp_tmpcode, 10)) {
11330   tmp_tmpres = ({   SI tmp_tmpb;
11331   tmp_tmpb = INVSI (tmp_tmpval);
11332 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11333 }
11334  else if (EQSI (tmp_tmpcode, 11)) {
11335   tmp_tmpres = ({   SI tmp_tmpr;
11336   tmp_tmpr = ({   SI tmp_tmpb;
11337   tmp_tmpb = INVSI (tmp_tmpval);
11338 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11339 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11340 }
11341  else if (EQSI (tmp_tmpcode, 12)) {
11342   tmp_tmpres = ({   SI tmp_tmpb;
11343   tmp_tmpb = INVSI (tmp_tmpval);
11344 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11345 }
11346  else if (EQSI (tmp_tmpcode, 13)) {
11347   tmp_tmpres = ({   SI tmp_tmpr;
11348   tmp_tmpr = ({   SI tmp_tmpb;
11349   tmp_tmpb = INVSI (tmp_tmpval);
11350 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11351 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11352 }
11353  else if (EQSI (tmp_tmpcode, 14)) {
11354   tmp_tmpres = ({   SI tmp_tmpb;
11355   tmp_tmpb = ({   SI tmp_tmpb;
11356   tmp_tmpb = INVSI (tmp_tmpval);
11357 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11358 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11359 }
11360  else if (EQSI (tmp_tmpcode, 15)) {
11361   tmp_tmpres = ({   SI tmp_tmpr;
11362   tmp_tmpr = ({   SI tmp_tmpb;
11363   tmp_tmpb = ({   SI tmp_tmpb;
11364   tmp_tmpb = INVSI (tmp_tmpval);
11365 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11366 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11367 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11368 }
11369 ; tmp_tmpres; });
11370   {
11371     SI opval = tmp_tmpd;
11372     SET_H_GR (FLD (f_operand1), opval);
11373     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11374   }
11375 {
11376   {
11377     BI opval = LTSI (tmp_tmpd, 0);
11378     CPU (h_nbit) = opval;
11379     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11380   }
11381   {
11382     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11383     CPU (h_zbit) = opval;
11384     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11385   }
11386 SET_H_CBIT_MOVE (0);
11387 SET_H_VBIT_MOVE (0);
11388 {
11389   {
11390     BI opval = 0;
11391     CPU (h_xbit) = opval;
11392     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11393   }
11394   {
11395     BI opval = 0;
11396     SET_H_INSN_PREFIXED_P (opval);
11397     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11398   }
11399 }
11400 }
11401 }
11402
11403 #undef FLD
11404 }
11405   NEXT (vpc);
11406
11407   CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
11408 {
11409   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11410   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11411 #define FLD(f) abuf->fields.sfmt_addc_m.f
11412   int UNUSED written = 0;
11413   IADDR UNUSED pc = abuf->addr;
11414   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11415
11416 {
11417   QI tmp_tmpd;
11418   SI tmp_cnt1;
11419   SI tmp_cnt2;
11420   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11421   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11422   tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11423 {
11424   SI tmp_oldregval;
11425   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11426   {
11427     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11428     SET_H_GR (FLD (f_operand2), opval);
11429     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11430   }
11431 }
11432 {
11433   {
11434     BI opval = LTQI (tmp_tmpd, 0);
11435     CPU (h_nbit) = opval;
11436     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11437   }
11438   {
11439     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11440     CPU (h_zbit) = opval;
11441     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11442   }
11443 SET_H_CBIT_MOVE (0);
11444 SET_H_VBIT_MOVE (0);
11445 {
11446   {
11447     BI opval = 0;
11448     CPU (h_xbit) = opval;
11449     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11450   }
11451   {
11452     BI opval = 0;
11453     SET_H_INSN_PREFIXED_P (opval);
11454     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11455   }
11456 }
11457 }
11458 }
11459
11460 #undef FLD
11461 }
11462   NEXT (vpc);
11463
11464   CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
11465 {
11466   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11467   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11468 #define FLD(f) abuf->fields.sfmt_addc_m.f
11469   int UNUSED written = 0;
11470   IADDR UNUSED pc = abuf->addr;
11471   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11472
11473 {
11474   HI tmp_tmpd;
11475   SI tmp_cnt1;
11476   SI tmp_cnt2;
11477   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11478   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11479   tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11480 {
11481   SI tmp_oldregval;
11482   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11483   {
11484     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11485     SET_H_GR (FLD (f_operand2), opval);
11486     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11487   }
11488 }
11489 {
11490   {
11491     BI opval = LTHI (tmp_tmpd, 0);
11492     CPU (h_nbit) = opval;
11493     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11494   }
11495   {
11496     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11497     CPU (h_zbit) = opval;
11498     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11499   }
11500 SET_H_CBIT_MOVE (0);
11501 SET_H_VBIT_MOVE (0);
11502 {
11503   {
11504     BI opval = 0;
11505     CPU (h_xbit) = opval;
11506     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11507   }
11508   {
11509     BI opval = 0;
11510     SET_H_INSN_PREFIXED_P (opval);
11511     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11512   }
11513 }
11514 }
11515 }
11516
11517 #undef FLD
11518 }
11519   NEXT (vpc);
11520
11521   CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
11522 {
11523   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11524   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11525 #define FLD(f) abuf->fields.sfmt_addc_m.f
11526   int UNUSED written = 0;
11527   IADDR UNUSED pc = abuf->addr;
11528   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11529
11530 {
11531   SI tmp_tmpd;
11532   SI tmp_cnt1;
11533   SI tmp_cnt2;
11534   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11535   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11536   tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11537   {
11538     SI opval = tmp_tmpd;
11539     SET_H_GR (FLD (f_operand2), opval);
11540     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11541   }
11542 {
11543   {
11544     BI opval = LTSI (tmp_tmpd, 0);
11545     CPU (h_nbit) = opval;
11546     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11547   }
11548   {
11549     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11550     CPU (h_zbit) = opval;
11551     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11552   }
11553 SET_H_CBIT_MOVE (0);
11554 SET_H_VBIT_MOVE (0);
11555 {
11556   {
11557     BI opval = 0;
11558     CPU (h_xbit) = opval;
11559     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11560   }
11561   {
11562     BI opval = 0;
11563     SET_H_INSN_PREFIXED_P (opval);
11564     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11565   }
11566 }
11567 }
11568 }
11569
11570 #undef FLD
11571 }
11572   NEXT (vpc);
11573
11574   CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
11575 {
11576   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11577   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11578 #define FLD(f) abuf->fields.sfmt_asrq.f
11579   int UNUSED written = 0;
11580   IADDR UNUSED pc = abuf->addr;
11581   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11582
11583 {
11584   SI tmp_tmpd;
11585   tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11586   {
11587     SI opval = tmp_tmpd;
11588     SET_H_GR (FLD (f_operand2), opval);
11589     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11590   }
11591 {
11592   {
11593     BI opval = LTSI (tmp_tmpd, 0);
11594     CPU (h_nbit) = opval;
11595     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11596   }
11597   {
11598     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11599     CPU (h_zbit) = opval;
11600     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11601   }
11602 SET_H_CBIT_MOVE (0);
11603 SET_H_VBIT_MOVE (0);
11604 {
11605   {
11606     BI opval = 0;
11607     CPU (h_xbit) = opval;
11608     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11609   }
11610   {
11611     BI opval = 0;
11612     SET_H_INSN_PREFIXED_P (opval);
11613     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11614   }
11615 }
11616 }
11617 }
11618
11619 #undef FLD
11620 }
11621   NEXT (vpc);
11622
11623   CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
11624 {
11625   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11626   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11627 #define FLD(f) abuf->fields.sfmt_addc_m.f
11628   int UNUSED written = 0;
11629   IADDR UNUSED pc = abuf->addr;
11630   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11631
11632 {
11633   SI tmp_tmpd;
11634   SI tmp_cnt;
11635   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11636   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11637 {
11638   SI tmp_oldregval;
11639   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11640   {
11641     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11642     SET_H_GR (FLD (f_operand2), opval);
11643     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11644   }
11645 }
11646 {
11647   {
11648     BI opval = LTQI (tmp_tmpd, 0);
11649     CPU (h_nbit) = opval;
11650     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11651   }
11652   {
11653     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11654     CPU (h_zbit) = opval;
11655     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11656   }
11657 SET_H_CBIT_MOVE (0);
11658 SET_H_VBIT_MOVE (0);
11659 {
11660   {
11661     BI opval = 0;
11662     CPU (h_xbit) = opval;
11663     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11664   }
11665   {
11666     BI opval = 0;
11667     SET_H_INSN_PREFIXED_P (opval);
11668     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11669   }
11670 }
11671 }
11672 }
11673
11674 #undef FLD
11675 }
11676   NEXT (vpc);
11677
11678   CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
11679 {
11680   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11681   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11682 #define FLD(f) abuf->fields.sfmt_addc_m.f
11683   int UNUSED written = 0;
11684   IADDR UNUSED pc = abuf->addr;
11685   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11686
11687 {
11688   SI tmp_tmpd;
11689   SI tmp_cnt;
11690   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11691   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11692 {
11693   SI tmp_oldregval;
11694   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11695   {
11696     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11697     SET_H_GR (FLD (f_operand2), opval);
11698     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11699   }
11700 }
11701 {
11702   {
11703     BI opval = LTHI (tmp_tmpd, 0);
11704     CPU (h_nbit) = opval;
11705     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11706   }
11707   {
11708     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11709     CPU (h_zbit) = opval;
11710     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11711   }
11712 SET_H_CBIT_MOVE (0);
11713 SET_H_VBIT_MOVE (0);
11714 {
11715   {
11716     BI opval = 0;
11717     CPU (h_xbit) = opval;
11718     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11719   }
11720   {
11721     BI opval = 0;
11722     SET_H_INSN_PREFIXED_P (opval);
11723     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11724   }
11725 }
11726 }
11727 }
11728
11729 #undef FLD
11730 }
11731   NEXT (vpc);
11732
11733   CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
11734 {
11735   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11736   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11737 #define FLD(f) abuf->fields.sfmt_addc_m.f
11738   int UNUSED written = 0;
11739   IADDR UNUSED pc = abuf->addr;
11740   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11741
11742 {
11743   SI tmp_tmpd;
11744   SI tmp_cnt;
11745   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11746   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11747   {
11748     SI opval = tmp_tmpd;
11749     SET_H_GR (FLD (f_operand2), opval);
11750     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11751   }
11752 {
11753   {
11754     BI opval = LTSI (tmp_tmpd, 0);
11755     CPU (h_nbit) = opval;
11756     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11757   }
11758   {
11759     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11760     CPU (h_zbit) = opval;
11761     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11762   }
11763 SET_H_CBIT_MOVE (0);
11764 SET_H_VBIT_MOVE (0);
11765 {
11766   {
11767     BI opval = 0;
11768     CPU (h_xbit) = opval;
11769     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11770   }
11771   {
11772     BI opval = 0;
11773     SET_H_INSN_PREFIXED_P (opval);
11774     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11775   }
11776 }
11777 }
11778 }
11779
11780 #undef FLD
11781 }
11782   NEXT (vpc);
11783
11784   CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
11785 {
11786   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11787   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11788 #define FLD(f) abuf->fields.sfmt_asrq.f
11789   int UNUSED written = 0;
11790   IADDR UNUSED pc = abuf->addr;
11791   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11792
11793 {
11794   SI tmp_tmpd;
11795   tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11796   {
11797     SI opval = tmp_tmpd;
11798     SET_H_GR (FLD (f_operand2), opval);
11799     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11800   }
11801 {
11802   {
11803     BI opval = LTSI (tmp_tmpd, 0);
11804     CPU (h_nbit) = opval;
11805     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11806   }
11807   {
11808     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11809     CPU (h_zbit) = opval;
11810     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11811   }
11812 SET_H_CBIT_MOVE (0);
11813 SET_H_VBIT_MOVE (0);
11814 {
11815   {
11816     BI opval = 0;
11817     CPU (h_xbit) = opval;
11818     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11819   }
11820   {
11821     BI opval = 0;
11822     SET_H_INSN_PREFIXED_P (opval);
11823     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11824   }
11825 }
11826 }
11827 }
11828
11829 #undef FLD
11830 }
11831   NEXT (vpc);
11832
11833   CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
11834 {
11835   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11836   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11837 #define FLD(f) abuf->fields.sfmt_addc_m.f
11838   int UNUSED written = 0;
11839   IADDR UNUSED pc = abuf->addr;
11840   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11841
11842 {
11843   SI tmp_tmpd;
11844   SI tmp_cnt;
11845   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11846   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11847 {
11848   SI tmp_oldregval;
11849   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11850   {
11851     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11852     SET_H_GR (FLD (f_operand2), opval);
11853     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11854   }
11855 }
11856 {
11857   {
11858     BI opval = LTQI (tmp_tmpd, 0);
11859     CPU (h_nbit) = opval;
11860     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11861   }
11862   {
11863     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11864     CPU (h_zbit) = opval;
11865     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11866   }
11867 SET_H_CBIT_MOVE (0);
11868 SET_H_VBIT_MOVE (0);
11869 {
11870   {
11871     BI opval = 0;
11872     CPU (h_xbit) = opval;
11873     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11874   }
11875   {
11876     BI opval = 0;
11877     SET_H_INSN_PREFIXED_P (opval);
11878     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11879   }
11880 }
11881 }
11882 }
11883
11884 #undef FLD
11885 }
11886   NEXT (vpc);
11887
11888   CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
11889 {
11890   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11891   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11892 #define FLD(f) abuf->fields.sfmt_addc_m.f
11893   int UNUSED written = 0;
11894   IADDR UNUSED pc = abuf->addr;
11895   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11896
11897 {
11898   SI tmp_tmpd;
11899   SI tmp_cnt;
11900   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11901   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11902 {
11903   SI tmp_oldregval;
11904   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11905   {
11906     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11907     SET_H_GR (FLD (f_operand2), opval);
11908     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11909   }
11910 }
11911 {
11912   {
11913     BI opval = LTHI (tmp_tmpd, 0);
11914     CPU (h_nbit) = opval;
11915     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11916   }
11917   {
11918     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11919     CPU (h_zbit) = opval;
11920     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11921   }
11922 SET_H_CBIT_MOVE (0);
11923 SET_H_VBIT_MOVE (0);
11924 {
11925   {
11926     BI opval = 0;
11927     CPU (h_xbit) = opval;
11928     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11929   }
11930   {
11931     BI opval = 0;
11932     SET_H_INSN_PREFIXED_P (opval);
11933     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11934   }
11935 }
11936 }
11937 }
11938
11939 #undef FLD
11940 }
11941   NEXT (vpc);
11942
11943   CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
11944 {
11945   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11946   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11947 #define FLD(f) abuf->fields.sfmt_addc_m.f
11948   int UNUSED written = 0;
11949   IADDR UNUSED pc = abuf->addr;
11950   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11951
11952 {
11953   SI tmp_tmpd;
11954   SI tmp_cnt;
11955   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11956   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11957   {
11958     SI opval = tmp_tmpd;
11959     SET_H_GR (FLD (f_operand2), opval);
11960     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11961   }
11962 {
11963   {
11964     BI opval = LTSI (tmp_tmpd, 0);
11965     CPU (h_nbit) = opval;
11966     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11967   }
11968   {
11969     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11970     CPU (h_zbit) = opval;
11971     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11972   }
11973 SET_H_CBIT_MOVE (0);
11974 SET_H_VBIT_MOVE (0);
11975 {
11976   {
11977     BI opval = 0;
11978     CPU (h_xbit) = opval;
11979     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11980   }
11981   {
11982     BI opval = 0;
11983     SET_H_INSN_PREFIXED_P (opval);
11984     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11985   }
11986 }
11987 }
11988 }
11989
11990 #undef FLD
11991 }
11992   NEXT (vpc);
11993
11994   CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
11995 {
11996   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11997   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11998 #define FLD(f) abuf->fields.sfmt_asrq.f
11999   int UNUSED written = 0;
12000   IADDR UNUSED pc = abuf->addr;
12001   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12002
12003 {
12004   SI tmp_tmpd;
12005   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
12006   {
12007     SI opval = tmp_tmpd;
12008     SET_H_GR (FLD (f_operand2), opval);
12009     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12010   }
12011 {
12012   {
12013     BI opval = LTSI (tmp_tmpd, 0);
12014     CPU (h_nbit) = opval;
12015     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12016   }
12017   {
12018     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12019     CPU (h_zbit) = opval;
12020     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12021   }
12022 SET_H_CBIT_MOVE (0);
12023 SET_H_VBIT_MOVE (0);
12024 {
12025   {
12026     BI opval = 0;
12027     CPU (h_xbit) = opval;
12028     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12029   }
12030   {
12031     BI opval = 0;
12032     SET_H_INSN_PREFIXED_P (opval);
12033     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12034   }
12035 }
12036 }
12037 }
12038
12039 #undef FLD
12040 }
12041   NEXT (vpc);
12042
12043   CASE (sem, INSN_BTST) : /* $Rs,$Rd */
12044 {
12045   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12046   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12047 #define FLD(f) abuf->fields.sfmt_muls_b.f
12048   int UNUSED written = 0;
12049   IADDR UNUSED pc = abuf->addr;
12050   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12051
12052 {
12053   SI tmp_tmpd;
12054   SI tmp_cnt;
12055   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
12056 {
12057   {
12058     BI opval = LTSI (tmp_tmpd, 0);
12059     CPU (h_nbit) = opval;
12060     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12061   }
12062   {
12063     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12064     CPU (h_zbit) = opval;
12065     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12066   }
12067 SET_H_CBIT_MOVE (0);
12068 SET_H_VBIT_MOVE (0);
12069 {
12070   {
12071     BI opval = 0;
12072     CPU (h_xbit) = opval;
12073     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12074   }
12075   {
12076     BI opval = 0;
12077     SET_H_INSN_PREFIXED_P (opval);
12078     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12079   }
12080 }
12081 }
12082 }
12083
12084 #undef FLD
12085 }
12086   NEXT (vpc);
12087
12088   CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
12089 {
12090   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12091   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12092 #define FLD(f) abuf->fields.sfmt_asrq.f
12093   int UNUSED written = 0;
12094   IADDR UNUSED pc = abuf->addr;
12095   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12096
12097 {
12098   SI tmp_tmpd;
12099   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
12100 {
12101   {
12102     BI opval = LTSI (tmp_tmpd, 0);
12103     CPU (h_nbit) = opval;
12104     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12105   }
12106   {
12107     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12108     CPU (h_zbit) = opval;
12109     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12110   }
12111 SET_H_CBIT_MOVE (0);
12112 SET_H_VBIT_MOVE (0);
12113 {
12114   {
12115     BI opval = 0;
12116     CPU (h_xbit) = opval;
12117     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12118   }
12119   {
12120     BI opval = 0;
12121     SET_H_INSN_PREFIXED_P (opval);
12122     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12123   }
12124 }
12125 }
12126 }
12127
12128 #undef FLD
12129 }
12130   NEXT (vpc);
12131
12132   CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
12133 {
12134   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12135   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12136 #define FLD(f) abuf->fields.sfmt_setf.f
12137   int UNUSED written = 0;
12138   IADDR UNUSED pc = abuf->addr;
12139   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12140
12141 {
12142   SI tmp_tmp;
12143   tmp_tmp = FLD (f_dstsrc);
12144 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
12145   {
12146     BI opval = 1;
12147     CPU (h_cbit) = opval;
12148     written |= (1 << 1);
12149     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
12150   }
12151 }
12152 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
12153   {
12154     BI opval = 1;
12155     CPU (h_vbit) = opval;
12156     written |= (1 << 7);
12157     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
12158   }
12159 }
12160 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
12161   {
12162     BI opval = 1;
12163     CPU (h_zbit) = opval;
12164     written |= (1 << 9);
12165     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12166   }
12167 }
12168 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
12169   {
12170     BI opval = 1;
12171     CPU (h_nbit) = opval;
12172     written |= (1 << 3);
12173     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12174   }
12175 }
12176 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12177   {
12178     BI opval = 1;
12179     CPU (h_xbit) = opval;
12180     written |= (1 << 8);
12181     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12182   }
12183 }
12184 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12185   {
12186     BI opval = 1;
12187     SET_H_IBIT (opval);
12188     written |= (1 << 2);
12189     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12190   }
12191 }
12192 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12193   {
12194     BI opval = 1;
12195     SET_H_UBIT (opval);
12196     written |= (1 << 6);
12197     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12198   }
12199 }
12200 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12201   {
12202     BI opval = 1;
12203     CPU (h_pbit) = opval;
12204     written |= (1 << 4);
12205     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12206   }
12207 }
12208   {
12209     BI opval = 0;
12210     SET_H_INSN_PREFIXED_P (opval);
12211     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12212   }
12213 if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12214   {
12215     BI opval = 0;
12216     CPU (h_xbit) = opval;
12217     written |= (1 << 8);
12218     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12219   }
12220 }
12221 }
12222
12223   abuf->written = written;
12224 #undef FLD
12225 }
12226   NEXT (vpc);
12227
12228   CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
12229 {
12230   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12231   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12232 #define FLD(f) abuf->fields.sfmt_setf.f
12233   int UNUSED written = 0;
12234   IADDR UNUSED pc = abuf->addr;
12235   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12236
12237 {
12238   SI tmp_tmp;
12239   tmp_tmp = FLD (f_dstsrc);
12240 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
12241   {
12242     BI opval = 0;
12243     CPU (h_cbit) = opval;
12244     written |= (1 << 1);
12245     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
12246   }
12247 }
12248 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
12249   {
12250     BI opval = 0;
12251     CPU (h_vbit) = opval;
12252     written |= (1 << 7);
12253     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
12254   }
12255 }
12256 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
12257   {
12258     BI opval = 0;
12259     CPU (h_zbit) = opval;
12260     written |= (1 << 9);
12261     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12262   }
12263 }
12264 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
12265   {
12266     BI opval = 0;
12267     CPU (h_nbit) = opval;
12268     written |= (1 << 3);
12269     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12270   }
12271 }
12272 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12273   {
12274     BI opval = 0;
12275     CPU (h_xbit) = opval;
12276     written |= (1 << 8);
12277     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12278   }
12279 }
12280 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12281   {
12282     BI opval = 0;
12283     SET_H_IBIT (opval);
12284     written |= (1 << 2);
12285     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12286   }
12287 }
12288 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12289   {
12290     BI opval = 0;
12291     SET_H_UBIT (opval);
12292     written |= (1 << 6);
12293     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12294   }
12295 }
12296 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12297   {
12298     BI opval = 0;
12299     CPU (h_pbit) = opval;
12300     written |= (1 << 4);
12301     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12302   }
12303 }
12304 {
12305   {
12306     BI opval = 0;
12307     CPU (h_xbit) = opval;
12308     written |= (1 << 8);
12309     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12310   }
12311   {
12312     BI opval = 0;
12313     SET_H_INSN_PREFIXED_P (opval);
12314     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12315   }
12316 }
12317 }
12318
12319   abuf->written = written;
12320 #undef FLD
12321 }
12322   NEXT (vpc);
12323
12324   CASE (sem, INSN_RFE) : /* rfe */
12325 {
12326   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12327   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12328 #define FLD(f) abuf->fields.sfmt_rfe.f
12329   int UNUSED written = 0;
12330   IADDR UNUSED pc = abuf->addr;
12331   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12332
12333 {
12334   USI tmp_oldccs;
12335   USI tmp_samebits;
12336   USI tmp_shiftbits;
12337   USI tmp_keepmask;
12338   BI tmp_p1;
12339   tmp_oldccs = GET_H_SR (((UINT) 13));
12340   tmp_keepmask = 0xc0000000;
12341   tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
12342   tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
12343   tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
12344   {
12345     SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
12346     SET_H_SR (((UINT) 13), opval);
12347     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12348   }
12349 }
12350
12351 #undef FLD
12352 }
12353   NEXT (vpc);
12354
12355   CASE (sem, INSN_SFE) : /* sfe */
12356 {
12357   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12358   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12359 #define FLD(f) abuf->fields.sfmt_rfe.f
12360   int UNUSED written = 0;
12361   IADDR UNUSED pc = abuf->addr;
12362   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12363
12364 {
12365   SI tmp_oldccs;
12366   SI tmp_savemask;
12367   tmp_savemask = 0xc0000000;
12368   tmp_oldccs = GET_H_SR (((UINT) 13));
12369   {
12370     SI opval = ORSI (ANDSI (tmp_savemask, tmp_oldccs), ANDSI (INVSI (tmp_savemask), SLLSI (tmp_oldccs, 10)));
12371     SET_H_SR (((UINT) 13), opval);
12372     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12373   }
12374 }
12375
12376 #undef FLD
12377 }
12378   NEXT (vpc);
12379
12380   CASE (sem, INSN_RFG) : /* rfg */
12381 {
12382   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12383   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12384 #define FLD(f) abuf->fields.fmt_empty.f
12385   int UNUSED written = 0;
12386   IADDR UNUSED pc = abuf->addr;
12387   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12388
12389 crisv32f_rfg_handler (current_cpu, pc);
12390
12391 #undef FLD
12392 }
12393   NEXT (vpc);
12394
12395   CASE (sem, INSN_RFN) : /* rfn */
12396 {
12397   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12398   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12399 #define FLD(f) abuf->fields.sfmt_rfe.f
12400   int UNUSED written = 0;
12401   IADDR UNUSED pc = abuf->addr;
12402   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12403
12404 {
12405 {
12406   USI tmp_oldccs;
12407   USI tmp_samebits;
12408   USI tmp_shiftbits;
12409   USI tmp_keepmask;
12410   BI tmp_p1;
12411   tmp_oldccs = GET_H_SR (((UINT) 13));
12412   tmp_keepmask = 0xc0000000;
12413   tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
12414   tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
12415   tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
12416   {
12417     SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
12418     SET_H_SR (((UINT) 13), opval);
12419     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12420   }
12421 }
12422   {
12423     BI opval = 1;
12424     SET_H_MBIT (opval);
12425     TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
12426   }
12427 }
12428
12429 #undef FLD
12430 }
12431   NEXT (vpc);
12432
12433   CASE (sem, INSN_HALT) : /* halt */
12434 {
12435   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12436   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12437 #define FLD(f) abuf->fields.fmt_empty.f
12438   int UNUSED written = 0;
12439   IADDR UNUSED pc = abuf->addr;
12440   SEM_BRANCH_INIT
12441   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12442
12443   {
12444     USI opval = crisv32f_halt_handler (current_cpu, pc);
12445     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12446     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12447   }
12448
12449   SEM_BRANCH_FINI (vpc);
12450 #undef FLD
12451 }
12452   NEXT (vpc);
12453
12454   CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
12455 {
12456   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12457   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12458 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12459   int UNUSED written = 0;
12460   IADDR UNUSED pc = abuf->addr;
12461   SEM_BRANCH_INIT
12462   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12463
12464 {
12465   BI tmp_truthval;
12466   tmp_truthval = ({   SI tmp_tmpcond;
12467   BI tmp_condres;
12468   tmp_tmpcond = FLD (f_operand2);
12469 ; if (EQSI (tmp_tmpcond, 0)) {
12470   tmp_condres = NOTBI (CPU (h_cbit));
12471 }
12472  else if (EQSI (tmp_tmpcond, 1)) {
12473   tmp_condres = CPU (h_cbit);
12474 }
12475  else if (EQSI (tmp_tmpcond, 2)) {
12476   tmp_condres = NOTBI (CPU (h_zbit));
12477 }
12478  else if (EQSI (tmp_tmpcond, 3)) {
12479   tmp_condres = CPU (h_zbit);
12480 }
12481  else if (EQSI (tmp_tmpcond, 4)) {
12482   tmp_condres = NOTBI (CPU (h_vbit));
12483 }
12484  else if (EQSI (tmp_tmpcond, 5)) {
12485   tmp_condres = CPU (h_vbit);
12486 }
12487  else if (EQSI (tmp_tmpcond, 6)) {
12488   tmp_condres = NOTBI (CPU (h_nbit));
12489 }
12490  else if (EQSI (tmp_tmpcond, 7)) {
12491   tmp_condres = CPU (h_nbit);
12492 }
12493  else if (EQSI (tmp_tmpcond, 8)) {
12494   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12495 }
12496  else if (EQSI (tmp_tmpcond, 9)) {
12497   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12498 }
12499  else if (EQSI (tmp_tmpcond, 10)) {
12500   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12501 }
12502  else if (EQSI (tmp_tmpcond, 11)) {
12503   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12504 }
12505  else if (EQSI (tmp_tmpcond, 12)) {
12506   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12507 }
12508  else if (EQSI (tmp_tmpcond, 13)) {
12509   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12510 }
12511  else if (EQSI (tmp_tmpcond, 14)) {
12512   tmp_condres = 1;
12513 }
12514  else if (EQSI (tmp_tmpcond, 15)) {
12515   tmp_condres = CPU (h_pbit);
12516 }
12517 ; tmp_condres; });
12518 crisv32f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
12519 {
12520   {
12521     BI opval = 0;
12522     CPU (h_xbit) = opval;
12523     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12524   }
12525   {
12526     BI opval = 0;
12527     SET_H_INSN_PREFIXED_P (opval);
12528     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12529   }
12530 }
12531 if (tmp_truthval) {
12532 {
12533   {
12534     USI opval = FLD (i_o_pcrel);
12535     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12536     written |= (1 << 8);
12537     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12538   }
12539 }
12540 }
12541 }
12542
12543   abuf->written = written;
12544   SEM_BRANCH_FINI (vpc);
12545 #undef FLD
12546 }
12547   NEXT (vpc);
12548
12549   CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
12550 {
12551   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12552   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12553 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12554   int UNUSED written = 0;
12555   IADDR UNUSED pc = abuf->addr;
12556   SEM_BRANCH_INIT
12557   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12558
12559 {
12560 {
12561   {
12562     BI opval = 0;
12563     CPU (h_xbit) = opval;
12564     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12565   }
12566   {
12567     BI opval = 0;
12568     SET_H_INSN_PREFIXED_P (opval);
12569     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12570   }
12571 }
12572 {
12573   {
12574     USI opval = FLD (i_o_pcrel);
12575     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12576     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12577   }
12578 }
12579 }
12580
12581   SEM_BRANCH_FINI (vpc);
12582 #undef FLD
12583 }
12584   NEXT (vpc);
12585
12586   CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
12587 {
12588   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12589   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12590 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12591   int UNUSED written = 0;
12592   IADDR UNUSED pc = abuf->addr;
12593   SEM_BRANCH_INIT
12594   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12595
12596 {
12597   BI tmp_truthval;
12598   tmp_truthval = ({   SI tmp_tmpcond;
12599   BI tmp_condres;
12600   tmp_tmpcond = FLD (f_operand2);
12601 ; if (EQSI (tmp_tmpcond, 0)) {
12602   tmp_condres = NOTBI (CPU (h_cbit));
12603 }
12604  else if (EQSI (tmp_tmpcond, 1)) {
12605   tmp_condres = CPU (h_cbit);
12606 }
12607  else if (EQSI (tmp_tmpcond, 2)) {
12608   tmp_condres = NOTBI (CPU (h_zbit));
12609 }
12610  else if (EQSI (tmp_tmpcond, 3)) {
12611   tmp_condres = CPU (h_zbit);
12612 }
12613  else if (EQSI (tmp_tmpcond, 4)) {
12614   tmp_condres = NOTBI (CPU (h_vbit));
12615 }
12616  else if (EQSI (tmp_tmpcond, 5)) {
12617   tmp_condres = CPU (h_vbit);
12618 }
12619  else if (EQSI (tmp_tmpcond, 6)) {
12620   tmp_condres = NOTBI (CPU (h_nbit));
12621 }
12622  else if (EQSI (tmp_tmpcond, 7)) {
12623   tmp_condres = CPU (h_nbit);
12624 }
12625  else if (EQSI (tmp_tmpcond, 8)) {
12626   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12627 }
12628  else if (EQSI (tmp_tmpcond, 9)) {
12629   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12630 }
12631  else if (EQSI (tmp_tmpcond, 10)) {
12632   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12633 }
12634  else if (EQSI (tmp_tmpcond, 11)) {
12635   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12636 }
12637  else if (EQSI (tmp_tmpcond, 12)) {
12638   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12639 }
12640  else if (EQSI (tmp_tmpcond, 13)) {
12641   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12642 }
12643  else if (EQSI (tmp_tmpcond, 14)) {
12644   tmp_condres = 1;
12645 }
12646  else if (EQSI (tmp_tmpcond, 15)) {
12647   tmp_condres = CPU (h_pbit);
12648 }
12649 ; tmp_condres; });
12650 crisv32f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
12651 {
12652   {
12653     BI opval = 0;
12654     CPU (h_xbit) = opval;
12655     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12656   }
12657   {
12658     BI opval = 0;
12659     SET_H_INSN_PREFIXED_P (opval);
12660     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12661   }
12662 }
12663 if (tmp_truthval) {
12664 {
12665   {
12666     USI opval = FLD (i_o_word_pcrel);
12667     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12668     written |= (1 << 8);
12669     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12670   }
12671 }
12672 }
12673 }
12674
12675   abuf->written = written;
12676   SEM_BRANCH_FINI (vpc);
12677 #undef FLD
12678 }
12679   NEXT (vpc);
12680
12681   CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
12682 {
12683   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12684   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12685 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12686   int UNUSED written = 0;
12687   IADDR UNUSED pc = abuf->addr;
12688   SEM_BRANCH_INIT
12689   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12690
12691 {
12692 {
12693   {
12694     BI opval = 0;
12695     CPU (h_xbit) = opval;
12696     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12697   }
12698   {
12699     BI opval = 0;
12700     SET_H_INSN_PREFIXED_P (opval);
12701     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12702   }
12703 }
12704 {
12705   {
12706     USI opval = FLD (i_o_word_pcrel);
12707     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12708     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12709   }
12710 }
12711 }
12712
12713   SEM_BRANCH_FINI (vpc);
12714 #undef FLD
12715 }
12716   NEXT (vpc);
12717
12718   CASE (sem, INSN_JAS_R) : /* jas ${Rs},${Pd} */
12719 {
12720   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12721   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12722 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
12723   int UNUSED written = 0;
12724   IADDR UNUSED pc = abuf->addr;
12725   SEM_BRANCH_INIT
12726   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12727
12728 {
12729 {
12730   {
12731     BI opval = 0;
12732     CPU (h_xbit) = opval;
12733     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12734   }
12735   {
12736     BI opval = 0;
12737     SET_H_INSN_PREFIXED_P (opval);
12738     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12739   }
12740 }
12741 if (ANDIF (EQSI (FLD (f_operand1), 1), EQSI (FLD (f_operand2), 11))) {
12742 cris_flush_simulator_decode_cache (current_cpu, pc);
12743 }
12744 {
12745 {
12746   {
12747     SI opval = ADDSI (pc, 4);
12748     SET_H_SR (FLD (f_operand2), opval);
12749     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12750   }
12751   {
12752     USI opval = GET_H_GR (FLD (f_operand1));
12753     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12754     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12755   }
12756 }
12757 }
12758 }
12759
12760   SEM_BRANCH_FINI (vpc);
12761 #undef FLD
12762 }
12763   NEXT (vpc);
12764
12765   CASE (sem, INSN_JAS_C) : /* jas ${const32},${Pd} */
12766 {
12767   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12768   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12769 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
12770   int UNUSED written = 0;
12771   IADDR UNUSED pc = abuf->addr;
12772   SEM_BRANCH_INIT
12773   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12774
12775 {
12776 {
12777   {
12778     BI opval = 0;
12779     CPU (h_xbit) = opval;
12780     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12781   }
12782   {
12783     BI opval = 0;
12784     SET_H_INSN_PREFIXED_P (opval);
12785     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12786   }
12787 }
12788 {
12789 {
12790   {
12791     SI opval = ADDSI (pc, 8);
12792     SET_H_SR (FLD (f_operand2), opval);
12793     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12794   }
12795   {
12796     USI opval = FLD (f_indir_pc__dword);
12797     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12798     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12799   }
12800 }
12801 }
12802 }
12803
12804   SEM_BRANCH_FINI (vpc);
12805 #undef FLD
12806 }
12807   NEXT (vpc);
12808
12809   CASE (sem, INSN_JUMP_P) : /* jump ${Ps} */
12810 {
12811   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12812   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12813 #define FLD(f) abuf->fields.sfmt_mcp.f
12814   int UNUSED written = 0;
12815   IADDR UNUSED pc = abuf->addr;
12816   SEM_BRANCH_INIT
12817   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12818
12819 {
12820 {
12821   {
12822     BI opval = 0;
12823     CPU (h_xbit) = opval;
12824     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12825   }
12826   {
12827     BI opval = 0;
12828     SET_H_INSN_PREFIXED_P (opval);
12829     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12830   }
12831 }
12832 {
12833   {
12834     USI opval = GET_H_SR (FLD (f_operand2));
12835     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12836     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12837   }
12838 }
12839 }
12840
12841   SEM_BRANCH_FINI (vpc);
12842 #undef FLD
12843 }
12844   NEXT (vpc);
12845
12846   CASE (sem, INSN_BAS_C) : /* bas ${const32},${Pd} */
12847 {
12848   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12849   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12850 #define FLD(f) abuf->fields.sfmt_bas_c.f
12851   int UNUSED written = 0;
12852   IADDR UNUSED pc = abuf->addr;
12853   SEM_BRANCH_INIT
12854   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12855
12856 {
12857 {
12858   {
12859     BI opval = 0;
12860     CPU (h_xbit) = opval;
12861     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12862   }
12863   {
12864     BI opval = 0;
12865     SET_H_INSN_PREFIXED_P (opval);
12866     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12867   }
12868 }
12869 {
12870 {
12871   {
12872     SI opval = ADDSI (pc, 8);
12873     SET_H_SR (FLD (f_operand2), opval);
12874     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12875   }
12876   {
12877     USI opval = FLD (i_const32_pcrel);
12878     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12879     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12880   }
12881 }
12882 }
12883 }
12884
12885   SEM_BRANCH_FINI (vpc);
12886 #undef FLD
12887 }
12888   NEXT (vpc);
12889
12890   CASE (sem, INSN_JASC_R) : /* jasc ${Rs},${Pd} */
12891 {
12892   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12893   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12894 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
12895   int UNUSED written = 0;
12896   IADDR UNUSED pc = abuf->addr;
12897   SEM_BRANCH_INIT
12898   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12899
12900 {
12901 {
12902   {
12903     BI opval = 0;
12904     CPU (h_xbit) = opval;
12905     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12906   }
12907   {
12908     BI opval = 0;
12909     SET_H_INSN_PREFIXED_P (opval);
12910     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12911   }
12912 }
12913 {
12914 {
12915   {
12916     SI opval = ADDSI (pc, 8);
12917     SET_H_SR (FLD (f_operand2), opval);
12918     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12919   }
12920   {
12921     USI opval = GET_H_GR (FLD (f_operand1));
12922     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12923     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12924   }
12925 }
12926 }
12927 }
12928
12929   SEM_BRANCH_FINI (vpc);
12930 #undef FLD
12931 }
12932   NEXT (vpc);
12933
12934   CASE (sem, INSN_JASC_C) : /* jasc ${const32},${Pd} */
12935 {
12936   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12937   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12938 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
12939   int UNUSED written = 0;
12940   IADDR UNUSED pc = abuf->addr;
12941   SEM_BRANCH_INIT
12942   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12943
12944 {
12945 {
12946   {
12947     BI opval = 0;
12948     CPU (h_xbit) = opval;
12949     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12950   }
12951   {
12952     BI opval = 0;
12953     SET_H_INSN_PREFIXED_P (opval);
12954     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12955   }
12956 }
12957 {
12958 {
12959   {
12960     SI opval = ADDSI (pc, 12);
12961     SET_H_SR (FLD (f_operand2), opval);
12962     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12963   }
12964   {
12965     USI opval = FLD (f_indir_pc__dword);
12966     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12967     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12968   }
12969 }
12970 }
12971 }
12972
12973   SEM_BRANCH_FINI (vpc);
12974 #undef FLD
12975 }
12976   NEXT (vpc);
12977
12978   CASE (sem, INSN_BASC_C) : /* basc ${const32},${Pd} */
12979 {
12980   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12981   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12982 #define FLD(f) abuf->fields.sfmt_bas_c.f
12983   int UNUSED written = 0;
12984   IADDR UNUSED pc = abuf->addr;
12985   SEM_BRANCH_INIT
12986   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12987
12988 {
12989 {
12990   {
12991     BI opval = 0;
12992     CPU (h_xbit) = opval;
12993     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12994   }
12995   {
12996     BI opval = 0;
12997     SET_H_INSN_PREFIXED_P (opval);
12998     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12999   }
13000 }
13001 {
13002 {
13003   {
13004     SI opval = ADDSI (pc, 12);
13005     SET_H_SR (FLD (f_operand2), opval);
13006     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
13007   }
13008   {
13009     USI opval = FLD (i_const32_pcrel);
13010     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13011     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13012   }
13013 }
13014 }
13015 }
13016
13017   SEM_BRANCH_FINI (vpc);
13018 #undef FLD
13019 }
13020   NEXT (vpc);
13021
13022   CASE (sem, INSN_BREAK) : /* break $n */
13023 {
13024   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13025   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13026 #define FLD(f) abuf->fields.sfmt_break.f
13027   int UNUSED written = 0;
13028   IADDR UNUSED pc = abuf->addr;
13029   SEM_BRANCH_INIT
13030   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13031
13032 {
13033 {
13034   {
13035     BI opval = 0;
13036     CPU (h_xbit) = opval;
13037     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13038   }
13039   {
13040     BI opval = 0;
13041     SET_H_INSN_PREFIXED_P (opval);
13042     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13043   }
13044 }
13045   {
13046     USI opval = crisv32f_break_handler (current_cpu, FLD (f_u4), pc);
13047     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13048     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13049   }
13050 }
13051
13052   SEM_BRANCH_FINI (vpc);
13053 #undef FLD
13054 }
13055   NEXT (vpc);
13056
13057   CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
13058 {
13059   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13060   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13061 #define FLD(f) abuf->fields.sfmt_muls_b.f
13062   int UNUSED written = 0;
13063   IADDR UNUSED pc = abuf->addr;
13064   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13065
13066 {
13067   SI tmp_tmpopd;
13068   SI tmp_tmpops;
13069   SI tmp_newval;
13070   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
13071   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13072   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13073   {
13074     SI opval = tmp_newval;
13075     SET_H_GR (FLD (f_operand2), opval);
13076     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13077   }
13078 {
13079   {
13080     BI opval = LTSI (tmp_newval, 0);
13081     CPU (h_nbit) = opval;
13082     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13083   }
13084   {
13085     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13086     CPU (h_zbit) = opval;
13087     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13088   }
13089 SET_H_CBIT_MOVE (0);
13090 SET_H_VBIT_MOVE (0);
13091 {
13092   {
13093     BI opval = 0;
13094     CPU (h_xbit) = opval;
13095     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13096   }
13097   {
13098     BI opval = 0;
13099     SET_H_INSN_PREFIXED_P (opval);
13100     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13101   }
13102 }
13103 }
13104 }
13105
13106 #undef FLD
13107 }
13108   NEXT (vpc);
13109
13110   CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
13111 {
13112   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13113   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13114 #define FLD(f) abuf->fields.sfmt_muls_b.f
13115   int UNUSED written = 0;
13116   IADDR UNUSED pc = abuf->addr;
13117   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13118
13119 {
13120   SI tmp_tmpopd;
13121   SI tmp_tmpops;
13122   SI tmp_newval;
13123   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
13124   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13125   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13126   {
13127     SI opval = tmp_newval;
13128     SET_H_GR (FLD (f_operand2), opval);
13129     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13130   }
13131 {
13132   {
13133     BI opval = LTSI (tmp_newval, 0);
13134     CPU (h_nbit) = opval;
13135     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13136   }
13137   {
13138     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13139     CPU (h_zbit) = opval;
13140     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13141   }
13142 SET_H_CBIT_MOVE (0);
13143 SET_H_VBIT_MOVE (0);
13144 {
13145   {
13146     BI opval = 0;
13147     CPU (h_xbit) = opval;
13148     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13149   }
13150   {
13151     BI opval = 0;
13152     SET_H_INSN_PREFIXED_P (opval);
13153     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13154   }
13155 }
13156 }
13157 }
13158
13159 #undef FLD
13160 }
13161   NEXT (vpc);
13162
13163   CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
13164 {
13165   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13166   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13167 #define FLD(f) abuf->fields.sfmt_muls_b.f
13168   int UNUSED written = 0;
13169   IADDR UNUSED pc = abuf->addr;
13170   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13171
13172 {
13173   SI tmp_tmpopd;
13174   SI tmp_tmpops;
13175   SI tmp_newval;
13176   tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
13177   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13178   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13179   {
13180     SI opval = tmp_newval;
13181     SET_H_GR (FLD (f_operand2), opval);
13182     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13183   }
13184 {
13185   {
13186     BI opval = LTSI (tmp_newval, 0);
13187     CPU (h_nbit) = opval;
13188     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13189   }
13190   {
13191     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13192     CPU (h_zbit) = opval;
13193     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13194   }
13195 SET_H_CBIT_MOVE (0);
13196 SET_H_VBIT_MOVE (0);
13197 {
13198   {
13199     BI opval = 0;
13200     CPU (h_xbit) = opval;
13201     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13202   }
13203   {
13204     BI opval = 0;
13205     SET_H_INSN_PREFIXED_P (opval);
13206     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13207   }
13208 }
13209 }
13210 }
13211
13212 #undef FLD
13213 }
13214   NEXT (vpc);
13215
13216   CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
13217 {
13218   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13219   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13220 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13221   int UNUSED written = 0;
13222   IADDR UNUSED pc = abuf->addr;
13223   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13224
13225 {
13226   SI tmp_tmpopd;
13227   SI tmp_tmpops;
13228   SI tmp_newval;
13229   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
13230   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13231   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13232   {
13233     SI opval = tmp_newval;
13234     SET_H_GR (FLD (f_operand2), opval);
13235     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13236   }
13237 {
13238   {
13239     BI opval = LTSI (tmp_newval, 0);
13240     CPU (h_nbit) = opval;
13241     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13242   }
13243   {
13244     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13245     CPU (h_zbit) = opval;
13246     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13247   }
13248 SET_H_CBIT_MOVE (0);
13249 SET_H_VBIT_MOVE (0);
13250 {
13251   {
13252     BI opval = 0;
13253     CPU (h_xbit) = opval;
13254     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13255   }
13256   {
13257     BI opval = 0;
13258     SET_H_INSN_PREFIXED_P (opval);
13259     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13260   }
13261 }
13262 }
13263 }
13264
13265 #undef FLD
13266 }
13267   NEXT (vpc);
13268
13269   CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
13270 {
13271   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13272   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13273 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13274   int UNUSED written = 0;
13275   IADDR UNUSED pc = abuf->addr;
13276   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13277
13278 {
13279   SI tmp_tmpopd;
13280   SI tmp_tmpops;
13281   SI tmp_newval;
13282   tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
13283   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13284   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13285   {
13286     SI opval = tmp_newval;
13287     SET_H_GR (FLD (f_operand2), opval);
13288     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13289   }
13290 {
13291   {
13292     BI opval = LTSI (tmp_newval, 0);
13293     CPU (h_nbit) = opval;
13294     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13295   }
13296   {
13297     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13298     CPU (h_zbit) = opval;
13299     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13300   }
13301 SET_H_CBIT_MOVE (0);
13302 SET_H_VBIT_MOVE (0);
13303 {
13304   {
13305     BI opval = 0;
13306     CPU (h_xbit) = opval;
13307     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13308   }
13309   {
13310     BI opval = 0;
13311     SET_H_INSN_PREFIXED_P (opval);
13312     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13313   }
13314 }
13315 }
13316 }
13317
13318 #undef FLD
13319 }
13320   NEXT (vpc);
13321
13322   CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
13323 {
13324   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13325   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13326 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13327   int UNUSED written = 0;
13328   IADDR UNUSED pc = abuf->addr;
13329   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13330
13331 {
13332   SI tmp_tmpopd;
13333   SI tmp_tmpops;
13334   SI tmp_newval;
13335   tmp_tmpops = FLD (f_indir_pc__dword);
13336   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13337   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13338   {
13339     SI opval = tmp_newval;
13340     SET_H_GR (FLD (f_operand2), opval);
13341     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13342   }
13343 {
13344   {
13345     BI opval = LTSI (tmp_newval, 0);
13346     CPU (h_nbit) = opval;
13347     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13348   }
13349   {
13350     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13351     CPU (h_zbit) = opval;
13352     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13353   }
13354 SET_H_CBIT_MOVE (0);
13355 SET_H_VBIT_MOVE (0);
13356 {
13357   {
13358     BI opval = 0;
13359     CPU (h_xbit) = opval;
13360     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13361   }
13362   {
13363     BI opval = 0;
13364     SET_H_INSN_PREFIXED_P (opval);
13365     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13366   }
13367 }
13368 }
13369 }
13370
13371 #undef FLD
13372 }
13373   NEXT (vpc);
13374
13375   CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
13376 {
13377   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13378   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13379 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
13380   int UNUSED written = 0;
13381   IADDR UNUSED pc = abuf->addr;
13382   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13383
13384 {
13385   BI tmp_truthval;
13386   tmp_truthval = ({   SI tmp_tmpcond;
13387   BI tmp_condres;
13388   tmp_tmpcond = FLD (f_operand2);
13389 ; if (EQSI (tmp_tmpcond, 0)) {
13390   tmp_condres = NOTBI (CPU (h_cbit));
13391 }
13392  else if (EQSI (tmp_tmpcond, 1)) {
13393   tmp_condres = CPU (h_cbit);
13394 }
13395  else if (EQSI (tmp_tmpcond, 2)) {
13396   tmp_condres = NOTBI (CPU (h_zbit));
13397 }
13398  else if (EQSI (tmp_tmpcond, 3)) {
13399   tmp_condres = CPU (h_zbit);
13400 }
13401  else if (EQSI (tmp_tmpcond, 4)) {
13402   tmp_condres = NOTBI (CPU (h_vbit));
13403 }
13404  else if (EQSI (tmp_tmpcond, 5)) {
13405   tmp_condres = CPU (h_vbit);
13406 }
13407  else if (EQSI (tmp_tmpcond, 6)) {
13408   tmp_condres = NOTBI (CPU (h_nbit));
13409 }
13410  else if (EQSI (tmp_tmpcond, 7)) {
13411   tmp_condres = CPU (h_nbit);
13412 }
13413  else if (EQSI (tmp_tmpcond, 8)) {
13414   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
13415 }
13416  else if (EQSI (tmp_tmpcond, 9)) {
13417   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
13418 }
13419  else if (EQSI (tmp_tmpcond, 10)) {
13420   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
13421 }
13422  else if (EQSI (tmp_tmpcond, 11)) {
13423   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
13424 }
13425  else if (EQSI (tmp_tmpcond, 12)) {
13426   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
13427 }
13428  else if (EQSI (tmp_tmpcond, 13)) {
13429   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
13430 }
13431  else if (EQSI (tmp_tmpcond, 14)) {
13432   tmp_condres = 1;
13433 }
13434  else if (EQSI (tmp_tmpcond, 15)) {
13435   tmp_condres = CPU (h_pbit);
13436 }
13437 ; tmp_condres; });
13438   {
13439     SI opval = ZEXTBISI (tmp_truthval);
13440     SET_H_GR (FLD (f_operand1), opval);
13441     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13442   }
13443 {
13444   {
13445     BI opval = 0;
13446     CPU (h_xbit) = opval;
13447     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13448   }
13449   {
13450     BI opval = 0;
13451     SET_H_INSN_PREFIXED_P (opval);
13452     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13453   }
13454 }
13455 }
13456
13457 #undef FLD
13458 }
13459   NEXT (vpc);
13460
13461   CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
13462 {
13463   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13464   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13465 #define FLD(f) abuf->fields.sfmt_muls_b.f
13466   int UNUSED written = 0;
13467   IADDR UNUSED pc = abuf->addr;
13468   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13469
13470 {
13471   SI tmp_tmpd;
13472   SI tmp_tmp;
13473   tmp_tmp = GET_H_GR (FLD (f_operand1));
13474   tmp_tmpd = 0;
13475 {
13476 if (GESI (tmp_tmp, 0)) {
13477 {
13478   tmp_tmp = SLLSI (tmp_tmp, 1);
13479   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13480 }
13481 }
13482 if (GESI (tmp_tmp, 0)) {
13483 {
13484   tmp_tmp = SLLSI (tmp_tmp, 1);
13485   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13486 }
13487 }
13488 if (GESI (tmp_tmp, 0)) {
13489 {
13490   tmp_tmp = SLLSI (tmp_tmp, 1);
13491   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13492 }
13493 }
13494 if (GESI (tmp_tmp, 0)) {
13495 {
13496   tmp_tmp = SLLSI (tmp_tmp, 1);
13497   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13498 }
13499 }
13500 if (GESI (tmp_tmp, 0)) {
13501 {
13502   tmp_tmp = SLLSI (tmp_tmp, 1);
13503   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13504 }
13505 }
13506 if (GESI (tmp_tmp, 0)) {
13507 {
13508   tmp_tmp = SLLSI (tmp_tmp, 1);
13509   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13510 }
13511 }
13512 if (GESI (tmp_tmp, 0)) {
13513 {
13514   tmp_tmp = SLLSI (tmp_tmp, 1);
13515   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13516 }
13517 }
13518 if (GESI (tmp_tmp, 0)) {
13519 {
13520   tmp_tmp = SLLSI (tmp_tmp, 1);
13521   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13522 }
13523 }
13524 if (GESI (tmp_tmp, 0)) {
13525 {
13526   tmp_tmp = SLLSI (tmp_tmp, 1);
13527   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13528 }
13529 }
13530 if (GESI (tmp_tmp, 0)) {
13531 {
13532   tmp_tmp = SLLSI (tmp_tmp, 1);
13533   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13534 }
13535 }
13536 if (GESI (tmp_tmp, 0)) {
13537 {
13538   tmp_tmp = SLLSI (tmp_tmp, 1);
13539   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13540 }
13541 }
13542 if (GESI (tmp_tmp, 0)) {
13543 {
13544   tmp_tmp = SLLSI (tmp_tmp, 1);
13545   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13546 }
13547 }
13548 if (GESI (tmp_tmp, 0)) {
13549 {
13550   tmp_tmp = SLLSI (tmp_tmp, 1);
13551   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13552 }
13553 }
13554 if (GESI (tmp_tmp, 0)) {
13555 {
13556   tmp_tmp = SLLSI (tmp_tmp, 1);
13557   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13558 }
13559 }
13560 if (GESI (tmp_tmp, 0)) {
13561 {
13562   tmp_tmp = SLLSI (tmp_tmp, 1);
13563   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13564 }
13565 }
13566 if (GESI (tmp_tmp, 0)) {
13567 {
13568   tmp_tmp = SLLSI (tmp_tmp, 1);
13569   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13570 }
13571 }
13572 if (GESI (tmp_tmp, 0)) {
13573 {
13574   tmp_tmp = SLLSI (tmp_tmp, 1);
13575   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13576 }
13577 }
13578 if (GESI (tmp_tmp, 0)) {
13579 {
13580   tmp_tmp = SLLSI (tmp_tmp, 1);
13581   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13582 }
13583 }
13584 if (GESI (tmp_tmp, 0)) {
13585 {
13586   tmp_tmp = SLLSI (tmp_tmp, 1);
13587   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13588 }
13589 }
13590 if (GESI (tmp_tmp, 0)) {
13591 {
13592   tmp_tmp = SLLSI (tmp_tmp, 1);
13593   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13594 }
13595 }
13596 if (GESI (tmp_tmp, 0)) {
13597 {
13598   tmp_tmp = SLLSI (tmp_tmp, 1);
13599   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13600 }
13601 }
13602 if (GESI (tmp_tmp, 0)) {
13603 {
13604   tmp_tmp = SLLSI (tmp_tmp, 1);
13605   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13606 }
13607 }
13608 if (GESI (tmp_tmp, 0)) {
13609 {
13610   tmp_tmp = SLLSI (tmp_tmp, 1);
13611   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13612 }
13613 }
13614 if (GESI (tmp_tmp, 0)) {
13615 {
13616   tmp_tmp = SLLSI (tmp_tmp, 1);
13617   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13618 }
13619 }
13620 if (GESI (tmp_tmp, 0)) {
13621 {
13622   tmp_tmp = SLLSI (tmp_tmp, 1);
13623   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13624 }
13625 }
13626 if (GESI (tmp_tmp, 0)) {
13627 {
13628   tmp_tmp = SLLSI (tmp_tmp, 1);
13629   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13630 }
13631 }
13632 if (GESI (tmp_tmp, 0)) {
13633 {
13634   tmp_tmp = SLLSI (tmp_tmp, 1);
13635   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13636 }
13637 }
13638 if (GESI (tmp_tmp, 0)) {
13639 {
13640   tmp_tmp = SLLSI (tmp_tmp, 1);
13641   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13642 }
13643 }
13644 if (GESI (tmp_tmp, 0)) {
13645 {
13646   tmp_tmp = SLLSI (tmp_tmp, 1);
13647   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13648 }
13649 }
13650 if (GESI (tmp_tmp, 0)) {
13651 {
13652   tmp_tmp = SLLSI (tmp_tmp, 1);
13653   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13654 }
13655 }
13656 if (GESI (tmp_tmp, 0)) {
13657 {
13658   tmp_tmp = SLLSI (tmp_tmp, 1);
13659   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13660 }
13661 }
13662 if (GESI (tmp_tmp, 0)) {
13663 {
13664   tmp_tmp = SLLSI (tmp_tmp, 1);
13665   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13666 }
13667 }
13668 }
13669   {
13670     SI opval = tmp_tmpd;
13671     SET_H_GR (FLD (f_operand2), opval);
13672     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13673   }
13674 {
13675   {
13676     BI opval = LTSI (tmp_tmpd, 0);
13677     CPU (h_nbit) = opval;
13678     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13679   }
13680   {
13681     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13682     CPU (h_zbit) = opval;
13683     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13684   }
13685 SET_H_CBIT_MOVE (0);
13686 SET_H_VBIT_MOVE (0);
13687 {
13688   {
13689     BI opval = 0;
13690     CPU (h_xbit) = opval;
13691     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13692   }
13693   {
13694     BI opval = 0;
13695     SET_H_INSN_PREFIXED_P (opval);
13696     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13697   }
13698 }
13699 }
13700 }
13701
13702 #undef FLD
13703 }
13704   NEXT (vpc);
13705
13706   CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
13707 {
13708   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13709   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13710 #define FLD(f) abuf->fields.sfmt_addoq.f
13711   int UNUSED written = 0;
13712   IADDR UNUSED pc = abuf->addr;
13713   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13714
13715 {
13716   {
13717     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
13718     SET_H_PREFIXREG_V32 (opval);
13719     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13720   }
13721   {
13722     BI opval = 1;
13723     SET_H_INSN_PREFIXED_P (opval);
13724     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13725   }
13726 }
13727
13728 #undef FLD
13729 }
13730   NEXT (vpc);
13731
13732   CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
13733 {
13734   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13735   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13736 #define FLD(f) abuf->fields.sfmt_addc_m.f
13737   int UNUSED written = 0;
13738   IADDR UNUSED pc = abuf->addr;
13739   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13740
13741 {
13742   QI tmp_tmps;
13743   tmp_tmps = ({   SI tmp_addr;
13744   QI tmp_tmp_mem;
13745   BI tmp_postinc;
13746   tmp_postinc = FLD (f_memmode);
13747 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
13748 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13749 ; if (NEBI (tmp_postinc, 0)) {
13750 {
13751 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13752   tmp_addr = ADDSI (tmp_addr, 1);
13753 }
13754   {
13755     SI opval = tmp_addr;
13756     SET_H_GR (FLD (f_operand1), opval);
13757     written |= (1 << 6);
13758     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13759   }
13760 }
13761 }
13762 ; tmp_tmp_mem; });
13763   {
13764     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
13765     SET_H_PREFIXREG_V32 (opval);
13766     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13767   }
13768   {
13769     BI opval = 1;
13770     SET_H_INSN_PREFIXED_P (opval);
13771     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13772   }
13773 }
13774
13775   abuf->written = written;
13776 #undef FLD
13777 }
13778   NEXT (vpc);
13779
13780   CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
13781 {
13782   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13783   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13784 #define FLD(f) abuf->fields.sfmt_addc_m.f
13785   int UNUSED written = 0;
13786   IADDR UNUSED pc = abuf->addr;
13787   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13788
13789 {
13790   HI tmp_tmps;
13791   tmp_tmps = ({   SI tmp_addr;
13792   HI tmp_tmp_mem;
13793   BI tmp_postinc;
13794   tmp_postinc = FLD (f_memmode);
13795 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
13796 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
13797 ; if (NEBI (tmp_postinc, 0)) {
13798 {
13799 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13800   tmp_addr = ADDSI (tmp_addr, 2);
13801 }
13802   {
13803     SI opval = tmp_addr;
13804     SET_H_GR (FLD (f_operand1), opval);
13805     written |= (1 << 6);
13806     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13807   }
13808 }
13809 }
13810 ; tmp_tmp_mem; });
13811   {
13812     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
13813     SET_H_PREFIXREG_V32 (opval);
13814     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13815   }
13816   {
13817     BI opval = 1;
13818     SET_H_INSN_PREFIXED_P (opval);
13819     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13820   }
13821 }
13822
13823   abuf->written = written;
13824 #undef FLD
13825 }
13826   NEXT (vpc);
13827
13828   CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
13829 {
13830   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13831   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13832 #define FLD(f) abuf->fields.sfmt_addc_m.f
13833   int UNUSED written = 0;
13834   IADDR UNUSED pc = abuf->addr;
13835   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13836
13837 {
13838   SI tmp_tmps;
13839   tmp_tmps = ({   SI tmp_addr;
13840   SI tmp_tmp_mem;
13841   BI tmp_postinc;
13842   tmp_postinc = FLD (f_memmode);
13843 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
13844 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13845 ; if (NEBI (tmp_postinc, 0)) {
13846 {
13847 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13848   tmp_addr = ADDSI (tmp_addr, 4);
13849 }
13850   {
13851     SI opval = tmp_addr;
13852     SET_H_GR (FLD (f_operand1), opval);
13853     written |= (1 << 6);
13854     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13855   }
13856 }
13857 }
13858 ; tmp_tmp_mem; });
13859   {
13860     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
13861     SET_H_PREFIXREG_V32 (opval);
13862     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13863   }
13864   {
13865     BI opval = 1;
13866     SET_H_INSN_PREFIXED_P (opval);
13867     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13868   }
13869 }
13870
13871   abuf->written = written;
13872 #undef FLD
13873 }
13874   NEXT (vpc);
13875
13876   CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
13877 {
13878   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13879   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13880 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13881   int UNUSED written = 0;
13882   IADDR UNUSED pc = abuf->addr;
13883   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13884
13885 {
13886   {
13887     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
13888     SET_H_PREFIXREG_V32 (opval);
13889     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13890   }
13891   {
13892     BI opval = 1;
13893     SET_H_INSN_PREFIXED_P (opval);
13894     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13895   }
13896 }
13897
13898 #undef FLD
13899 }
13900   NEXT (vpc);
13901
13902   CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
13903 {
13904   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13905   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13906 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13907   int UNUSED written = 0;
13908   IADDR UNUSED pc = abuf->addr;
13909   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13910
13911 {
13912   {
13913     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
13914     SET_H_PREFIXREG_V32 (opval);
13915     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13916   }
13917   {
13918     BI opval = 1;
13919     SET_H_INSN_PREFIXED_P (opval);
13920     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13921   }
13922 }
13923
13924 #undef FLD
13925 }
13926   NEXT (vpc);
13927
13928   CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
13929 {
13930   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13931   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13932 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13933   int UNUSED written = 0;
13934   IADDR UNUSED pc = abuf->addr;
13935   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13936
13937 {
13938   {
13939     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
13940     SET_H_PREFIXREG_V32 (opval);
13941     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13942   }
13943   {
13944     BI opval = 1;
13945     SET_H_INSN_PREFIXED_P (opval);
13946     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13947   }
13948 }
13949
13950 #undef FLD
13951 }
13952   NEXT (vpc);
13953
13954   CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
13955 {
13956   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13957   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13958 #define FLD(f) abuf->fields.sfmt_muls_b.f
13959   int UNUSED written = 0;
13960   IADDR UNUSED pc = abuf->addr;
13961   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13962
13963 {
13964   {
13965     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
13966     SET_H_PREFIXREG_V32 (opval);
13967     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13968   }
13969   {
13970     BI opval = 1;
13971     SET_H_INSN_PREFIXED_P (opval);
13972     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13973   }
13974 }
13975
13976 #undef FLD
13977 }
13978   NEXT (vpc);
13979
13980   CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
13981 {
13982   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13983   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13984 #define FLD(f) abuf->fields.sfmt_muls_b.f
13985   int UNUSED written = 0;
13986   IADDR UNUSED pc = abuf->addr;
13987   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13988
13989 {
13990   {
13991     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
13992     SET_H_PREFIXREG_V32 (opval);
13993     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13994   }
13995   {
13996     BI opval = 1;
13997     SET_H_INSN_PREFIXED_P (opval);
13998     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13999   }
14000 }
14001
14002 #undef FLD
14003 }
14004   NEXT (vpc);
14005
14006   CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
14007 {
14008   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14009   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14010 #define FLD(f) abuf->fields.sfmt_muls_b.f
14011   int UNUSED written = 0;
14012   IADDR UNUSED pc = abuf->addr;
14013   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14014
14015 {
14016   {
14017     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
14018     SET_H_PREFIXREG_V32 (opval);
14019     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14020   }
14021   {
14022     BI opval = 1;
14023     SET_H_INSN_PREFIXED_P (opval);
14024     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14025   }
14026 }
14027
14028 #undef FLD
14029 }
14030   NEXT (vpc);
14031
14032   CASE (sem, INSN_FIDXI) : /* fidxi [$Rs] */
14033 {
14034   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14035   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14036 #define FLD(f) abuf->fields.sfmt_mcp.f
14037   int UNUSED written = 0;
14038   IADDR UNUSED pc = abuf->addr;
14039   SEM_BRANCH_INIT
14040   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14041
14042   {
14043     USI opval = crisv32f_fidxi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14044     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14045     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14046   }
14047
14048   SEM_BRANCH_FINI (vpc);
14049 #undef FLD
14050 }
14051   NEXT (vpc);
14052
14053   CASE (sem, INSN_FTAGI) : /* fidxi [$Rs] */
14054 {
14055   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14056   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14057 #define FLD(f) abuf->fields.sfmt_mcp.f
14058   int UNUSED written = 0;
14059   IADDR UNUSED pc = abuf->addr;
14060   SEM_BRANCH_INIT
14061   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14062
14063   {
14064     USI opval = crisv32f_ftagi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14065     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14066     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14067   }
14068
14069   SEM_BRANCH_FINI (vpc);
14070 #undef FLD
14071 }
14072   NEXT (vpc);
14073
14074   CASE (sem, INSN_FIDXD) : /* fidxd [$Rs] */
14075 {
14076   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14077   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14078 #define FLD(f) abuf->fields.sfmt_mcp.f
14079   int UNUSED written = 0;
14080   IADDR UNUSED pc = abuf->addr;
14081   SEM_BRANCH_INIT
14082   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14083
14084   {
14085     USI opval = crisv32f_fidxd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14086     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14087     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14088   }
14089
14090   SEM_BRANCH_FINI (vpc);
14091 #undef FLD
14092 }
14093   NEXT (vpc);
14094
14095   CASE (sem, INSN_FTAGD) : /* ftagd [$Rs] */
14096 {
14097   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14098   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14099 #define FLD(f) abuf->fields.sfmt_mcp.f
14100   int UNUSED written = 0;
14101   IADDR UNUSED pc = abuf->addr;
14102   SEM_BRANCH_INIT
14103   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14104
14105   {
14106     USI opval = crisv32f_ftagd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14107     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14108     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14109   }
14110
14111   SEM_BRANCH_FINI (vpc);
14112 #undef FLD
14113 }
14114   NEXT (vpc);
14115
14116
14117     }
14118   ENDSWITCH (sem) /* End of semantic switch.  */
14119
14120   /* At this point `vpc' contains the next insn to execute.  */
14121 }
14122
14123 #undef DEFINE_SWITCH
14124 #endif /* DEFINE_SWITCH */