elfcpp/mips.h

   1 // mips.h -- ELF definitions specific to EM_MIPS  -*- C++ -*-
   2
   3 // Copyright (C) 2012-2018 Free Software Foundation, Inc.
   4 // Written by Sasa Stankovic <sasa.stankovic@imgtec.com>
   5 //        and Aleksandar Simeonov <aleksandar.simeonov@rt-rk.com>.
   6
   7 // This file is part of elfcpp.
   8
   9 // This program is free software; you can redistribute it and/or
  10 // modify it under the terms of the GNU Library General Public License
  11 // as published by the Free Software Foundation; either version 2, or
  12 // (at your option) any later version.
  13
  14 // In addition to the permissions in the GNU Library General Public
  15 // License, the Free Software Foundation gives you unlimited
  16 // permission to link the compiled version of this file into
  17 // combinations with other programs, and to distribute those
  18 // combinations without any restriction coming from the use of this
  19 // file.  (The Library Public License restrictions do apply in other
  20 // respects; for example, they cover modification of the file, and
  21 /// distribution when not linked into a combined executable.)
  22
  23 // This program is distributed in the hope that it will be useful, but
  24 // WITHOUT ANY WARRANTY; without even the implied warranty of
  25 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  26 // Library General Public License for more details.
  27
  28 // You should have received a copy of the GNU Library General Public
  29 // License along with this program; if not, write to the Free Software
  30 // Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
  31 // 02110-1301, USA.
  32
  33 #ifndef ELFCPP_MIPS_H
  34 #define ELFCPP_MIPS_H
  35
  36 // Documentation for the MIPS relocs is taken from
  37 //   http://math-atlas.sourceforge.net/devel/assembly/mipsabi32.pdf
  38
  39 namespace elfcpp
  40 {
  41
  42 //
  43 // MIPS Relocation Codes
  44 //
  45
  46 enum
  47 {
  48   R_MIPS_NONE = 0,
  49   R_MIPS_16 = 1,
  50   R_MIPS_32 = 2,                   // In Elf 64: alias R_MIPS_ADD
  51   R_MIPS_REL32 = 3,                // In Elf 64: alias R_MIPS_REL
  52   R_MIPS_26 = 4,
  53   R_MIPS_HI16 = 5,
  54   R_MIPS_LO16 = 6,
  55   R_MIPS_GPREL16 = 7,              // In Elf 64: alias R_MIPS_GPREL
  56   R_MIPS_LITERAL = 8,
  57   R_MIPS_GOT16 = 9,                // In Elf 64: alias R_MIPS_GOT
  58   R_MIPS_PC16 = 10,
  59   R_MIPS_CALL16 = 11,              // In Elf 64: alias R_MIPS_CALL
  60   R_MIPS_GPREL32 = 12,
  61   R_MIPS_UNUSED1 = 13,
  62   R_MIPS_UNUSED2 = 14,
  63   R_MIPS_UNUSED3 = 15,
  64   R_MIPS_SHIFT5 = 16,
  65   R_MIPS_SHIFT6 = 17,
  66   R_MIPS_64 = 18,
  67   R_MIPS_GOT_DISP = 19,
  68   R_MIPS_GOT_PAGE = 20,
  69   R_MIPS_GOT_OFST = 21,
  70   R_MIPS_GOT_HI16 = 22,
  71   R_MIPS_GOT_LO16 = 23,
  72   R_MIPS_SUB = 24,
  73   R_MIPS_INSERT_A = 25,
  74   R_MIPS_INSERT_B = 26,
  75   R_MIPS_DELETE = 27,
  76   R_MIPS_HIGHER = 28,
  77   R_MIPS_HIGHEST = 29,
  78   R_MIPS_CALL_HI16 = 30,
  79   R_MIPS_CALL_LO16 = 31,
  80   R_MIPS_SCN_DISP = 32,
  81   R_MIPS_REL16 = 33,
  82   R_MIPS_ADD_IMMEDIATE = 34,
  83   R_MIPS_PJUMP = 35,
  84   R_MIPS_RELGOT = 36,
  85   R_MIPS_JALR = 37,
  86   // TLS relocations.
  87   R_MIPS_TLS_DTPMOD32 = 38,
  88   R_MIPS_TLS_DTPREL32 = 39,
  89   R_MIPS_TLS_DTPMOD64 = 40,
  90   R_MIPS_TLS_DTPREL64 = 41,
  91   R_MIPS_TLS_GD = 42,
  92   R_MIPS_TLS_LDM = 43,
  93   R_MIPS_TLS_DTPREL_HI16 = 44,
  94   R_MIPS_TLS_DTPREL_LO16 = 45,
  95   R_MIPS_TLS_GOTTPREL = 46,
  96   R_MIPS_TLS_TPREL32 = 47,
  97   R_MIPS_TLS_TPREL64 = 48,
  98   R_MIPS_TLS_TPREL_HI16 = 49,
  99   R_MIPS_TLS_TPREL_LO16 = 50,
 100   R_MIPS_GLOB_DAT = 51,
 101   R_MIPS_PC21_S2 = 60,
 102   R_MIPS_PC26_S2 = 61,
 103   R_MIPS_PC18_S3 = 62,
 104   R_MIPS_PC19_S2 = 63,
 105   R_MIPS_PCHI16 = 64,
 106   R_MIPS_PCLO16 = 65,
 107   // These relocs are used for the mips16.
 108   R_MIPS16_26 = 100,
 109   R_MIPS16_GPREL = 101,
 110   R_MIPS16_GOT16 = 102,
 111   R_MIPS16_CALL16 = 103,
 112   R_MIPS16_HI16 = 104,
 113   R_MIPS16_LO16 = 105,
 114   R_MIPS16_TLS_GD = 106,
 115   R_MIPS16_TLS_LDM = 107,
 116   R_MIPS16_TLS_DTPREL_HI16 = 108,
 117   R_MIPS16_TLS_DTPREL_LO16 = 109,
 118   R_MIPS16_TLS_GOTTPREL = 110,
 119   R_MIPS16_TLS_TPREL_HI16 = 111,
 120   R_MIPS16_TLS_TPREL_LO16 = 112,
 121
 122   R_MIPS_COPY = 126,
 123   R_MIPS_JUMP_SLOT = 127,
 124
 125   // These relocations are specific to microMIPS.
 126   R_MICROMIPS_26_S1 = 133,
 127   R_MICROMIPS_HI16 = 134,
 128   R_MICROMIPS_LO16 = 135,
 129   R_MICROMIPS_GPREL16 = 136,       // In Elf 64: alias R_MICROMIPS_GPREL
 130   R_MICROMIPS_LITERAL = 137,
 131   R_MICROMIPS_GOT16 = 138,         // In Elf 64: alias R_MICROMIPS_GOT
 132   R_MICROMIPS_PC7_S1 = 139,
 133   R_MICROMIPS_PC10_S1 = 140,
 134   R_MICROMIPS_PC16_S1 = 141,
 135   R_MICROMIPS_CALL16 = 142,        // In Elf 64: alias R_MICROMIPS_CALL
 136   R_MICROMIPS_GOT_DISP = 145,
 137   R_MICROMIPS_GOT_PAGE = 146,
 138   R_MICROMIPS_GOT_OFST = 147,
 139   R_MICROMIPS_GOT_HI16 = 148,
 140   R_MICROMIPS_GOT_LO16 = 149,
 141   R_MICROMIPS_SUB = 150,
 142   R_MICROMIPS_HIGHER = 151,
 143   R_MICROMIPS_HIGHEST = 152,
 144   R_MICROMIPS_CALL_HI16 = 153,
 145   R_MICROMIPS_CALL_LO16 = 154,
 146   R_MICROMIPS_SCN_DISP = 155,
 147   R_MICROMIPS_JALR = 156,
 148   R_MICROMIPS_HI0_LO16 = 157,
 149   // TLS relocations.
 150   R_MICROMIPS_TLS_GD = 162,
 151   R_MICROMIPS_TLS_LDM = 163,
 152   R_MICROMIPS_TLS_DTPREL_HI16 = 164,
 153   R_MICROMIPS_TLS_DTPREL_LO16 = 165,
 154   R_MICROMIPS_TLS_GOTTPREL = 166,
 155   R_MICROMIPS_TLS_TPREL_HI16 = 169,
 156   R_MICROMIPS_TLS_TPREL_LO16 = 170,
 157   // microMIPS GP- and PC-relative relocations.
 158   R_MICROMIPS_GPREL7_S2 = 172,
 159   R_MICROMIPS_PC23_S2 = 173,
 160
 161   // This was a GNU extension used by embedded-PIC.  It was co-opted by
 162   // mips-linux for exception-handling data.  GCC stopped using it in
 163   // May, 2004, then started using it again for compact unwind tables.
 164   R_MIPS_PC32 = 248,
 165   R_MIPS_EH = 249,
 166   // This relocation is used internally by gas.
 167   R_MIPS_GNU_REL16_S2 = 250,
 168   // These are GNU extensions to enable C++ vtable garbage collection.
 169   R_MIPS_GNU_VTINHERIT = 253,
 170   R_MIPS_GNU_VTENTRY = 254
 171 };
 172
 173 // Processor specific flags for the ELF header e_flags field.
 174 enum
 175 {
 176   // At least one .noreorder directive appears in the source.
 177   EF_MIPS_NOREORDER = 0x00000001,
 178   // File contains position independent code.
 179   EF_MIPS_PIC = 0x00000002,
 180   // Code in file uses the standard calling sequence for calling
 181   // position independent code.
 182   EF_MIPS_CPIC = 0x00000004,
 183   // ???  Unknown flag, set in IRIX 6's BSDdup2.o in libbsd.a.
 184   EF_MIPS_XGOT = 0x00000008,
 185   // Code in file uses UCODE (obsolete)
 186   EF_MIPS_UCODE = 0x00000010,
 187   // Code in file uses new ABI (-n32 on Irix 6).
 188   EF_MIPS_ABI2 = 0x00000020,
 189   // Process the .MIPS.options section first by ld
 190   EF_MIPS_OPTIONS_FIRST = 0x00000080,
 191   // Architectural Extensions used by this file
 192   EF_MIPS_ARCH_ASE = 0x0f000000,
 193   // Use MDMX multimedia extensions
 194   EF_MIPS_ARCH_ASE_MDMX = 0x08000000,
 195   // Use MIPS-16 ISA extensions
 196   EF_MIPS_ARCH_ASE_M16 = 0x04000000,
 197   // Use MICROMIPS ISA extensions.
 198   EF_MIPS_ARCH_ASE_MICROMIPS = 0x02000000,
 199   // Indicates code compiled for a 64-bit machine in 32-bit mode.
 200   // (regs are 32-bits wide.)
 201   EF_MIPS_32BITMODE = 0x00000100,
 202   // 32-bit machine but FP registers are 64 bit (-mfp64).
 203   EF_MIPS_FP64 = 0x00000200,
 204   /// Code in file uses the IEEE 754-2008 NaN encoding convention.
 205   EF_MIPS_NAN2008 = 0x00000400,
 206   // MIPS dynamic
 207   EF_MIPS_DYNAMIC = 0x40
 208 };
 209
 210 // Machine variant if we know it.  This field was invented at Cygnus,
 211 // but it is hoped that other vendors will adopt it.  If some standard
 212 // is developed, this code should be changed to follow it.
 213 enum
 214 {
 215   EF_MIPS_MACH = 0x00FF0000,
 216
 217 // Cygnus is choosing values between 80 and 9F;
 218 // 00 - 7F should be left for a future standard;
 219 // the rest are open.
 220
 221   E_MIPS_MACH_3900 = 0x00810000,
 222   E_MIPS_MACH_4010 = 0x00820000,
 223   E_MIPS_MACH_4100 = 0x00830000,
 224   E_MIPS_MACH_4650 = 0x00850000,
 225   E_MIPS_MACH_4120 = 0x00870000,
 226   E_MIPS_MACH_4111 = 0x00880000,
 227   E_MIPS_MACH_SB1 = 0x008a0000,
 228   E_MIPS_MACH_OCTEON = 0x008b0000,
 229   E_MIPS_MACH_XLR = 0x008c0000,
 230   E_MIPS_MACH_OCTEON2 = 0x008d0000,
 231   E_MIPS_MACH_OCTEON3 = 0x008e0000,
 232   E_MIPS_MACH_5400 = 0x00910000,
 233   E_MIPS_MACH_5900 = 0x00920000,
 234   E_MIPS_MACH_5500 = 0x00980000,
 235   E_MIPS_MACH_9000 = 0x00990000,
 236   E_MIPS_MACH_LS2E = 0x00A00000,
 237   E_MIPS_MACH_LS2F = 0x00A10000,
 238   E_MIPS_MACH_LS3A = 0x00A20000,
 239 };
 240
 241 // MIPS architecture
 242 enum
 243 {
 244   // Four bit MIPS architecture field.
 245   EF_MIPS_ARCH = 0xf0000000,
 246   // -mips1 code.
 247   E_MIPS_ARCH_1 = 0x00000000,
 248   // -mips2 code.
 249   E_MIPS_ARCH_2 = 0x10000000,
 250   // -mips3 code.
 251   E_MIPS_ARCH_3 = 0x20000000,
 252   // -mips4 code.
 253   E_MIPS_ARCH_4 = 0x30000000,
 254   // -mips5 code.
 255   E_MIPS_ARCH_5 = 0x40000000,
 256   // -mips32 code.
 257   E_MIPS_ARCH_32 = 0x50000000,
 258   // -mips64 code.
 259   E_MIPS_ARCH_64 = 0x60000000,
 260   // -mips32r2 code.
 261   E_MIPS_ARCH_32R2 = 0x70000000,
 262   // -mips64r2 code.
 263   E_MIPS_ARCH_64R2 = 0x80000000,
 264   // -mips32r6 code.
 265   E_MIPS_ARCH_32R6 = 0x90000000,
 266   // -mips64r6 code.
 267   E_MIPS_ARCH_64R6 = 0xa0000000,
 268 };
 269
 270 // Values for the xxx_size bytes of an ABI flags structure.
 271 enum
 272 {
 273   // No registers.
 274   AFL_REG_NONE = 0x00,
 275   // 32-bit registers.
 276   AFL_REG_32 = 0x01,
 277   // 64-bit registers.
 278   AFL_REG_64 = 0x02,
 279   // 128-bit registers.
 280   AFL_REG_128 = 0x03
 281 };
 282
 283 // Masks for the ases word of an ABI flags structure.
 284 enum
 285 {
 286   // DSP ASE.
 287   AFL_ASE_DSP = 0x00000001,
 288   // DSP R2 ASE.
 289   AFL_ASE_DSPR2 = 0x00000002,
 290   // Enhanced VA Scheme.
 291   AFL_ASE_EVA = 0x00000004,
 292   // MCU (MicroController) ASE.
 293   AFL_ASE_MCU = 0x00000008,
 294   // MDMX ASE.
 295   AFL_ASE_MDMX = 0x00000010,
 296   // MIPS-3D ASE.
 297   AFL_ASE_MIPS3D = 0x00000020,
 298   // MT ASE.
 299   AFL_ASE_MT  = 0x00000040,
 300   // SmartMIPS ASE.
 301   AFL_ASE_SMARTMIPS = 0x00000080,
 302   // VZ ASE.
 303   AFL_ASE_VIRT = 0x00000100,
 304   // MSA ASE.
 305   AFL_ASE_MSA = 0x00000200,
 306   // MIPS16 ASE.
 307   AFL_ASE_MIPS16 = 0x00000400,
 308   // MICROMIPS ASE.
 309   AFL_ASE_MICROMIPS = 0x00000800,
 310   // XPA ASE.
 311   AFL_ASE_XPA = 0x00001000
 312 };
 313
 314 // Values for the isa_ext word of an ABI flags structure.
 315 enum
 316 {
 317   // RMI Xlr instruction.
 318   AFL_EXT_XLR = 1,
 319   // Cavium Networks Octeon2.
 320   AFL_EXT_OCTEON2 = 2,
 321   // Cavium Networks OcteonP.
 322   AFL_EXT_OCTEONP = 3,
 323   // Loongson 3A.
 324   AFL_EXT_LOONGSON_3A = 4,
 325   // Cavium Networks Octeon.
 326   AFL_EXT_OCTEON = 5,
 327   // MIPS R5900 instruction.
 328   AFL_EXT_5900 = 6,
 329   // MIPS R4650 instruction.
 330   AFL_EXT_4650 = 7,
 331   // LSI R4010 instruction.
 332   AFL_EXT_4010 = 8,
 333   // NEC VR4100 instruction.
 334   AFL_EXT_4100 = 9,
 335   // Toshiba R3900 instruction.
 336   AFL_EXT_3900 = 10,
 337   // MIPS R10000 instruction.
 338   AFL_EXT_10000 = 11,
 339   // Broadcom SB-1 instruction.
 340   AFL_EXT_SB1 = 12,
 341   // NEC VR4111/VR4181 instruction.
 342   AFL_EXT_4111 = 13,
 343   // NEC VR4120 instruction.
 344   AFL_EXT_4120 = 14,
 345   // NEC VR5400 instruction.
 346   AFL_EXT_5400 = 15,
 347   // NEC VR5500 instruction.
 348   AFL_EXT_5500 = 16,
 349   // ST Microelectronics Loongson 2E.
 350   AFL_EXT_LOONGSON_2E = 17,
 351   // ST Microelectronics Loongson 2F.
 352   AFL_EXT_LOONGSON_2F = 18,
 353   // Cavium Networks Octeon3.
 354   AFL_EXT_OCTEON3 = 19
 355 };
 356
 357 // Masks for the flags1 word of an ABI flags structure.
 358 enum
 359 {
 360   // Uses odd single-precision registers.
 361   AFL_FLAGS1_ODDSPREG = 1
 362 };
 363
 364 // Object attribute tags.
 365 enum
 366 {
 367   // 0-3 are generic.
 368   // Floating-point ABI used by this object file.
 369   Tag_GNU_MIPS_ABI_FP = 4,
 370   // MSA ABI used by this object file.
 371   Tag_GNU_MIPS_ABI_MSA = 8
 372 };
 373
 374 // Object attribute values.
 375 enum
 376 {
 377   // Values defined for Tag_GNU_MIPS_ABI_FP.
 378   // Not tagged or not using any ABIs affected by the differences.
 379   Val_GNU_MIPS_ABI_FP_ANY = 0,
 380   // Using hard-float -mdouble-float.
 381   Val_GNU_MIPS_ABI_FP_DOUBLE = 1,
 382   // Using hard-float -msingle-float.
 383   Val_GNU_MIPS_ABI_FP_SINGLE = 2,
 384   // Using soft-float.
 385   Val_GNU_MIPS_ABI_FP_SOFT = 3,
 386   // Using -mips32r2 -mfp64.
 387   Val_GNU_MIPS_ABI_FP_OLD_64 = 4,
 388   // Using -mfpxx
 389   Val_GNU_MIPS_ABI_FP_XX = 5,
 390   // Using -mips32r2 -mfp64.
 391   Val_GNU_MIPS_ABI_FP_64 = 6,
 392   // Using -mips32r2 -mfp64 -mno-odd-spreg.
 393   Val_GNU_MIPS_ABI_FP_64A = 7,
 394   // This is reserved for backward-compatibility with an earlier
 395   // implementation of the MIPS NaN2008 functionality.
 396   Val_GNU_MIPS_ABI_FP_NAN2008 = 8,
 397
 398   // Values defined for Tag_GNU_MIPS_ABI_MSA.
 399   // Not tagged or not using any ABIs affected by the differences.
 400   Val_GNU_MIPS_ABI_MSA_ANY = 0,
 401   // Using 128-bit MSA.
 402   Val_GNU_MIPS_ABI_MSA_128 = 1
 403 };
 404
 405 enum
 406 {
 407   // Mask to extract ABI version, not really a flag value.
 408   EF_MIPS_ABI = 0x0000F000,
 409
 410   // The original o32 abi.
 411   E_MIPS_ABI_O32 = 0x00001000,
 412   // O32 extended to work on 64 bit architectures
 413   E_MIPS_ABI_O64 = 0x00002000,
 414   // EABI in 32 bit mode
 415   E_MIPS_ABI_EABI32 = 0x00003000,
 416   // EABI in 64 bit mode
 417   E_MIPS_ABI_EABI64 = 0x00004000,
 418 };
 419
 420 // Dynamic section MIPS flags
 421 enum
 422 {
 423   // None
 424   RHF_NONE = 0x00000000,
 425   // Use shortcut pointers
 426   RHF_QUICKSTART = 0x00000001,
 427   // Hash size not power of two
 428   RHF_NOTPOT = 0x00000002,
 429   // Ignore LD_LIBRARY_PATH
 430   RHF_NO_LIBRARY_REPLACEMENT = 0x00000004
 431 };
 432
 433 // Special values for the st_other field in the symbol table.
 434 enum
 435 {
 436   // Two topmost bits denote the MIPS ISA for .text symbols:
 437   // + 00 -- standard MIPS code,
 438   // + 10 -- microMIPS code,
 439   // + 11 -- MIPS16 code; requires the following two bits to be set too.
 440   // Note that one of the MIPS16 bits overlaps with STO_MIPS_PIC.
 441   STO_MIPS_ISA = 0xc0,
 442
 443   // The mask spanning the rest of MIPS psABI flags.  At most one is expected
 444   // to be set except for STO_MIPS16.
 445   STO_MIPS_FLAGS = ~(STO_MIPS_ISA | 0x3),
 446
 447   // The MIPS psABI was updated in 2008 with support for PLTs and copy
 448   // relocs.  There are therefore two types of nonzero SHN_UNDEF functions:
 449   // PLT entries and traditional MIPS lazy binding stubs.  We mark the former
 450   // with STO_MIPS_PLT to distinguish them from the latter.
 451   STO_MIPS_PLT = 0x8,
 452
 453   // This value is used to mark PIC functions in an object that mixes
 454   // PIC and non-PIC.  Note that this bit overlaps with STO_MIPS16,
 455   // although MIPS16 symbols are never considered to be MIPS_PIC.
 456   STO_MIPS_PIC = 0x20,
 457
 458   // This value is used for a mips16 .text symbol.
 459   STO_MIPS16 = 0xf0,
 460
 461   // This value is used for a microMIPS .text symbol.  To distinguish from
 462   // STO_MIPS16, we set top two bits to be 10 to denote STO_MICROMIPS.  The
 463   // mask is STO_MIPS_ISA.
 464   STO_MICROMIPS  = 0x80
 465 };
 466
 467 // Values for base offsets for thread-local storage
 468 enum
 469 {
 470   TP_OFFSET = 0x7000,
 471   DTP_OFFSET = 0x8000
 472 };
 473
 474
 475 bool
 476 elf_st_is_mips16(unsigned char st_other)
 477 { return (st_other & elfcpp::STO_MIPS16) == elfcpp::STO_MIPS16; }
 478
 479 bool
 480 elf_st_is_micromips(unsigned char st_other)
 481 { return (st_other & elfcpp::STO_MIPS_ISA) == elfcpp::STO_MICROMIPS; }
 482
 483 // Whether the ABI is N32.
 484 bool
 485 abi_n32(elfcpp::Elf_Word e_flags)
 486 { return (e_flags & elfcpp::EF_MIPS_ABI2) != 0; }
 487
 488 // Whether the ISA is R6.
 489 bool
 490 r6_isa(elfcpp::Elf_Word e_flags)
 491 {
 492   return ((e_flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_32R6)
 493            || ((e_flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_64R6);
 494 }
 495
 496 // Whether the file has microMIPS code.
 497 bool
 498 is_micromips(elfcpp::Elf_Word e_flags)
 499 { return (e_flags & elfcpp::EF_MIPS_ARCH_ASE_MICROMIPS) != 0; }
 500
 501 // Values which may appear in the kind field of an Elf_Options structure.
 502 enum
 503 {
 504   // Undefined.
 505   ODK_NULL = 0,
 506   // Register usage and GP value.
 507   ODK_REGINFO = 1,
 508   // Exception processing information.
 509   ODK_EXCEPTIONS = 2,
 510   // Section padding information.
 511   ODK_PAD = 3,
 512   // Hardware workarounds performed.
 513   ODK_HWPATCH = 4,
 514   // Fill value used by the linker.
 515   ODK_FILL = 5,
 516   // Reserved space for desktop tools.
 517   ODK_TAGS = 6,
 518   // Hardware workarounds, AND bits when merging.
 519   ODK_HWAND = 7,
 520   // Hardware workarounds, OR bits when merging.
 521   ODK_HWOR = 8,
 522   // GP group to use for text/data sections.
 523   ODK_GP_GROUP = 9,
 524   // ID information.
 525   ODK_IDENT = 10
 526 };
 527
 528 } // End namespace elfcpp.
 529
 530 #endif // !defined(ELFCPP_MIPS_H)