include/sim/sim-sh.h

   1 /* This file defines the interface between the sh simulator and gdb.
   2    Copyright (C) 2000-2023 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #if !defined (SIM_SH_H)
  20 #define SIM_SH_H
  21
  22 /* The simulator makes use of the following register information. */
  23
  24 enum
  25 {
  26   SIM_SH_R0_REGNUM = 0,
  27   SIM_SH_R1_REGNUM,
  28   SIM_SH_R2_REGNUM,
  29   SIM_SH_R3_REGNUM,
  30   SIM_SH_R4_REGNUM,
  31   SIM_SH_R5_REGNUM,
  32   SIM_SH_R6_REGNUM,
  33   SIM_SH_R7_REGNUM,
  34   SIM_SH_R8_REGNUM,
  35   SIM_SH_R9_REGNUM,
  36   SIM_SH_R10_REGNUM,
  37   SIM_SH_R11_REGNUM,
  38   SIM_SH_R12_REGNUM,
  39   SIM_SH_R13_REGNUM,
  40   SIM_SH_R14_REGNUM,
  41   SIM_SH_R15_REGNUM,
  42   SIM_SH_PC_REGNUM,
  43   SIM_SH_PR_REGNUM,
  44   SIM_SH_GBR_REGNUM,
  45   SIM_SH_VBR_REGNUM,
  46   SIM_SH_MACH_REGNUM,
  47   SIM_SH_MACL_REGNUM,
  48   SIM_SH_SR_REGNUM,
  49   SIM_SH_FPUL_REGNUM,
  50   SIM_SH_FPSCR_REGNUM,
  51   SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */
  52   SIM_SH_FR1_REGNUM,
  53   SIM_SH_FR2_REGNUM,
  54   SIM_SH_FR3_REGNUM,
  55   SIM_SH_FR4_REGNUM,
  56   SIM_SH_FR5_REGNUM,
  57   SIM_SH_FR6_REGNUM,
  58   SIM_SH_FR7_REGNUM,
  59   SIM_SH_FR8_REGNUM,
  60   SIM_SH_FR9_REGNUM,
  61   SIM_SH_FR10_REGNUM,
  62   SIM_SH_FR11_REGNUM,
  63   SIM_SH_FR12_REGNUM,
  64   SIM_SH_FR13_REGNUM,
  65   SIM_SH_FR14_REGNUM,
  66   SIM_SH_FR15_REGNUM,
  67   SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */
  68   SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */
  69   SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */
  70   SIM_SH_R1_BANK0_REGNUM,
  71   SIM_SH_R2_BANK0_REGNUM,
  72   SIM_SH_R3_BANK0_REGNUM,
  73   SIM_SH_R4_BANK0_REGNUM,
  74   SIM_SH_R5_BANK0_REGNUM,
  75   SIM_SH_R6_BANK0_REGNUM,
  76   SIM_SH_R7_BANK0_REGNUM,
  77   SIM_SH_R0_BANK1_REGNUM,
  78   SIM_SH_R1_BANK1_REGNUM,
  79   SIM_SH_R2_BANK1_REGNUM,
  80   SIM_SH_R3_BANK1_REGNUM,
  81   SIM_SH_R4_BANK1_REGNUM,
  82   SIM_SH_R5_BANK1_REGNUM,
  83   SIM_SH_R6_BANK1_REGNUM,
  84   SIM_SH_R7_BANK1_REGNUM,
  85   SIM_SH_XF0_REGNUM,
  86   SIM_SH_XF1_REGNUM,
  87   SIM_SH_XF2_REGNUM,
  88   SIM_SH_XF3_REGNUM,
  89   SIM_SH_XF4_REGNUM,
  90   SIM_SH_XF5_REGNUM,
  91   SIM_SH_XF6_REGNUM,
  92   SIM_SH_XF7_REGNUM,
  93   SIM_SH_XF8_REGNUM,
  94   SIM_SH_XF9_REGNUM,
  95   SIM_SH_XF10_REGNUM,
  96   SIM_SH_XF11_REGNUM,
  97   SIM_SH_XF12_REGNUM,
  98   SIM_SH_XF13_REGNUM,
  99   SIM_SH_XF14_REGNUM,
 100   SIM_SH_XF15_REGNUM,
 101   SIM_SH_SGR_REGNUM,
 102   SIM_SH_DBR_REGNUM,
 103   SIM_SH4_NUM_REGS, /* 77 */
 104
 105   /* sh[3]-dsp */
 106   SIM_SH_DSR_REGNUM,
 107   SIM_SH_A0G_REGNUM,
 108   SIM_SH_A0_REGNUM,
 109   SIM_SH_A1G_REGNUM,
 110   SIM_SH_A1_REGNUM,
 111   SIM_SH_M0_REGNUM,
 112   SIM_SH_M1_REGNUM,
 113   SIM_SH_X0_REGNUM,
 114   SIM_SH_X1_REGNUM,
 115   SIM_SH_Y0_REGNUM,
 116   SIM_SH_Y1_REGNUM,
 117   SIM_SH_MOD_REGNUM,
 118   SIM_SH_RS_REGNUM,
 119   SIM_SH_RE_REGNUM,
 120   SIM_SH_R0_BANK_REGNUM,
 121   SIM_SH_R1_BANK_REGNUM,
 122   SIM_SH_R2_BANK_REGNUM,
 123   SIM_SH_R3_BANK_REGNUM,
 124   SIM_SH_R4_BANK_REGNUM,
 125   SIM_SH_R5_BANK_REGNUM,
 126   SIM_SH_R6_BANK_REGNUM,
 127   SIM_SH_R7_BANK_REGNUM,
 128   /* 109..127: room for expansion.  */
 129   SIM_SH_TBR_REGNUM,
 130   SIM_SH_IBNR_REGNUM,
 131   SIM_SH_IBCR_REGNUM,
 132   SIM_SH_BANK_REGNUM,
 133   SIM_SH_BANK_MACL_REGNUM,
 134   SIM_SH_BANK_GBR_REGNUM,
 135   SIM_SH_BANK_PR_REGNUM,
 136   SIM_SH_BANK_IVN_REGNUM,
 137   SIM_SH_BANK_MACH_REGNUM
 138 };
 139
 140 enum
 141 {
 142   SIM_SH64_R0_REGNUM = 0,
 143   SIM_SH64_SP_REGNUM = 15,
 144   SIM_SH64_PC_REGNUM = 64,
 145   SIM_SH64_SR_REGNUM = 65,
 146   SIM_SH64_SSR_REGNUM = 66,
 147   SIM_SH64_SPC_REGNUM = 67,
 148   SIM_SH64_TR0_REGNUM = 68,
 149   SIM_SH64_FPCSR_REGNUM = 76,
 150   SIM_SH64_FR0_REGNUM = 77
 151 };
 152
 153 enum
 154 {
 155   SIM_SH64_NR_REGS = 141,  /* total number of architectural registers */
 156   SIM_SH64_NR_R_REGS = 64, /* number of general registers */
 157   SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
 158   SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */
 159 };
 160
 161 #endif