opcodes/iq2000-dis.c

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* Disassembler interface for targets using CGEN. -*- C -*-
   3    CGEN: Cpu tools GENerator
   4
   5    THIS FILE IS MACHINE GENERATED WITH CGEN.
   6    - the resultant file is machine generated, cgen-dis.in isn't
   7
   8    Copyright (C) 1996-2021 Free Software Foundation, Inc.
   9
  10    This file is part of libopcodes.
  11
  12    This library is free software; you can redistribute it and/or modify
  13    it under the terms of the GNU General Public License as published by
  14    the Free Software Foundation; either version 3, or (at your option)
  15    any later version.
  16
  17    It is distributed in the hope that it will be useful, but WITHOUT
  18    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  19    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  20    License for more details.
  21
  22    You should have received a copy of the GNU General Public License
  23    along with this program; if not, write to the Free Software Foundation, Inc.,
  24    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  25
  26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  27    Keep that in mind.  */
  28
  29 #include "sysdep.h"
  30 #include <stdio.h>
  31 #include "ansidecl.h"
  32 #include "disassemble.h"
  33 #include "bfd.h"
  34 #include "symcat.h"
  35 #include "libiberty.h"
  36 #include "iq2000-desc.h"
  37 #include "iq2000-opc.h"
  38 #include "opintl.h"
  39
  40 /* Default text to print if an instruction isn't recognized.  */
  41 #define UNKNOWN_INSN_MSG _("*unknown*")
  42
  43 static void print_normal
  44   (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
  45 static void print_address
  46   (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
  47 static void print_keyword
  48   (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
  49 static void print_insn_normal
  50   (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
  51 static int print_insn
  52   (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
  53 static int default_print_insn
  54   (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
  55 static int read_insn
  56   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
  57    unsigned long *);
  58 \f
  59 /* -- disassembler routines inserted here.  */
  60
  61
  62 void iq2000_cgen_print_operand
  63   (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
  64
  65 /* Main entry point for printing operands.
  66    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
  67    of dis-asm.h on cgen.h.
  68
  69    This function is basically just a big switch statement.  Earlier versions
  70    used tables to look up the function to use, but
  71    - if the table contains both assembler and disassembler functions then
  72      the disassembler contains much of the assembler and vice-versa,
  73    - there's a lot of inlining possibilities as things grow,
  74    - using a switch statement avoids the function call overhead.
  75
  76    This function could be moved into `print_insn_normal', but keeping it
  77    separate makes clear the interface between `print_insn_normal' and each of
  78    the handlers.  */
  79
  80 void
  81 iq2000_cgen_print_operand (CGEN_CPU_DESC cd,
  82                            int opindex,
  83                            void * xinfo,
  84                            CGEN_FIELDS *fields,
  85                            void const *attrs ATTRIBUTE_UNUSED,
  86                            bfd_vma pc,
  87                            int length)
  88 {
  89   disassemble_info *info = (disassemble_info *) xinfo;
  90
  91   switch (opindex)
  92     {
  93     case IQ2000_OPERAND__INDEX :
  94       print_normal (cd, info, fields->f_index, 0, pc, length);
  95       break;
  96     case IQ2000_OPERAND_BASE :
  97       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
  98       break;
  99     case IQ2000_OPERAND_BASEOFF :
 100       print_address (cd, info, fields->f_imm, 0, pc, length);
 101       break;
 102     case IQ2000_OPERAND_BITNUM :
 103       print_normal (cd, info, fields->f_rt, 0, pc, length);
 104       break;
 105     case IQ2000_OPERAND_BYTECOUNT :
 106       print_normal (cd, info, fields->f_bytecount, 0, pc, length);
 107       break;
 108     case IQ2000_OPERAND_CAM_Y :
 109       print_normal (cd, info, fields->f_cam_y, 0, pc, length);
 110       break;
 111     case IQ2000_OPERAND_CAM_Z :
 112       print_normal (cd, info, fields->f_cam_z, 0, pc, length);
 113       break;
 114     case IQ2000_OPERAND_CM_3FUNC :
 115       print_normal (cd, info, fields->f_cm_3func, 0, pc, length);
 116       break;
 117     case IQ2000_OPERAND_CM_3Z :
 118       print_normal (cd, info, fields->f_cm_3z, 0, pc, length);
 119       break;
 120     case IQ2000_OPERAND_CM_4FUNC :
 121       print_normal (cd, info, fields->f_cm_4func, 0, pc, length);
 122       break;
 123     case IQ2000_OPERAND_CM_4Z :
 124       print_normal (cd, info, fields->f_cm_4z, 0, pc, length);
 125       break;
 126     case IQ2000_OPERAND_COUNT :
 127       print_normal (cd, info, fields->f_count, 0, pc, length);
 128       break;
 129     case IQ2000_OPERAND_EXECODE :
 130       print_normal (cd, info, fields->f_excode, 0, pc, length);
 131       break;
 132     case IQ2000_OPERAND_HI16 :
 133       print_normal (cd, info, fields->f_imm, 0, pc, length);
 134       break;
 135     case IQ2000_OPERAND_IMM :
 136       print_normal (cd, info, fields->f_imm, 0, pc, length);
 137       break;
 138     case IQ2000_OPERAND_JMPTARG :
 139       print_address (cd, info, fields->f_jtarg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 140       break;
 141     case IQ2000_OPERAND_JMPTARGQ10 :
 142       print_address (cd, info, fields->f_jtargq10, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 143       break;
 144     case IQ2000_OPERAND_LO16 :
 145       print_normal (cd, info, fields->f_imm, 0, pc, length);
 146       break;
 147     case IQ2000_OPERAND_MASK :
 148       print_normal (cd, info, fields->f_mask, 0, pc, length);
 149       break;
 150     case IQ2000_OPERAND_MASKL :
 151       print_normal (cd, info, fields->f_maskl, 0, pc, length);
 152       break;
 153     case IQ2000_OPERAND_MASKQ10 :
 154       print_normal (cd, info, fields->f_maskq10, 0, pc, length);
 155       break;
 156     case IQ2000_OPERAND_MASKR :
 157       print_normal (cd, info, fields->f_rs, 0, pc, length);
 158       break;
 159     case IQ2000_OPERAND_MLO16 :
 160       print_normal (cd, info, fields->f_imm, 0, pc, length);
 161       break;
 162     case IQ2000_OPERAND_OFFSET :
 163       print_address (cd, info, fields->f_offset, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 164       break;
 165     case IQ2000_OPERAND_RD :
 166       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd, 0);
 167       break;
 168     case IQ2000_OPERAND_RD_RS :
 169       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
 170       break;
 171     case IQ2000_OPERAND_RD_RT :
 172       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rt, 0|(1<<CGEN_OPERAND_VIRTUAL));
 173       break;
 174     case IQ2000_OPERAND_RS :
 175       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
 176       break;
 177     case IQ2000_OPERAND_RT :
 178       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0);
 179       break;
 180     case IQ2000_OPERAND_RT_RS :
 181       print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
 182       break;
 183     case IQ2000_OPERAND_SHAMT :
 184       print_normal (cd, info, fields->f_shamt, 0, pc, length);
 185       break;
 186
 187     default :
 188       /* xgettext:c-format */
 189       opcodes_error_handler
 190         (_("internal error: unrecognized field %d while printing insn"),
 191          opindex);
 192       abort ();
 193   }
 194 }
 195
 196 cgen_print_fn * const iq2000_cgen_print_handlers[] =
 197 {
 198   print_insn_normal,
 199 };
 200
 201
 202 void
 203 iq2000_cgen_init_dis (CGEN_CPU_DESC cd)
 204 {
 205   iq2000_cgen_init_opcode_table (cd);
 206   iq2000_cgen_init_ibld_table (cd);
 207   cd->print_handlers = & iq2000_cgen_print_handlers[0];
 208   cd->print_operand = iq2000_cgen_print_operand;
 209 }
 210
 211 \f
 212 /* Default print handler.  */
 213
 214 static void
 215 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 216               void *dis_info,
 217               long value,
 218               unsigned int attrs,
 219               bfd_vma pc ATTRIBUTE_UNUSED,
 220               int length ATTRIBUTE_UNUSED)
 221 {
 222   disassemble_info *info = (disassemble_info *) dis_info;
 223
 224   /* Print the operand as directed by the attributes.  */
 225   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 226     ; /* nothing to do */
 227   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 228     (*info->fprintf_func) (info->stream, "%ld", value);
 229   else
 230     (*info->fprintf_func) (info->stream, "0x%lx", value);
 231 }
 232
 233 /* Default address handler.  */
 234
 235 static void
 236 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 237                void *dis_info,
 238                bfd_vma value,
 239                unsigned int attrs,
 240                bfd_vma pc ATTRIBUTE_UNUSED,
 241                int length ATTRIBUTE_UNUSED)
 242 {
 243   disassemble_info *info = (disassemble_info *) dis_info;
 244
 245   /* Print the operand as directed by the attributes.  */
 246   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 247     ; /* Nothing to do.  */
 248   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 249     (*info->print_address_func) (value, info);
 250   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 251     (*info->print_address_func) (value, info);
 252   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 253     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 254   else
 255     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 256 }
 257
 258 /* Keyword print handler.  */
 259
 260 static void
 261 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 262                void *dis_info,
 263                CGEN_KEYWORD *keyword_table,
 264                long value,
 265                unsigned int attrs ATTRIBUTE_UNUSED)
 266 {
 267   disassemble_info *info = (disassemble_info *) dis_info;
 268   const CGEN_KEYWORD_ENTRY *ke;
 269
 270   ke = cgen_keyword_lookup_value (keyword_table, value);
 271   if (ke != NULL)
 272     (*info->fprintf_func) (info->stream, "%s", ke->name);
 273   else
 274     (*info->fprintf_func) (info->stream, "???");
 275 }
 276 \f
 277 /* Default insn printer.
 278
 279    DIS_INFO is defined as `void *' so the disassembler needn't know anything
 280    about disassemble_info.  */
 281
 282 static void
 283 print_insn_normal (CGEN_CPU_DESC cd,
 284                    void *dis_info,
 285                    const CGEN_INSN *insn,
 286                    CGEN_FIELDS *fields,
 287                    bfd_vma pc,
 288                    int length)
 289 {
 290   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 291   disassemble_info *info = (disassemble_info *) dis_info;
 292   const CGEN_SYNTAX_CHAR_TYPE *syn;
 293
 294   CGEN_INIT_PRINT (cd);
 295
 296   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 297     {
 298       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 299         {
 300           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 301           continue;
 302         }
 303       if (CGEN_SYNTAX_CHAR_P (*syn))
 304         {
 305           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 306           continue;
 307         }
 308
 309       /* We have an operand.  */
 310       iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 311                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 312     }
 313 }
 314 \f
 315 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 316    the extract info.
 317    Returns 0 if all is well, non-zero otherwise.  */
 318
 319 static int
 320 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 321            bfd_vma pc,
 322            disassemble_info *info,
 323            bfd_byte *buf,
 324            int buflen,
 325            CGEN_EXTRACT_INFO *ex_info,
 326            unsigned long *insn_value)
 327 {
 328   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 329
 330   if (status != 0)
 331     {
 332       (*info->memory_error_func) (status, pc, info);
 333       return -1;
 334     }
 335
 336   ex_info->dis_info = info;
 337   ex_info->valid = (1 << buflen) - 1;
 338   ex_info->insn_bytes = buf;
 339
 340   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 341   return 0;
 342 }
 343
 344 /* Utility to print an insn.
 345    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 346    The result is the size of the insn in bytes or zero for an unknown insn
 347    or -1 if an error occurs fetching data (memory_error_func will have
 348    been called).  */
 349
 350 static int
 351 print_insn (CGEN_CPU_DESC cd,
 352             bfd_vma pc,
 353             disassemble_info *info,
 354             bfd_byte *buf,
 355             unsigned int buflen)
 356 {
 357   CGEN_INSN_INT insn_value;
 358   const CGEN_INSN_LIST *insn_list;
 359   CGEN_EXTRACT_INFO ex_info;
 360   int basesize;
 361
 362   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 363   basesize = cd->base_insn_bitsize < buflen * 8 ?
 364                                      cd->base_insn_bitsize : buflen * 8;
 365   insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
 366
 367
 368   /* Fill in ex_info fields like read_insn would.  Don't actually call
 369      read_insn, since the incoming buffer is already read (and possibly
 370      modified a la m32r).  */
 371   ex_info.valid = (1 << buflen) - 1;
 372   ex_info.dis_info = info;
 373   ex_info.insn_bytes = buf;
 374
 375   /* The instructions are stored in hash lists.
 376      Pick the first one and keep trying until we find the right one.  */
 377
 378   insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
 379   while (insn_list != NULL)
 380     {
 381       const CGEN_INSN *insn = insn_list->insn;
 382       CGEN_FIELDS fields;
 383       int length;
 384       unsigned long insn_value_cropped;
 385
 386 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 387       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 388       /* Supported by this cpu?  */
 389       if (! iq2000_cgen_insn_supported (cd, insn))
 390         {
 391           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 392           continue;
 393         }
 394 #endif
 395
 396       /* Basic bit mask must be correct.  */
 397       /* ??? May wish to allow target to defer this check until the extract
 398          handler.  */
 399
 400       /* Base size may exceed this instruction's size.  Extract the
 401          relevant part from the buffer. */
 402       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 403           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 404         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 405                                            info->endian == BFD_ENDIAN_BIG);
 406       else
 407         insn_value_cropped = insn_value;
 408
 409       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 410           == CGEN_INSN_BASE_VALUE (insn))
 411         {
 412           /* Printing is handled in two passes.  The first pass parses the
 413              machine insn and extracts the fields.  The second pass prints
 414              them.  */
 415
 416           /* Make sure the entire insn is loaded into insn_value, if it
 417              can fit.  */
 418           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 419               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 420             {
 421               unsigned long full_insn_value;
 422               int rc = read_insn (cd, pc, info, buf,
 423                                   CGEN_INSN_BITSIZE (insn) / 8,
 424                                   & ex_info, & full_insn_value);
 425               if (rc != 0)
 426                 return rc;
 427               length = CGEN_EXTRACT_FN (cd, insn)
 428                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 429             }
 430           else
 431             length = CGEN_EXTRACT_FN (cd, insn)
 432               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 433
 434           /* Length < 0 -> error.  */
 435           if (length < 0)
 436             return length;
 437           if (length > 0)
 438             {
 439               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 440               /* Length is in bits, result is in bytes.  */
 441               return length / 8;
 442             }
 443         }
 444
 445       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 446     }
 447
 448   return 0;
 449 }
 450
 451 /* Default value for CGEN_PRINT_INSN.
 452    The result is the size of the insn in bytes or zero for an unknown insn
 453    or -1 if an error occured fetching bytes.  */
 454
 455 #ifndef CGEN_PRINT_INSN
 456 #define CGEN_PRINT_INSN default_print_insn
 457 #endif
 458
 459 static int
 460 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 461 {
 462   bfd_byte buf[CGEN_MAX_INSN_SIZE];
 463   int buflen;
 464   int status;
 465
 466   /* Attempt to read the base part of the insn.  */
 467   buflen = cd->base_insn_bitsize / 8;
 468   status = (*info->read_memory_func) (pc, buf, buflen, info);
 469
 470   /* Try again with the minimum part, if min < base.  */
 471   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 472     {
 473       buflen = cd->min_insn_bitsize / 8;
 474       status = (*info->read_memory_func) (pc, buf, buflen, info);
 475     }
 476
 477   if (status != 0)
 478     {
 479       (*info->memory_error_func) (status, pc, info);
 480       return -1;
 481     }
 482
 483   return print_insn (cd, pc, info, buf, buflen);
 484 }
 485
 486 /* Main entry point.
 487    Print one instruction from PC on INFO->STREAM.
 488    Return the size of the instruction (in bytes).  */
 489
 490 typedef struct cpu_desc_list
 491 {
 492   struct cpu_desc_list *next;
 493   CGEN_BITSET *isa;
 494   int mach;
 495   int endian;
 496   int insn_endian;
 497   CGEN_CPU_DESC cd;
 498 } cpu_desc_list;
 499
 500 int
 501 print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
 502 {
 503   static cpu_desc_list *cd_list = 0;
 504   cpu_desc_list *cl = 0;
 505   static CGEN_CPU_DESC cd = 0;
 506   static CGEN_BITSET *prev_isa;
 507   static int prev_mach;
 508   static int prev_endian;
 509   static int prev_insn_endian;
 510   int length;
 511   CGEN_BITSET *isa;
 512   int mach;
 513   int endian = (info->endian == BFD_ENDIAN_BIG
 514                 ? CGEN_ENDIAN_BIG
 515                 : CGEN_ENDIAN_LITTLE);
 516   int insn_endian = (info->endian_code == BFD_ENDIAN_BIG
 517                      ? CGEN_ENDIAN_BIG
 518                      : CGEN_ENDIAN_LITTLE);
 519   enum bfd_architecture arch;
 520
 521   /* ??? gdb will set mach but leave the architecture as "unknown" */
 522 #ifndef CGEN_BFD_ARCH
 523 #define CGEN_BFD_ARCH bfd_arch_iq2000
 524 #endif
 525   arch = info->arch;
 526   if (arch == bfd_arch_unknown)
 527     arch = CGEN_BFD_ARCH;
 528
 529   /* There's no standard way to compute the machine or isa number
 530      so we leave it to the target.  */
 531 #ifdef CGEN_COMPUTE_MACH
 532   mach = CGEN_COMPUTE_MACH (info);
 533 #else
 534   mach = info->mach;
 535 #endif
 536
 537 #ifdef CGEN_COMPUTE_ISA
 538   {
 539     static CGEN_BITSET *permanent_isa;
 540
 541     if (!permanent_isa)
 542       permanent_isa = cgen_bitset_create (MAX_ISAS);
 543     isa = permanent_isa;
 544     cgen_bitset_clear (isa);
 545     cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
 546   }
 547 #else
 548   isa = info->private_data;
 549 #endif
 550
 551   /* If we've switched cpu's, try to find a handle we've used before */
 552   if (cd
 553       && (cgen_bitset_compare (isa, prev_isa) != 0
 554           || mach != prev_mach
 555           || endian != prev_endian))
 556     {
 557       cd = 0;
 558       for (cl = cd_list; cl; cl = cl->next)
 559         {
 560           if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 561               cl->mach == mach &&
 562               cl->endian == endian)
 563             {
 564               cd = cl->cd;
 565               prev_isa = cd->isas;
 566               break;
 567             }
 568         }
 569     }
 570
 571   /* If we haven't initialized yet, initialize the opcode table.  */
 572   if (! cd)
 573     {
 574       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 575       const char *mach_name;
 576
 577       if (!arch_type)
 578         abort ();
 579       mach_name = arch_type->printable_name;
 580
 581       prev_isa = cgen_bitset_copy (isa);
 582       prev_mach = mach;
 583       prev_endian = endian;
 584       prev_insn_endian = insn_endian;
 585       cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 586                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 587                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 588                                  CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,
 589                                  CGEN_CPU_OPEN_END);
 590       if (!cd)
 591         abort ();
 592
 593       /* Save this away for future reference.  */
 594       cl = xmalloc (sizeof (struct cpu_desc_list));
 595       cl->cd = cd;
 596       cl->isa = prev_isa;
 597       cl->mach = mach;
 598       cl->endian = endian;
 599       cl->next = cd_list;
 600       cd_list = cl;
 601
 602       iq2000_cgen_init_dis (cd);
 603     }
 604
 605   /* We try to have as much common code as possible.
 606      But at this point some targets need to take over.  */
 607   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 608      but if not possible try to move this hook elsewhere rather than
 609      have two hooks.  */
 610   length = CGEN_PRINT_INSN (cd, pc, info);
 611   if (length > 0)
 612     return length;
 613   if (length < 0)
 614     return -1;
 615
 616   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 617   return cd->default_insn_bitsize / 8;
 618 }