arm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M Mainline
[binutils-gdb.git] / sim / aarch64 / aarch64-sim.h
blobf527b62c174ed2310f759f2cf7236996ebc97339
1 /* aarch64-sim.h -- Internal aarch64 settings.
3 Copyright (C) 2015-2024 Free Software Foundation, Inc.
5 Contributed by Red Hat.
7 This file is part of the GNU simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #ifndef AARCH64_SIM_H
23 #define AARCH64_SIM_H
25 #include <stdint.h>
27 #include "cpustate.h"
29 /* A per-core state structure. */
30 struct aarch64_sim_cpu
32 GRegister gr[33]; /* Extra register at index 32 is used to hold zero value. */
33 FRegister fr[32];
35 uint64_t pc;
36 uint32_t CPSR;
37 uint32_t FPSR; /* Floating point Status register. */
38 uint32_t FPCR; /* Floating point Control register. */
40 uint64_t nextpc;
41 uint32_t instr;
43 uint64_t tpidr; /* Thread pointer id. */
46 #define AARCH64_SIM_CPU(cpu) ((struct aarch64_sim_cpu *) CPU_ARCH_DATA (cpu))
48 typedef enum
50 AARCH64_MIN_GR = 0,
51 AARCH64_MAX_GR = 31,
52 AARCH64_MIN_FR = 32,
53 AARCH64_MAX_FR = 63,
54 AARCH64_PC_REGNO = 64,
55 AARCH64_CPSR_REGNO = 65,
56 AARCH64_FPSR_REGNO = 66,
57 AARCH64_MAX_REGNO = 67
58 } aarch64_regno;
60 #endif /* AARCH64_SIM_H */