sim/common/sim-core.h

   1 /* The common simulator framework for GDB, the GNU Debugger.
   2
   3    Copyright 2002-2024 Free Software Foundation, Inc.
   4
   5    Contributed by Andrew Cagney and Red Hat.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22
  23 #ifndef SIM_CORE_H
  24 #define SIM_CORE_H
  25
  26 #include "symcat.h"
  27
  28 /* core signals (error conditions)
  29    Define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
  30    details.  */
  31
  32 typedef enum {
  33   sim_core_unmapped_signal,
  34   sim_core_unaligned_signal,
  35   nr_sim_core_signals,
  36 } sim_core_signals;
  37
  38 /* Type of SIM_CORE_SIGNAL handler.  */
  39 typedef void (SIM_CORE_SIGNAL_FN)
  40      (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, unsigned map, int nr_bytes,
  41       address_word addr, transfer_type transfer, sim_core_signals sig);
  42
  43 extern SIM_CORE_SIGNAL_FN sim_core_signal ATTRIBUTE_NORETURN;
  44
  45
  46 /* basic types */
  47
  48 typedef struct _sim_core_mapping sim_core_mapping;
  49 struct _sim_core_mapping {
  50   /* common */
  51   int level;
  52   int space;
  53   unsigned_word base;
  54   unsigned_word bound;
  55   unsigned_word nr_bytes;
  56   unsigned mask;
  57   /* memory map */
  58   void *free_buffer;
  59   void *buffer;
  60   /* callback map */
  61   struct hw *device;
  62   /* tracing */
  63   int trace;
  64   /* growth */
  65   sim_core_mapping *next;
  66 };
  67
  68 typedef struct _sim_core_map sim_core_map;
  69 struct _sim_core_map {
  70   sim_core_mapping *first;
  71 };
  72
  73
  74 typedef struct _sim_core_common {
  75   sim_core_map map[nr_maps];
  76 } sim_core_common;
  77
  78
  79 /* Main core structure */
  80
  81 typedef struct _sim_core sim_core;
  82 struct _sim_core {
  83   sim_core_common common;
  84   address_word byte_xor; /* apply xor universally */
  85 };
  86
  87
  88 /* Per CPU distributed component of the core.  At present this is
  89    mostly a clone of the global core data structure. */
  90
  91 typedef struct _sim_cpu_core {
  92   sim_core_common common;
  93   address_word byte_xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
  94 } sim_cpu_core;
  95
  96
  97 /* Install the "core" module.  */
  98
  99 extern SIM_RC sim_core_install (SIM_DESC sd);
 100
 101
 102
 103 /* Create a memory region within the core.
 104
 105    CPU - when non NULL, specifes the single processor that the memory
 106    space is to be attached to. (INIMPLEMENTED).
 107
 108    LEVEL - specifies the ordering of the memory region.  Lower regions
 109    are searched first.  Within a level, memory regions can not
 110    overlap.
 111
 112    MAPMASK - Bitmask specifying the memory maps that the region is to
 113    be attached to.  Typically the enums sim-basics.h:access_* are used.
 114
 115    ADDRESS_SPACE - For device regions, a MAP:ADDRESS pair is
 116    translated into ADDRESS_SPACE:OFFSET before being passed to the
 117    client device.
 118
 119    MODULO - Specifies that accesses to the region [ADDR .. ADDR+NR_BYTES)
 120    should be mapped onto the sub region [ADDR .. ADDR+MODULO).  The modulo
 121    value must be a power of two.
 122
 123    DEVICE - When non NULL, indicates that this is a callback memory
 124    space and specified device's memory callback handler should be
 125    called.
 126
 127    OPTIONAL_BUFFER - when non NULL, specifies the buffer to use for
 128    data read & written to the region.  Normally a more efficient
 129    internal structure is used.  It is assumed that buffer is allocated
 130    such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
 131    (OPTIONAL_BUFFER % 8) == (ADDR % 8)).  It is defined to be a sub-optimal
 132    hook that allows clients to do nasty things that the interface doesn't
 133    accomodate. */
 134
 135 extern void sim_core_attach
 136 (SIM_DESC sd,
 137  sim_cpu *cpu,
 138  int level,
 139  unsigned mapmask,
 140  int address_space,
 141  address_word addr,
 142  address_word nr_bytes,
 143  unsigned modulo,
 144  struct hw *client,
 145  void *optional_buffer);
 146
 147
 148 /* Delete a memory section within the core.
 149
 150  */
 151
 152 extern void sim_core_detach
 153 (SIM_DESC sd,
 154  sim_cpu *cpu,
 155  int level,
 156  int address_space,
 157  address_word addr);
 158
 159
 160 /* Variable sized read/write
 161
 162    Transfer a variable sized block of raw data between the host and
 163    target.  Should any problems occur, the number of bytes
 164    successfully transfered is returned.
 165
 166    No host/target byte endian conversion is performed.  No xor-endian
 167    conversion is performed.
 168
 169    If CPU argument, when non NULL, specifies the processor specific
 170    address map that is to be used in the transfer. */
 171
 172
 173 extern unsigned sim_core_read_buffer
 174 (SIM_DESC sd,
 175  sim_cpu *cpu,
 176  unsigned map,
 177  void *buffer,
 178  address_word addr,
 179  unsigned nr_bytes);
 180
 181 extern unsigned sim_core_write_buffer
 182 (SIM_DESC sd,
 183  sim_cpu *cpu,
 184  unsigned map,
 185  const void *buffer,
 186  address_word addr,
 187  unsigned nr_bytes);
 188
 189
 190
 191 /* Configure the core's XOR endian transfer mode.  Only applicable
 192    when WITH_XOR_ENDIAN is enabled.
 193
 194    Targets suporting XOR endian, shall notify the core of any changes
 195    in state via this call.
 196
 197    The CPU argument, when non NULL, specifes the single processor that
 198    the xor-endian configuration is to be applied to. */
 199
 200 extern void sim_core_set_xor
 201 (SIM_DESC sd,
 202  sim_cpu *cpu,
 203  int is_xor);
 204
 205
 206 /* XOR version of variable sized read/write.
 207
 208    Transfer a variable sized block of raw data between the host and
 209    target.  Should any problems occur, the number of bytes
 210    successfully transfered is returned.
 211
 212    No host/target byte endian conversion is performed.  If applicable
 213    (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
 214    performed.
 215
 216    If CPU argument, when non NULL, specifies the processor specific
 217    address map that is to be used in the transfer. */
 218
 219 extern unsigned sim_core_xor_read_buffer
 220 (SIM_DESC sd,
 221  sim_cpu *cpu,
 222  unsigned map,
 223  void *buffer,
 224  address_word addr,
 225  unsigned nr_bytes);
 226
 227 extern unsigned sim_core_xor_write_buffer
 228 (SIM_DESC sd,
 229  sim_cpu *cpu,
 230  unsigned map,
 231  const void *buffer,
 232  address_word addr,
 233  unsigned nr_bytes);
 234
 235
 236 /* Translate an address based on a map.  */
 237
 238 extern void *sim_core_trans_addr
 239 (SIM_DESC sd,
 240  sim_cpu *cpu,
 241  unsigned map,
 242  address_word addr);
 243
 244
 245 /* Fixed sized, processor oriented, read/write.
 246
 247    Transfer a fixed amout of memory between the host and target.  The
 248    data transfered is translated from/to host to/from target byte
 249    order (including xor endian).  Should the transfer fail, the
 250    operation shall abort (no return).
 251
 252    ALIGNED assumes that the specified ADDRESS is correctly aligned
 253    for an N byte transfer (no alignment checks are made).  Passing an
 254    incorrectly aligned ADDRESS is erroneous.
 255
 256    UNALIGNED checks/modifies the ADDRESS according to the requirements
 257    of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
 258    taken should the check fail.
 259
 260    MISALIGNED transfers the data regardless.
 261
 262    Misaligned xor-endian accesses are broken into a sequence of
 263    transfers each <= WITH_XOR_ENDIAN bytes */
 264
 265
 266 #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \
 267 INLINE_SIM_CORE\
 268 (void) sim_core_write_##ALIGNMENT##_##N \
 269 (sim_cpu *cpu, \
 270  sim_cia cia, \
 271  unsigned map, \
 272  address_word addr, \
 273  unsigned_##M val);
 274
 275 DECLARE_SIM_CORE_WRITE_N(aligned,1,1)
 276 DECLARE_SIM_CORE_WRITE_N(aligned,2,2)
 277 DECLARE_SIM_CORE_WRITE_N(aligned,4,4)
 278 DECLARE_SIM_CORE_WRITE_N(aligned,8,8)
 279 DECLARE_SIM_CORE_WRITE_N(aligned,16,16)
 280
 281 #define sim_core_write_unaligned_1 sim_core_write_aligned_1
 282 DECLARE_SIM_CORE_WRITE_N(unaligned,2,2)
 283 DECLARE_SIM_CORE_WRITE_N(unaligned,4,4)
 284 DECLARE_SIM_CORE_WRITE_N(unaligned,8,8)
 285 DECLARE_SIM_CORE_WRITE_N(unaligned,16,16)
 286
 287 DECLARE_SIM_CORE_WRITE_N(misaligned,3,4)
 288 DECLARE_SIM_CORE_WRITE_N(misaligned,5,8)
 289 DECLARE_SIM_CORE_WRITE_N(misaligned,6,8)
 290 DECLARE_SIM_CORE_WRITE_N(misaligned,7,8)
 291
 292 #define sim_core_write_1 sim_core_write_aligned_1
 293 #define sim_core_write_2 sim_core_write_aligned_2
 294 #define sim_core_write_4 sim_core_write_aligned_4
 295 #define sim_core_write_8 sim_core_write_aligned_8
 296 #define sim_core_write_16 sim_core_write_aligned_16
 297
 298 #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
 299 #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
 300 #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
 301
 302 #undef DECLARE_SIM_CORE_WRITE_N
 303
 304
 305 #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \
 306 INLINE_SIM_CORE\
 307 (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \
 308 (sim_cpu *cpu, \
 309  sim_cia cia, \
 310  unsigned map, \
 311  address_word addr);
 312
 313 DECLARE_SIM_CORE_READ_N(aligned,1,1)
 314 DECLARE_SIM_CORE_READ_N(aligned,2,2)
 315 DECLARE_SIM_CORE_READ_N(aligned,4,4)
 316 DECLARE_SIM_CORE_READ_N(aligned,8,8)
 317 DECLARE_SIM_CORE_READ_N(aligned,16,16)
 318
 319 #define sim_core_read_unaligned_1 sim_core_read_aligned_1
 320 DECLARE_SIM_CORE_READ_N(unaligned,2,2)
 321 DECLARE_SIM_CORE_READ_N(unaligned,4,4)
 322 DECLARE_SIM_CORE_READ_N(unaligned,8,8)
 323 DECLARE_SIM_CORE_READ_N(unaligned,16,16)
 324
 325 DECLARE_SIM_CORE_READ_N(misaligned,3,4)
 326 DECLARE_SIM_CORE_READ_N(misaligned,5,8)
 327 DECLARE_SIM_CORE_READ_N(misaligned,6,8)
 328 DECLARE_SIM_CORE_READ_N(misaligned,7,8)
 329
 330
 331 #define sim_core_read_1 sim_core_read_aligned_1
 332 #define sim_core_read_2 sim_core_read_aligned_2
 333 #define sim_core_read_4 sim_core_read_aligned_4
 334 #define sim_core_read_8 sim_core_read_aligned_8
 335 #define sim_core_read_16 sim_core_read_aligned_16
 336
 337 #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
 338 #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
 339 #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
 340
 341 #undef DECLARE_SIM_CORE_READ_N
 342
 343 #endif