sim/d10v/d10v-sim.h

   1 #ifndef D10V_SIM_H
   2 #define D10V_SIM_H
   3
   4 #include <stdio.h>
   5 #include <ctype.h>
   6 #include <limits.h>
   7 #include "ansidecl.h"
   8 #include "sim/callback.h"
   9 #include "opcode/d10v.h"
  10 #include "bfd.h"
  11
  12 #define DEBUG_TRACE             0x00000001
  13 #define DEBUG_VALUES            0x00000002
  14 #define DEBUG_LINE_NUMBER       0x00000004
  15 #define DEBUG_MEMSIZE           0x00000008
  16 #define DEBUG_INSTRUCTION       0x00000010
  17 #define DEBUG_TRAP              0x00000020
  18 #define DEBUG_MEMORY            0x00000040
  19
  20 #ifndef DEBUG
  21 #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
  22 #endif
  23
  24 extern int d10v_debug;
  25
  26 #include "sim/sim.h"
  27 #include "sim-config.h"
  28 #include "sim-types.h"
  29
  30 /* FIXME: D10V defines */
  31 typedef uint16_t reg_t;
  32
  33 struct simops
  34 {
  35   long opcode;
  36   int  is_long;
  37   long mask;
  38   int format;
  39   int cycles;
  40   int unit;
  41   int exec_type;
  42   void (*func)(SIM_DESC, SIM_CPU *);
  43   int numops;
  44   int operands[9];
  45 };
  46
  47 enum _ins_type
  48 {
  49   INS_UNKNOWN,                  /* unknown instruction */
  50   INS_COND_TRUE,                /* # times EXExxx executed other instruction */
  51   INS_COND_FALSE,               /* # times EXExxx did not execute other instruction */
  52   INS_COND_JUMP,                /* # times JUMP skipped other instruction */
  53   INS_CYCLES,                   /* # cycles */
  54   INS_LONG,                     /* long instruction (both containers, ie FM == 11) */
  55   INS_LEFTRIGHT,                /* # times instruction encoded as L -> R (ie, FM == 01) */
  56   INS_RIGHTLEFT,                /* # times instruction encoded as L <- R (ie, FM == 10) */
  57   INS_PARALLEL,                 /* # times instruction encoded as L || R (ie, RM == 00) */
  58
  59   INS_LEFT,                     /* normal left instructions */
  60   INS_LEFT_PARALLEL,            /* left side of || */
  61   INS_LEFT_COND_TEST,           /* EXExx test on left side */
  62   INS_LEFT_COND_EXE,            /* execution after EXExxx test on right side succeeded */
  63   INS_LEFT_NOPS,                /* NOP on left side */
  64
  65   INS_RIGHT,                    /* normal right instructions */
  66   INS_RIGHT_PARALLEL,           /* right side of || */
  67   INS_RIGHT_COND_TEST,          /* EXExx test on right side */
  68   INS_RIGHT_COND_EXE,           /* execution after EXExxx test on left side succeeded */
  69   INS_RIGHT_NOPS,               /* NOP on right side */
  70
  71   INS_MAX
  72 };
  73
  74 extern unsigned long ins_type_counters[ (int)INS_MAX ];
  75
  76 enum {
  77   SP_IDX = 15,
  78 };
  79
  80 /* Write-back slots */
  81 union slot_data {
  82   unsigned_1 _1;
  83   unsigned_2 _2;
  84   unsigned_4 _4;
  85   unsigned_8 _8;
  86 };
  87 struct slot {
  88   void *dest;
  89   int size;
  90   union slot_data data;
  91   union slot_data mask;
  92 };
  93 enum {
  94  NR_SLOTS = 16,
  95 };
  96 #define SLOT (State.slot)
  97 #define SLOT_NR (State.slot_nr)
  98 #define SLOT_PEND_MASK(DEST, MSK, VAL) \
  99   do \
 100     { \
 101       SLOT[SLOT_NR].dest = &(DEST); \
 102       SLOT[SLOT_NR].size = sizeof (DEST); \
 103       switch (sizeof (DEST)) \
 104         { \
 105         case 1: \
 106           SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
 107           SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
 108           break; \
 109         case 2: \
 110           SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
 111           SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
 112           break; \
 113         case 4: \
 114           SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
 115           SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
 116           break; \
 117         case 8: \
 118           SLOT[SLOT_NR].data._8 = (unsigned_8) (VAL); \
 119           SLOT[SLOT_NR].mask._8 = (unsigned_8) (MSK); \
 120           break; \
 121         } \
 122       SLOT_NR = (SLOT_NR + 1); \
 123     } \
 124   while (0)
 125 #define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
 126 #define SLOT_DISCARD() (SLOT_NR = 0)
 127 #define SLOT_FLUSH() \
 128   do \
 129     { \
 130       int i; \
 131       for (i = 0; i < SLOT_NR; i++) \
 132         { \
 133           switch (SLOT[i].size) \
 134             { \
 135             case 1: \
 136               *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
 137               *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
 138               break; \
 139             case 2: \
 140               *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
 141               *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
 142               break; \
 143             case 4: \
 144               *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
 145               *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
 146               break; \
 147             case 8: \
 148               *(unsigned_8*) SLOT[i].dest &= SLOT[i].mask._8; \
 149               *(unsigned_8*) SLOT[i].dest |= SLOT[i].data._8; \
 150               break; \
 151             } \
 152         } \
 153       SLOT_NR = 0; \
 154     } \
 155   while (0)
 156 #define SLOT_DUMP() \
 157   do \
 158     { \
 159       int i; \
 160       for (i = 0; i < SLOT_NR; i++) \
 161         { \
 162           switch (SLOT[i].size) \
 163             { \
 164             case 1: \
 165               printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
 166                       (long) SLOT[i].dest, \
 167                       (unsigned) SLOT[i].mask._1, \
 168                       (unsigned) SLOT[i].data._1); \
 169               break; \
 170             case 2: \
 171               printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
 172                       (long) SLOT[i].dest, \
 173                       (unsigned) SLOT[i].mask._2, \
 174                       (unsigned) SLOT[i].data._2); \
 175               break; \
 176             case 4: \
 177               printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
 178                       (long) SLOT[i].dest, \
 179                       (unsigned) SLOT[i].mask._4, \
 180                       (unsigned) SLOT[i].data._4); \
 181               break; \
 182             case 8: \
 183               printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
 184                       (long) SLOT[i].dest, \
 185                       (unsigned) (SLOT[i].mask._8 >> 32),  \
 186                       (unsigned) SLOT[i].mask._8, \
 187                       (unsigned) (SLOT[i].data._8 >> 32),  \
 188                       (unsigned) SLOT[i].data._8); \
 189               break; \
 190             } \
 191         } \
 192     } \
 193   while (0)
 194
 195 /* d10v memory: There are three separate d10v memory regions IMEM,
 196    UMEM and DMEM.  The IMEM and DMEM are further broken down into
 197    blocks (very like VM pages). */
 198
 199 enum
 200 {
 201   IMAP_BLOCK_SIZE = 0x20000,
 202   DMAP_BLOCK_SIZE = 0x4000,
 203 };
 204
 205 /* Implement the three memory regions using sparse arrays.  Allocate
 206    memory using ``segments''.  A segment must be at least as large as
 207    a BLOCK - ensures that an access that doesn't cross a block
 208    boundary can't cross a segment boundary */
 209
 210 enum
 211 {
 212   SEGMENT_SIZE = 0x20000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
 213   IMEM_SEGMENTS = 8, /* 1MB */
 214   DMEM_SEGMENTS = 8, /* 1MB */
 215   UMEM_SEGMENTS = 128 /* 16MB */
 216 };
 217
 218 struct d10v_memory
 219 {
 220   uint8_t *insn[IMEM_SEGMENTS];
 221   uint8_t *data[DMEM_SEGMENTS];
 222   uint8_t *unif[UMEM_SEGMENTS];
 223 };
 224
 225 struct _state
 226 {
 227   reg_t regs[16];               /* general-purpose registers */
 228 #define GPR(N) (State.regs[(N)] + 0)
 229 #define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))
 230
 231 #define GPR32(N) ((((uint32_t) State.regs[(N) + 0]) << 16) \
 232                   | (uint16_t) State.regs[(N) + 1])
 233 #define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)
 234
 235   reg_t cregs[16];              /* control registers */
 236 #define CREG(N) (State.cregs[(N)] + 0)
 237 #define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
 238 #define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
 239
 240   reg_t sp[2];                  /* holding area for SPI(0)/SPU(1) */
 241 #define HELD_SP(N) (State.sp[(N)] + 0)
 242 #define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
 243
 244   int64_t a[2];                 /* accumulators */
 245 #define ACC(N) (State.a[(N)] + 0)
 246 #define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)
 247
 248   /* writeback info */
 249   struct slot slot[NR_SLOTS];
 250   int slot_nr;
 251
 252   /* trace data */
 253   struct {
 254     uint16_t psw;
 255   } trace;
 256
 257   uint8_t exe;
 258   int   pc_changed;
 259
 260   /* NOTE: everything below this line is not reset by
 261      sim_create_inferior() */
 262
 263   struct d10v_memory mem;
 264
 265   enum _ins_type ins_type;
 266
 267 };
 268
 269 extern struct _state State;
 270
 271
 272 extern uint16_t OP[4];
 273 extern struct simops Simops[];
 274
 275 enum
 276 {
 277   PSW_CR = 0,
 278   BPSW_CR = 1,
 279   PC_CR = 2,
 280   BPC_CR = 3,
 281   DPSW_CR = 4,
 282   DPC_CR = 5,
 283   RPT_C_CR = 7,
 284   RPT_S_CR = 8,
 285   RPT_E_CR = 9,
 286   MOD_S_CR = 10,
 287   MOD_E_CR = 11,
 288   IBA_CR = 14,
 289 };
 290
 291 enum
 292 {
 293   PSW_SM_BIT = 0x8000,
 294   PSW_EA_BIT = 0x2000,
 295   PSW_DB_BIT = 0x1000,
 296   PSW_DM_BIT = 0x0800,
 297   PSW_IE_BIT = 0x0400,
 298   PSW_RP_BIT = 0x0200,
 299   PSW_MD_BIT = 0x0100,
 300   PSW_FX_BIT = 0x0080,
 301   PSW_ST_BIT = 0x0040,
 302   PSW_F0_BIT = 0x0008,
 303   PSW_F1_BIT = 0x0004,
 304   PSW_C_BIT =  0x0001,
 305 };
 306
 307 #define PSW CREG (PSW_CR)
 308 #define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
 309 #define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL))
 310 #define SET_PSW_BIT(MASK,VAL) move_to_cr (sd, cpu, PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)
 311
 312 #define PSW_SM ((PSW & PSW_SM_BIT) != 0)
 313 #define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))
 314
 315 #define PSW_EA ((PSW & PSW_EA_BIT) != 0)
 316 #define SET_PSW_EA(VAL) SET_PSW_BIT (PSW_EA_BIT, (VAL))
 317
 318 #define PSW_DB ((PSW & PSW_DB_BIT) != 0)
 319 #define SET_PSW_DB(VAL) SET_PSW_BIT (PSW_DB_BIT, (VAL))
 320
 321 #define PSW_DM ((PSW & PSW_DM_BIT) != 0)
 322 #define SET_PSW_DM(VAL) SET_PSW_BIT (PSW_DM_BIT, (VAL))
 323
 324 #define PSW_IE ((PSW & PSW_IE_BIT) != 0)
 325 #define SET_PSW_IE(VAL) SET_PSW_BIT (PSW_IE_BIT, (VAL))
 326
 327 #define PSW_RP ((PSW & PSW_RP_BIT) != 0)
 328 #define SET_PSW_RP(VAL) SET_PSW_BIT (PSW_RP_BIT, (VAL))
 329
 330 #define PSW_MD ((PSW & PSW_MD_BIT) != 0)
 331 #define SET_PSW_MD(VAL) SET_PSW_BIT (PSW_MD_BIT, (VAL))
 332
 333 #define PSW_FX ((PSW & PSW_FX_BIT) != 0)
 334 #define SET_PSW_FX(VAL) SET_PSW_BIT (PSW_FX_BIT, (VAL))
 335
 336 #define PSW_ST ((PSW & PSW_ST_BIT) != 0)
 337 #define SET_PSW_ST(VAL) SET_PSW_BIT (PSW_ST_BIT, (VAL))
 338
 339 #define PSW_F0 ((PSW & PSW_F0_BIT) != 0)
 340 #define SET_PSW_F0(VAL) SET_PSW_BIT (PSW_F0_BIT, (VAL))
 341
 342 #define PSW_F1 ((PSW & PSW_F1_BIT) != 0)
 343 #define SET_PSW_F1(VAL) SET_PSW_BIT (PSW_F1_BIT, (VAL))
 344
 345 #define PSW_C ((PSW & PSW_C_BIT) != 0)
 346 #define SET_PSW_C(VAL) SET_PSW_BIT (PSW_C_BIT, (VAL))
 347
 348 /* See simopsc.:move_to_cr() for registers that can not be read-from
 349    or assigned-to directly */
 350
 351 #define PC      CREG (PC_CR)
 352 #define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
 353
 354 #define BPSW    CREG (BPSW_CR)
 355 #define SET_BPSW(VAL) SET_CREG (BPSW_CR, (VAL))
 356
 357 #define BPC     CREG (BPC_CR)
 358 #define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
 359
 360 #define DPSW    CREG (DPSW_CR)
 361 #define SET_DPSW(VAL) SET_CREG (DPSW_CR, (VAL))
 362
 363 #define DPC     CREG (DPC_CR)
 364 #define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
 365
 366 #define RPT_C   CREG (RPT_C_CR)
 367 #define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
 368
 369 #define RPT_S   CREG (RPT_S_CR)
 370 #define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
 371
 372 #define RPT_E   CREG (RPT_E_CR)
 373 #define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
 374
 375 #define MOD_S   CREG (MOD_S_CR)
 376 #define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
 377
 378 #define MOD_E   CREG (MOD_E_CR)
 379 #define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
 380
 381 #define IBA     CREG (IBA_CR)
 382 #define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
 383
 384
 385 #define SIG_D10V_STOP   -1
 386 #define SIG_D10V_EXIT   -2
 387 #define SIG_D10V_BUS    -3
 388
 389 /* TODO: Resolve conflicts with common headers.  */
 390 #undef SEXT8
 391 #undef SEXT16
 392 #undef SEXT32
 393 #undef MASK32
 394
 395 #define SEXT3(x)        ((((x)&0x7)^(~3))+4)
 396
 397 /* sign-extend a 4-bit number */
 398 #define SEXT4(x)        ((((x)&0xf)^(~7))+8)
 399
 400 /* sign-extend an 8-bit number */
 401 #define SEXT8(x)        ((((x)&0xff)^(~0x7f))+0x80)
 402
 403 /* sign-extend a 16-bit number */
 404 #define SEXT16(x)       ((((x)&0xffff)^(~0x7fff))+0x8000)
 405
 406 /* sign-extend a 32-bit number */
 407 #define SEXT32(x)       ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000))
 408
 409 /* sign extend a 40 bit number */
 410 #define SEXT40(x)       ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000))
 411
 412 /* sign extend a 44 bit number */
 413 #define SEXT44(x)       ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000))
 414
 415 /* sign extend a 56 bit number */
 416 #define SEXT56(x)       ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000))
 417
 418 /* sign extend a 60 bit number */
 419 #define SEXT60(x)       ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000))
 420
 421 #define MAX32   SIGNED64(0x7fffffff)
 422 #define MIN32   SIGNED64(0xff80000000)
 423 #define MASK32  SIGNED64(0xffffffff)
 424 #define MASK40  SIGNED64(0xffffffffff)
 425
 426 /* The alignment of MOD_E in the following macro depends upon "i"
 427    always being a power of 2. */
 428 #define INC_ADDR(x,i) \
 429 do \
 430   { \
 431     int test_i = i < 0 ? i : ~((i) - 1); \
 432     if (PSW_MD && GPR (x) == (MOD_E & test_i)) \
 433       SET_GPR (x, MOD_S & test_i); \
 434     else \
 435       SET_GPR (x, GPR (x) + (i)); \
 436   } \
 437 while (0)
 438
 439 extern uint8_t *dmem_addr (SIM_DESC, SIM_CPU *, uint16_t offset);
 440 extern uint8_t *imem_addr (SIM_DESC, SIM_CPU *, uint32_t);
 441
 442 #define RB(x)   (*(dmem_addr (sd, cpu, x)))
 443 #define SB(addr,data)   ( RB(addr) = (data & 0xff))
 444
 445 #if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
 446 #define ENDIAN_INLINE static __inline__
 447 #include "endian.c"
 448 #undef ENDIAN_INLINE
 449
 450 #else
 451 extern uint32_t get_longword (const uint8_t *);
 452 extern uint16_t get_word (const uint8_t *);
 453 extern int64_t get_longlong (const uint8_t *);
 454 extern void write_word (uint8_t *addr, uint16_t data);
 455 extern void write_longword (uint8_t *addr, uint32_t data);
 456 extern void write_longlong (uint8_t *addr, int64_t data);
 457 #endif
 458
 459 #define SW(addr,data)           write_word (dmem_addr (sd, cpu, addr), data)
 460 #define RW(x)                   get_word (dmem_addr (sd, cpu, x))
 461 #define SLW(addr,data)          write_longword (dmem_addr (sd, cpu, addr), data)
 462 #define RLW(x)                  get_longword (dmem_addr (sd, cpu, x))
 463 #define READ_16(x)              get_word(x)
 464 #define WRITE_16(addr,data)     write_word(addr,data)
 465 #define READ_64(x)              get_longlong(x)
 466 #define WRITE_64(addr,data)     write_longlong(addr,data)
 467
 468 #define JMP(x)                  do { SET_PC (x); State.pc_changed = 1; } while (0)
 469
 470 #define RIE_VECTOR_START 0xffc2
 471 #define AE_VECTOR_START 0xffc3
 472 #define TRAP_VECTOR_START 0xffc4        /* vector for trap 0 */
 473 #define DBT_VECTOR_START 0xffd4
 474 #define SDBT_VECTOR_START 0xffd5
 475
 476 /* Scedule a store of VAL into cr[CR].  MASK indicates the bits in
 477    cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
 478    (VAL & ~MASK)).  In addition, unless PSW_HW_P, a VAL intended for
 479    PSW is masked for zero bits. */
 480
 481 extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p);
 482
 483 #endif