sim/lm32/decode.c

   1 /* Simulator instruction decoder for lm32bf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996-2024 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #define WANT_CPU lm32bf
  26 #define WANT_CPU_LM32BF
  27
  28 #include "sim-main.h"
  29 #include "sim-assert.h"
  30 #include "cgen-mem.h"
  31 #include "cgen-ops.h"
  32
  33 /* The instruction descriptor array.
  34    This is computed at runtime.  Space for it is not malloc'd to save a
  35    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
  36    but won't be done until necessary (we don't currently support the runtime
  37    addition of instructions nor an SMP machine with different cpus).  */
  38 static IDESC lm32bf_insn_data[LM32BF_INSN__MAX];
  39
  40 /* Commas between elements are contained in the macros.
  41    Some of these are conditionally compiled out.  */
  42
  43 static const struct insn_sem lm32bf_insn_sem[] =
  44 {
  45   { VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY },
  46   { VIRTUAL_INSN_X_AFTER, LM32BF_INSN_X_AFTER, LM32BF_SFMT_EMPTY },
  47   { VIRTUAL_INSN_X_BEFORE, LM32BF_INSN_X_BEFORE, LM32BF_SFMT_EMPTY },
  48   { VIRTUAL_INSN_X_CTI_CHAIN, LM32BF_INSN_X_CTI_CHAIN, LM32BF_SFMT_EMPTY },
  49   { VIRTUAL_INSN_X_CHAIN, LM32BF_INSN_X_CHAIN, LM32BF_SFMT_EMPTY },
  50   { VIRTUAL_INSN_X_BEGIN, LM32BF_INSN_X_BEGIN, LM32BF_SFMT_EMPTY },
  51   { LM32_INSN_ADD, LM32BF_INSN_ADD, LM32BF_SFMT_ADD },
  52   { LM32_INSN_ADDI, LM32BF_INSN_ADDI, LM32BF_SFMT_ADDI },
  53   { LM32_INSN_AND, LM32BF_INSN_AND, LM32BF_SFMT_ADD },
  54   { LM32_INSN_ANDI, LM32BF_INSN_ANDI, LM32BF_SFMT_ANDI },
  55   { LM32_INSN_ANDHII, LM32BF_INSN_ANDHII, LM32BF_SFMT_ANDHII },
  56   { LM32_INSN_B, LM32BF_INSN_B, LM32BF_SFMT_B },
  57   { LM32_INSN_BI, LM32BF_INSN_BI, LM32BF_SFMT_BI },
  58   { LM32_INSN_BE, LM32BF_INSN_BE, LM32BF_SFMT_BE },
  59   { LM32_INSN_BG, LM32BF_INSN_BG, LM32BF_SFMT_BE },
  60   { LM32_INSN_BGE, LM32BF_INSN_BGE, LM32BF_SFMT_BE },
  61   { LM32_INSN_BGEU, LM32BF_INSN_BGEU, LM32BF_SFMT_BE },
  62   { LM32_INSN_BGU, LM32BF_INSN_BGU, LM32BF_SFMT_BE },
  63   { LM32_INSN_BNE, LM32BF_INSN_BNE, LM32BF_SFMT_BE },
  64   { LM32_INSN_CALL, LM32BF_INSN_CALL, LM32BF_SFMT_CALL },
  65   { LM32_INSN_CALLI, LM32BF_INSN_CALLI, LM32BF_SFMT_CALLI },
  66   { LM32_INSN_CMPE, LM32BF_INSN_CMPE, LM32BF_SFMT_ADD },
  67   { LM32_INSN_CMPEI, LM32BF_INSN_CMPEI, LM32BF_SFMT_ADDI },
  68   { LM32_INSN_CMPG, LM32BF_INSN_CMPG, LM32BF_SFMT_ADD },
  69   { LM32_INSN_CMPGI, LM32BF_INSN_CMPGI, LM32BF_SFMT_ADDI },
  70   { LM32_INSN_CMPGE, LM32BF_INSN_CMPGE, LM32BF_SFMT_ADD },
  71   { LM32_INSN_CMPGEI, LM32BF_INSN_CMPGEI, LM32BF_SFMT_ADDI },
  72   { LM32_INSN_CMPGEU, LM32BF_INSN_CMPGEU, LM32BF_SFMT_ADD },
  73   { LM32_INSN_CMPGEUI, LM32BF_INSN_CMPGEUI, LM32BF_SFMT_ANDI },
  74   { LM32_INSN_CMPGU, LM32BF_INSN_CMPGU, LM32BF_SFMT_ADD },
  75   { LM32_INSN_CMPGUI, LM32BF_INSN_CMPGUI, LM32BF_SFMT_ANDI },
  76   { LM32_INSN_CMPNE, LM32BF_INSN_CMPNE, LM32BF_SFMT_ADD },
  77   { LM32_INSN_CMPNEI, LM32BF_INSN_CMPNEI, LM32BF_SFMT_ADDI },
  78   { LM32_INSN_DIVU, LM32BF_INSN_DIVU, LM32BF_SFMT_DIVU },
  79   { LM32_INSN_LB, LM32BF_INSN_LB, LM32BF_SFMT_LB },
  80   { LM32_INSN_LBU, LM32BF_INSN_LBU, LM32BF_SFMT_LB },
  81   { LM32_INSN_LH, LM32BF_INSN_LH, LM32BF_SFMT_LH },
  82   { LM32_INSN_LHU, LM32BF_INSN_LHU, LM32BF_SFMT_LH },
  83   { LM32_INSN_LW, LM32BF_INSN_LW, LM32BF_SFMT_LW },
  84   { LM32_INSN_MODU, LM32BF_INSN_MODU, LM32BF_SFMT_DIVU },
  85   { LM32_INSN_MUL, LM32BF_INSN_MUL, LM32BF_SFMT_ADD },
  86   { LM32_INSN_MULI, LM32BF_INSN_MULI, LM32BF_SFMT_ADDI },
  87   { LM32_INSN_NOR, LM32BF_INSN_NOR, LM32BF_SFMT_ADD },
  88   { LM32_INSN_NORI, LM32BF_INSN_NORI, LM32BF_SFMT_ANDI },
  89   { LM32_INSN_OR, LM32BF_INSN_OR, LM32BF_SFMT_ADD },
  90   { LM32_INSN_ORI, LM32BF_INSN_ORI, LM32BF_SFMT_ORI },
  91   { LM32_INSN_ORHII, LM32BF_INSN_ORHII, LM32BF_SFMT_ANDHII },
  92   { LM32_INSN_RCSR, LM32BF_INSN_RCSR, LM32BF_SFMT_RCSR },
  93   { LM32_INSN_SB, LM32BF_INSN_SB, LM32BF_SFMT_SB },
  94   { LM32_INSN_SEXTB, LM32BF_INSN_SEXTB, LM32BF_SFMT_SEXTB },
  95   { LM32_INSN_SEXTH, LM32BF_INSN_SEXTH, LM32BF_SFMT_SEXTB },
  96   { LM32_INSN_SH, LM32BF_INSN_SH, LM32BF_SFMT_SH },
  97   { LM32_INSN_SL, LM32BF_INSN_SL, LM32BF_SFMT_ADD },
  98   { LM32_INSN_SLI, LM32BF_INSN_SLI, LM32BF_SFMT_ADDI },
  99   { LM32_INSN_SR, LM32BF_INSN_SR, LM32BF_SFMT_ADD },
 100   { LM32_INSN_SRI, LM32BF_INSN_SRI, LM32BF_SFMT_ADDI },
 101   { LM32_INSN_SRU, LM32BF_INSN_SRU, LM32BF_SFMT_ADD },
 102   { LM32_INSN_SRUI, LM32BF_INSN_SRUI, LM32BF_SFMT_ADDI },
 103   { LM32_INSN_SUB, LM32BF_INSN_SUB, LM32BF_SFMT_ADD },
 104   { LM32_INSN_SW, LM32BF_INSN_SW, LM32BF_SFMT_SW },
 105   { LM32_INSN_USER, LM32BF_INSN_USER, LM32BF_SFMT_USER },
 106   { LM32_INSN_WCSR, LM32BF_INSN_WCSR, LM32BF_SFMT_WCSR },
 107   { LM32_INSN_XOR, LM32BF_INSN_XOR, LM32BF_SFMT_ADD },
 108   { LM32_INSN_XORI, LM32BF_INSN_XORI, LM32BF_SFMT_ANDI },
 109   { LM32_INSN_XNOR, LM32BF_INSN_XNOR, LM32BF_SFMT_ADD },
 110   { LM32_INSN_XNORI, LM32BF_INSN_XNORI, LM32BF_SFMT_ANDI },
 111   { LM32_INSN_BREAK, LM32BF_INSN_BREAK, LM32BF_SFMT_BREAK },
 112   { LM32_INSN_SCALL, LM32BF_INSN_SCALL, LM32BF_SFMT_BREAK },
 113 };
 114
 115 static const struct insn_sem lm32bf_insn_sem_invalid =
 116 {
 117   VIRTUAL_INSN_X_INVALID, LM32BF_INSN_X_INVALID, LM32BF_SFMT_EMPTY
 118 };
 119
 120 /* Initialize an IDESC from the compile-time computable parts.  */
 121
 122 static INLINE void
 123 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
 124 {
 125   const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
 126
 127   id->num = t->index;
 128   id->sfmt = t->sfmt;
 129   if ((int) t->type <= 0)
 130     id->idata = & cgen_virtual_insn_table[- (int) t->type];
 131   else
 132     id->idata = & insn_table[t->type];
 133   id->attrs = CGEN_INSN_ATTRS (id->idata);
 134   /* Oh my god, a magic number.  */
 135   id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
 136
 137 #if WITH_PROFILE_MODEL_P
 138   id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
 139   {
 140     SIM_DESC sd = CPU_STATE (cpu);
 141     SIM_ASSERT (t->index == id->timing->num);
 142   }
 143 #endif
 144
 145   /* Semantic pointers are initialized elsewhere.  */
 146 }
 147
 148 /* Initialize the instruction descriptor table.  */
 149
 150 void
 151 lm32bf_init_idesc_table (SIM_CPU *cpu)
 152 {
 153   IDESC *id,*tabend;
 154   const struct insn_sem *t,*tend;
 155   int tabsize = LM32BF_INSN__MAX;
 156   IDESC *table = lm32bf_insn_data;
 157
 158   memset (table, 0, tabsize * sizeof (IDESC));
 159
 160   /* First set all entries to the `invalid insn'.  */
 161   t = & lm32bf_insn_sem_invalid;
 162   for (id = table, tabend = table + tabsize; id < tabend; ++id)
 163     init_idesc (cpu, id, t);
 164
 165   /* Now fill in the values for the chosen cpu.  */
 166   for (t = lm32bf_insn_sem, tend = t + ARRAY_SIZE (lm32bf_insn_sem);
 167        t != tend; ++t)
 168     {
 169       init_idesc (cpu, & table[t->index], t);
 170     }
 171
 172   /* Link the IDESC table into the cpu.  */
 173   CPU_IDESC (cpu) = table;
 174 }
 175
 176 /* Given an instruction, return a pointer to its IDESC entry.  */
 177
 178 const IDESC *
 179 lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
 180               CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
 181               ARGBUF *abuf)
 182 {
 183   /* Result of decoder.  */
 184   LM32BF_INSN_TYPE itype;
 185
 186   {
 187     CGEN_INSN_WORD insn = base_insn;
 188
 189     {
 190       unsigned int val0 = (((insn >> 26) & (63 << 0)));
 191       switch (val0)
 192       {
 193       case 0: itype = LM32BF_INSN_SRUI; goto extract_sfmt_addi;
 194       case 1: itype = LM32BF_INSN_NORI; goto extract_sfmt_andi;
 195       case 2: itype = LM32BF_INSN_MULI; goto extract_sfmt_addi;
 196       case 3: itype = LM32BF_INSN_SH; goto extract_sfmt_sh;
 197       case 4: itype = LM32BF_INSN_LB; goto extract_sfmt_lb;
 198       case 5: itype = LM32BF_INSN_SRI; goto extract_sfmt_addi;
 199       case 6: itype = LM32BF_INSN_XORI; goto extract_sfmt_andi;
 200       case 7: itype = LM32BF_INSN_LH; goto extract_sfmt_lh;
 201       case 8: itype = LM32BF_INSN_ANDI; goto extract_sfmt_andi;
 202       case 9: itype = LM32BF_INSN_XNORI; goto extract_sfmt_andi;
 203       case 10: itype = LM32BF_INSN_LW; goto extract_sfmt_lw;
 204       case 11: itype = LM32BF_INSN_LHU; goto extract_sfmt_lh;
 205       case 12: itype = LM32BF_INSN_SB; goto extract_sfmt_sb;
 206       case 13: itype = LM32BF_INSN_ADDI; goto extract_sfmt_addi;
 207       case 14: itype = LM32BF_INSN_ORI; goto extract_sfmt_ori;
 208       case 15: itype = LM32BF_INSN_SLI; goto extract_sfmt_addi;
 209       case 16: itype = LM32BF_INSN_LBU; goto extract_sfmt_lb;
 210       case 17: itype = LM32BF_INSN_BE; goto extract_sfmt_be;
 211       case 18: itype = LM32BF_INSN_BG; goto extract_sfmt_be;
 212       case 19: itype = LM32BF_INSN_BGE; goto extract_sfmt_be;
 213       case 20: itype = LM32BF_INSN_BGEU; goto extract_sfmt_be;
 214       case 21: itype = LM32BF_INSN_BGU; goto extract_sfmt_be;
 215       case 22: itype = LM32BF_INSN_SW; goto extract_sfmt_sw;
 216       case 23: itype = LM32BF_INSN_BNE; goto extract_sfmt_be;
 217       case 24: itype = LM32BF_INSN_ANDHII; goto extract_sfmt_andhii;
 218       case 25: itype = LM32BF_INSN_CMPEI; goto extract_sfmt_addi;
 219       case 26: itype = LM32BF_INSN_CMPGI; goto extract_sfmt_addi;
 220       case 27: itype = LM32BF_INSN_CMPGEI; goto extract_sfmt_addi;
 221       case 28: itype = LM32BF_INSN_CMPGEUI; goto extract_sfmt_andi;
 222       case 29: itype = LM32BF_INSN_CMPGUI; goto extract_sfmt_andi;
 223       case 30: itype = LM32BF_INSN_ORHII; goto extract_sfmt_andhii;
 224       case 31: itype = LM32BF_INSN_CMPNEI; goto extract_sfmt_addi;
 225       case 32:
 226         if ((entire_insn & 0xfc0007ff) == 0x80000000)
 227           { itype = LM32BF_INSN_SRU; goto extract_sfmt_add; }
 228         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 229       case 33:
 230         if ((entire_insn & 0xfc0007ff) == 0x84000000)
 231           { itype = LM32BF_INSN_NOR; goto extract_sfmt_add; }
 232         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 233       case 34:
 234         if ((entire_insn & 0xfc0007ff) == 0x88000000)
 235           { itype = LM32BF_INSN_MUL; goto extract_sfmt_add; }
 236         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 237       case 35:
 238         if ((entire_insn & 0xfc0007ff) == 0x8c000000)
 239           { itype = LM32BF_INSN_DIVU; goto extract_sfmt_divu; }
 240         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 241       case 36:
 242         if ((entire_insn & 0xfc1f07ff) == 0x90000000)
 243           { itype = LM32BF_INSN_RCSR; goto extract_sfmt_rcsr; }
 244         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 245       case 37:
 246         if ((entire_insn & 0xfc0007ff) == 0x94000000)
 247           { itype = LM32BF_INSN_SR; goto extract_sfmt_add; }
 248         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 249       case 38:
 250         if ((entire_insn & 0xfc0007ff) == 0x98000000)
 251           { itype = LM32BF_INSN_XOR; goto extract_sfmt_add; }
 252         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 253       case 40:
 254         if ((entire_insn & 0xfc0007ff) == 0xa0000000)
 255           { itype = LM32BF_INSN_AND; goto extract_sfmt_add; }
 256         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 257       case 41:
 258         if ((entire_insn & 0xfc0007ff) == 0xa4000000)
 259           { itype = LM32BF_INSN_XNOR; goto extract_sfmt_add; }
 260         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 261       case 43:
 262         {
 263           unsigned int val1 = (((insn >> 1) & (1 << 1)) | ((insn >> 0) & (1 << 0)));
 264           switch (val1)
 265           {
 266           case 0:
 267             if ((entire_insn & 0xffffffff) == 0xac000002)
 268               { itype = LM32BF_INSN_BREAK; goto extract_sfmt_break; }
 269             itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 270           case 3:
 271             if ((entire_insn & 0xffffffff) == 0xac000007)
 272               { itype = LM32BF_INSN_SCALL; goto extract_sfmt_break; }
 273             itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 274           default: itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 275           }
 276         }
 277       case 44:
 278         if ((entire_insn & 0xfc1f07ff) == 0xb0000000)
 279           { itype = LM32BF_INSN_SEXTB; goto extract_sfmt_sextb; }
 280         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 281       case 45:
 282         if ((entire_insn & 0xfc0007ff) == 0xb4000000)
 283           { itype = LM32BF_INSN_ADD; goto extract_sfmt_add; }
 284         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 285       case 46:
 286         if ((entire_insn & 0xfc0007ff) == 0xb8000000)
 287           { itype = LM32BF_INSN_OR; goto extract_sfmt_add; }
 288         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 289       case 47:
 290         if ((entire_insn & 0xfc0007ff) == 0xbc000000)
 291           { itype = LM32BF_INSN_SL; goto extract_sfmt_add; }
 292         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 293       case 48:
 294         if ((entire_insn & 0xfc1fffff) == 0xc0000000)
 295           { itype = LM32BF_INSN_B; goto extract_sfmt_b; }
 296         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 297       case 49:
 298         if ((entire_insn & 0xfc0007ff) == 0xc4000000)
 299           { itype = LM32BF_INSN_MODU; goto extract_sfmt_divu; }
 300         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 301       case 50:
 302         if ((entire_insn & 0xfc0007ff) == 0xc8000000)
 303           { itype = LM32BF_INSN_SUB; goto extract_sfmt_add; }
 304         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 305       case 51: itype = LM32BF_INSN_USER; goto extract_sfmt_user;
 306       case 52:
 307         if ((entire_insn & 0xfc00ffff) == 0xd0000000)
 308           { itype = LM32BF_INSN_WCSR; goto extract_sfmt_wcsr; }
 309         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 310       case 54:
 311         if ((entire_insn & 0xfc1fffff) == 0xd8000000)
 312           { itype = LM32BF_INSN_CALL; goto extract_sfmt_call; }
 313         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 314       case 55:
 315         if ((entire_insn & 0xfc1f07ff) == 0xdc000000)
 316           { itype = LM32BF_INSN_SEXTH; goto extract_sfmt_sextb; }
 317         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 318       case 56: itype = LM32BF_INSN_BI; goto extract_sfmt_bi;
 319       case 57:
 320         if ((entire_insn & 0xfc0007ff) == 0xe4000000)
 321           { itype = LM32BF_INSN_CMPE; goto extract_sfmt_add; }
 322         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 323       case 58:
 324         if ((entire_insn & 0xfc0007ff) == 0xe8000000)
 325           { itype = LM32BF_INSN_CMPG; goto extract_sfmt_add; }
 326         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 327       case 59:
 328         if ((entire_insn & 0xfc0007ff) == 0xec000000)
 329           { itype = LM32BF_INSN_CMPGE; goto extract_sfmt_add; }
 330         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 331       case 60:
 332         if ((entire_insn & 0xfc0007ff) == 0xf0000000)
 333           { itype = LM32BF_INSN_CMPGEU; goto extract_sfmt_add; }
 334         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 335       case 61:
 336         if ((entire_insn & 0xfc0007ff) == 0xf4000000)
 337           { itype = LM32BF_INSN_CMPGU; goto extract_sfmt_add; }
 338         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 339       case 62: itype = LM32BF_INSN_CALLI; goto extract_sfmt_calli;
 340       case 63:
 341         if ((entire_insn & 0xfc0007ff) == 0xfc000000)
 342           { itype = LM32BF_INSN_CMPNE; goto extract_sfmt_add; }
 343         itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 344       default: itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty;
 345       }
 346     }
 347   }
 348
 349   /* The instruction has been decoded, now extract the fields.  */
 350
 351  extract_sfmt_empty:
 352   {
 353     const IDESC *idesc = &lm32bf_insn_data[itype];
 354 #define FLD(f) abuf->fields.sfmt_empty.f
 355
 356
 357   /* Record the fields for the semantic handler.  */
 358   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
 359
 360 #undef FLD
 361     return idesc;
 362   }
 363
 364  extract_sfmt_add:
 365   {
 366     const IDESC *idesc = &lm32bf_insn_data[itype];
 367     CGEN_INSN_WORD insn = entire_insn;
 368 #define FLD(f) abuf->fields.sfmt_user.f
 369     UINT f_r0;
 370     UINT f_r1;
 371     UINT f_r2;
 372
 373     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 374     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 375     f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
 376
 377   /* Record the fields for the semantic handler.  */
 378   FLD (f_r0) = f_r0;
 379   FLD (f_r1) = f_r1;
 380   FLD (f_r2) = f_r2;
 381   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, (char *) 0));
 382
 383 #undef FLD
 384     return idesc;
 385   }
 386
 387  extract_sfmt_addi:
 388   {
 389     const IDESC *idesc = &lm32bf_insn_data[itype];
 390     CGEN_INSN_WORD insn = entire_insn;
 391 #define FLD(f) abuf->fields.sfmt_addi.f
 392     UINT f_r0;
 393     UINT f_r1;
 394     INT f_imm;
 395
 396     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 397     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 398     f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
 399
 400   /* Record the fields for the semantic handler.  */
 401   FLD (f_imm) = f_imm;
 402   FLD (f_r0) = f_r0;
 403   FLD (f_r1) = f_r1;
 404   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 405
 406 #undef FLD
 407     return idesc;
 408   }
 409
 410  extract_sfmt_andi:
 411   {
 412     const IDESC *idesc = &lm32bf_insn_data[itype];
 413     CGEN_INSN_WORD insn = entire_insn;
 414 #define FLD(f) abuf->fields.sfmt_andi.f
 415     UINT f_r0;
 416     UINT f_r1;
 417     UINT f_uimm;
 418
 419     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 420     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 421     f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
 422
 423   /* Record the fields for the semantic handler.  */
 424   FLD (f_r0) = f_r0;
 425   FLD (f_uimm) = f_uimm;
 426   FLD (f_r1) = f_r1;
 427   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andi", "f_r0 0x%x", 'x', f_r0, "f_uimm 0x%x", 'x', f_uimm, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 428
 429 #undef FLD
 430     return idesc;
 431   }
 432
 433  extract_sfmt_andhii:
 434   {
 435     const IDESC *idesc = &lm32bf_insn_data[itype];
 436     CGEN_INSN_WORD insn = entire_insn;
 437 #define FLD(f) abuf->fields.sfmt_andi.f
 438     UINT f_r0;
 439     UINT f_r1;
 440     UINT f_uimm;
 441
 442     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 443     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 444     f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
 445
 446   /* Record the fields for the semantic handler.  */
 447   FLD (f_uimm) = f_uimm;
 448   FLD (f_r0) = f_r0;
 449   FLD (f_r1) = f_r1;
 450   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andhii", "f_uimm 0x%x", 'x', f_uimm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 451
 452 #undef FLD
 453     return idesc;
 454   }
 455
 456  extract_sfmt_b:
 457   {
 458     const IDESC *idesc = &lm32bf_insn_data[itype];
 459     CGEN_INSN_WORD insn = entire_insn;
 460 #define FLD(f) abuf->fields.sfmt_be.f
 461     UINT f_r0;
 462
 463     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 464
 465   /* Record the fields for the semantic handler.  */
 466   FLD (f_r0) = f_r0;
 467   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_b", "f_r0 0x%x", 'x', f_r0, (char *) 0));
 468
 469 #undef FLD
 470     return idesc;
 471   }
 472
 473  extract_sfmt_bi:
 474   {
 475     const IDESC *idesc = &lm32bf_insn_data[itype];
 476     CGEN_INSN_WORD insn = entire_insn;
 477 #define FLD(f) abuf->fields.sfmt_bi.f
 478     SI f_call;
 479
 480     f_call = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) & (67108863))) << (2))) ^ (134217728))) - (134217728))));
 481
 482   /* Record the fields for the semantic handler.  */
 483   FLD (i_call) = f_call;
 484   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bi", "call 0x%x", 'x', f_call, (char *) 0));
 485
 486 #undef FLD
 487     return idesc;
 488   }
 489
 490  extract_sfmt_be:
 491   {
 492     const IDESC *idesc = &lm32bf_insn_data[itype];
 493     CGEN_INSN_WORD insn = entire_insn;
 494 #define FLD(f) abuf->fields.sfmt_be.f
 495     UINT f_r0;
 496     UINT f_r1;
 497     SI f_branch;
 498
 499     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 500     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 501     f_branch = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) & (65535))) << (2))) ^ (131072))) - (131072))));
 502
 503   /* Record the fields for the semantic handler.  */
 504   FLD (f_r0) = f_r0;
 505   FLD (f_r1) = f_r1;
 506   FLD (i_branch) = f_branch;
 507   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_be", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "branch 0x%x", 'x', f_branch, (char *) 0));
 508
 509 #undef FLD
 510     return idesc;
 511   }
 512
 513  extract_sfmt_call:
 514   {
 515     const IDESC *idesc = &lm32bf_insn_data[itype];
 516     CGEN_INSN_WORD insn = entire_insn;
 517 #define FLD(f) abuf->fields.sfmt_be.f
 518     UINT f_r0;
 519
 520     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 521
 522   /* Record the fields for the semantic handler.  */
 523   FLD (f_r0) = f_r0;
 524   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_call", "f_r0 0x%x", 'x', f_r0, (char *) 0));
 525
 526 #undef FLD
 527     return idesc;
 528   }
 529
 530  extract_sfmt_calli:
 531   {
 532     const IDESC *idesc = &lm32bf_insn_data[itype];
 533     CGEN_INSN_WORD insn = entire_insn;
 534 #define FLD(f) abuf->fields.sfmt_bi.f
 535     SI f_call;
 536
 537     f_call = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) & (67108863))) << (2))) ^ (134217728))) - (134217728))));
 538
 539   /* Record the fields for the semantic handler.  */
 540   FLD (i_call) = f_call;
 541   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_calli", "call 0x%x", 'x', f_call, (char *) 0));
 542
 543 #undef FLD
 544     return idesc;
 545   }
 546
 547  extract_sfmt_divu:
 548   {
 549     const IDESC *idesc = &lm32bf_insn_data[itype];
 550     CGEN_INSN_WORD insn = entire_insn;
 551 #define FLD(f) abuf->fields.sfmt_user.f
 552     UINT f_r0;
 553     UINT f_r1;
 554     UINT f_r2;
 555
 556     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 557     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 558     f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
 559
 560   /* Record the fields for the semantic handler.  */
 561   FLD (f_r0) = f_r0;
 562   FLD (f_r1) = f_r1;
 563   FLD (f_r2) = f_r2;
 564   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_divu", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, (char *) 0));
 565
 566 #undef FLD
 567     return idesc;
 568   }
 569
 570  extract_sfmt_lb:
 571   {
 572     const IDESC *idesc = &lm32bf_insn_data[itype];
 573     CGEN_INSN_WORD insn = entire_insn;
 574 #define FLD(f) abuf->fields.sfmt_addi.f
 575     UINT f_r0;
 576     UINT f_r1;
 577     INT f_imm;
 578
 579     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 580     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 581     f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
 582
 583   /* Record the fields for the semantic handler.  */
 584   FLD (f_imm) = f_imm;
 585   FLD (f_r0) = f_r0;
 586   FLD (f_r1) = f_r1;
 587   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lb", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 588
 589 #undef FLD
 590     return idesc;
 591   }
 592
 593  extract_sfmt_lh:
 594   {
 595     const IDESC *idesc = &lm32bf_insn_data[itype];
 596     CGEN_INSN_WORD insn = entire_insn;
 597 #define FLD(f) abuf->fields.sfmt_addi.f
 598     UINT f_r0;
 599     UINT f_r1;
 600     INT f_imm;
 601
 602     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 603     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 604     f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
 605
 606   /* Record the fields for the semantic handler.  */
 607   FLD (f_imm) = f_imm;
 608   FLD (f_r0) = f_r0;
 609   FLD (f_r1) = f_r1;
 610   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lh", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 611
 612 #undef FLD
 613     return idesc;
 614   }
 615
 616  extract_sfmt_lw:
 617   {
 618     const IDESC *idesc = &lm32bf_insn_data[itype];
 619     CGEN_INSN_WORD insn = entire_insn;
 620 #define FLD(f) abuf->fields.sfmt_addi.f
 621     UINT f_r0;
 622     UINT f_r1;
 623     INT f_imm;
 624
 625     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 626     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 627     f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
 628
 629   /* Record the fields for the semantic handler.  */
 630   FLD (f_imm) = f_imm;
 631   FLD (f_r0) = f_r0;
 632   FLD (f_r1) = f_r1;
 633   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lw", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 634
 635 #undef FLD
 636     return idesc;
 637   }
 638
 639  extract_sfmt_ori:
 640   {
 641     const IDESC *idesc = &lm32bf_insn_data[itype];
 642     CGEN_INSN_WORD insn = entire_insn;
 643 #define FLD(f) abuf->fields.sfmt_andi.f
 644     UINT f_r0;
 645     UINT f_r1;
 646     UINT f_uimm;
 647
 648     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 649     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 650     f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
 651
 652   /* Record the fields for the semantic handler.  */
 653   FLD (f_uimm) = f_uimm;
 654   FLD (f_r0) = f_r0;
 655   FLD (f_r1) = f_r1;
 656   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ori", "f_uimm 0x%x", 'x', f_uimm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 657
 658 #undef FLD
 659     return idesc;
 660   }
 661
 662  extract_sfmt_rcsr:
 663   {
 664     const IDESC *idesc = &lm32bf_insn_data[itype];
 665     CGEN_INSN_WORD insn = entire_insn;
 666 #define FLD(f) abuf->fields.sfmt_rcsr.f
 667     UINT f_csr;
 668     UINT f_r2;
 669
 670     f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 671     f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
 672
 673   /* Record the fields for the semantic handler.  */
 674   FLD (f_csr) = f_csr;
 675   FLD (f_r2) = f_r2;
 676   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rcsr", "f_csr 0x%x", 'x', f_csr, "f_r2 0x%x", 'x', f_r2, (char *) 0));
 677
 678 #undef FLD
 679     return idesc;
 680   }
 681
 682  extract_sfmt_sb:
 683   {
 684     const IDESC *idesc = &lm32bf_insn_data[itype];
 685     CGEN_INSN_WORD insn = entire_insn;
 686 #define FLD(f) abuf->fields.sfmt_addi.f
 687     UINT f_r0;
 688     UINT f_r1;
 689     INT f_imm;
 690
 691     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 692     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 693     f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
 694
 695   /* Record the fields for the semantic handler.  */
 696   FLD (f_imm) = f_imm;
 697   FLD (f_r0) = f_r0;
 698   FLD (f_r1) = f_r1;
 699   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sb", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 700
 701 #undef FLD
 702     return idesc;
 703   }
 704
 705  extract_sfmt_sextb:
 706   {
 707     const IDESC *idesc = &lm32bf_insn_data[itype];
 708     CGEN_INSN_WORD insn = entire_insn;
 709 #define FLD(f) abuf->fields.sfmt_user.f
 710     UINT f_r0;
 711     UINT f_r2;
 712
 713     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 714     f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
 715
 716   /* Record the fields for the semantic handler.  */
 717   FLD (f_r0) = f_r0;
 718   FLD (f_r2) = f_r2;
 719   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sextb", "f_r0 0x%x", 'x', f_r0, "f_r2 0x%x", 'x', f_r2, (char *) 0));
 720
 721 #undef FLD
 722     return idesc;
 723   }
 724
 725  extract_sfmt_sh:
 726   {
 727     const IDESC *idesc = &lm32bf_insn_data[itype];
 728     CGEN_INSN_WORD insn = entire_insn;
 729 #define FLD(f) abuf->fields.sfmt_addi.f
 730     UINT f_r0;
 731     UINT f_r1;
 732     INT f_imm;
 733
 734     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 735     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 736     f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
 737
 738   /* Record the fields for the semantic handler.  */
 739   FLD (f_imm) = f_imm;
 740   FLD (f_r0) = f_r0;
 741   FLD (f_r1) = f_r1;
 742   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sh", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 743
 744 #undef FLD
 745     return idesc;
 746   }
 747
 748  extract_sfmt_sw:
 749   {
 750     const IDESC *idesc = &lm32bf_insn_data[itype];
 751     CGEN_INSN_WORD insn = entire_insn;
 752 #define FLD(f) abuf->fields.sfmt_addi.f
 753     UINT f_r0;
 754     UINT f_r1;
 755     INT f_imm;
 756
 757     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 758     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 759     f_imm = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
 760
 761   /* Record the fields for the semantic handler.  */
 762   FLD (f_imm) = f_imm;
 763   FLD (f_r0) = f_r0;
 764   FLD (f_r1) = f_r1;
 765   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sw", "f_imm 0x%x", 'x', f_imm, "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 766
 767 #undef FLD
 768     return idesc;
 769   }
 770
 771  extract_sfmt_user:
 772   {
 773     const IDESC *idesc = &lm32bf_insn_data[itype];
 774     CGEN_INSN_WORD insn = entire_insn;
 775 #define FLD(f) abuf->fields.sfmt_user.f
 776     UINT f_r0;
 777     UINT f_r1;
 778     UINT f_r2;
 779     UINT f_user;
 780
 781     f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 782     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 783     f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
 784     f_user = EXTRACT_LSB0_UINT (insn, 32, 10, 11);
 785
 786   /* Record the fields for the semantic handler.  */
 787   FLD (f_r0) = f_r0;
 788   FLD (f_r1) = f_r1;
 789   FLD (f_user) = f_user;
 790   FLD (f_r2) = f_r2;
 791   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_user", "f_r0 0x%x", 'x', f_r0, "f_r1 0x%x", 'x', f_r1, "f_user 0x%x", 'x', f_user, "f_r2 0x%x", 'x', f_r2, (char *) 0));
 792
 793 #undef FLD
 794     return idesc;
 795   }
 796
 797  extract_sfmt_wcsr:
 798   {
 799     const IDESC *idesc = &lm32bf_insn_data[itype];
 800     CGEN_INSN_WORD insn = entire_insn;
 801 #define FLD(f) abuf->fields.sfmt_wcsr.f
 802     UINT f_csr;
 803     UINT f_r1;
 804
 805     f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
 806     f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
 807
 808   /* Record the fields for the semantic handler.  */
 809   FLD (f_csr) = f_csr;
 810   FLD (f_r1) = f_r1;
 811   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_wcsr", "f_csr 0x%x", 'x', f_csr, "f_r1 0x%x", 'x', f_r1, (char *) 0));
 812
 813 #undef FLD
 814     return idesc;
 815   }
 816
 817  extract_sfmt_break:
 818   {
 819     const IDESC *idesc = &lm32bf_insn_data[itype];
 820 #define FLD(f) abuf->fields.sfmt_empty.f
 821
 822
 823   /* Record the fields for the semantic handler.  */
 824   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_break", (char *) 0));
 825
 826 #undef FLD
 827     return idesc;
 828   }
 829
 830 }