sim/lm32/dv-lm32cpu.c

   1 /*  Lattice Mico32 CPU model.
   2     Contributed by Jon Beniston <jon@beniston.com>
   3
   4    Copyright (C) 2009-2024 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #define WANT_CPU lm32bf
  22 #define WANT_CPU_LM32BF
  23
  24 /* This must come before any other includes.  */
  25 #include "defs.h"
  26
  27 #include "hw-main.h"
  28 #include "sim-main.h"
  29
  30
  31 struct lm32cpu
  32 {
  33   struct hw_event *event;
  34 };
  35
  36 /* input port ID's.  */
  37
  38 enum
  39 {
  40   INT0_PORT,
  41   INT1_PORT,
  42   INT2_PORT,
  43   INT3_PORT,
  44   INT4_PORT,
  45   INT5_PORT,
  46   INT6_PORT,
  47   INT7_PORT,
  48   INT8_PORT,
  49   INT9_PORT,
  50   INT10_PORT,
  51   INT11_PORT,
  52   INT12_PORT,
  53   INT13_PORT,
  54   INT14_PORT,
  55   INT15_PORT,
  56   INT16_PORT,
  57   INT17_PORT,
  58   INT18_PORT,
  59   INT19_PORT,
  60   INT20_PORT,
  61   INT21_PORT,
  62   INT22_PORT,
  63   INT23_PORT,
  64   INT24_PORT,
  65   INT25_PORT,
  66   INT26_PORT,
  67   INT27_PORT,
  68   INT28_PORT,
  69   INT29_PORT,
  70   INT30_PORT,
  71   INT31_PORT,
  72 };
  73
  74 static const struct hw_port_descriptor lm32cpu_ports[] = {
  75   /* interrupt inputs.  */
  76   {"int0", INT0_PORT, 0, input_port,},
  77   {"int1", INT1_PORT, 0, input_port,},
  78   {"int2", INT2_PORT, 0, input_port,},
  79   {"int3", INT3_PORT, 0, input_port,},
  80   {"int4", INT4_PORT, 0, input_port,},
  81   {"int5", INT5_PORT, 0, input_port,},
  82   {"int6", INT6_PORT, 0, input_port,},
  83   {"int7", INT7_PORT, 0, input_port,},
  84   {"int8", INT8_PORT, 0, input_port,},
  85   {"int9", INT9_PORT, 0, input_port,},
  86   {"int10", INT10_PORT, 0, input_port,},
  87   {"int11", INT11_PORT, 0, input_port,},
  88   {"int12", INT12_PORT, 0, input_port,},
  89   {"int13", INT13_PORT, 0, input_port,},
  90   {"int14", INT14_PORT, 0, input_port,},
  91   {"int15", INT15_PORT, 0, input_port,},
  92   {"int16", INT16_PORT, 0, input_port,},
  93   {"int17", INT17_PORT, 0, input_port,},
  94   {"int18", INT18_PORT, 0, input_port,},
  95   {"int19", INT19_PORT, 0, input_port,},
  96   {"int20", INT20_PORT, 0, input_port,},
  97   {"int21", INT21_PORT, 0, input_port,},
  98   {"int22", INT22_PORT, 0, input_port,},
  99   {"int23", INT23_PORT, 0, input_port,},
 100   {"int24", INT24_PORT, 0, input_port,},
 101   {"int25", INT25_PORT, 0, input_port,},
 102   {"int26", INT26_PORT, 0, input_port,},
 103   {"int27", INT27_PORT, 0, input_port,},
 104   {"int28", INT28_PORT, 0, input_port,},
 105   {"int29", INT29_PORT, 0, input_port,},
 106   {"int30", INT30_PORT, 0, input_port,},
 107   {"int31", INT31_PORT, 0, input_port,},
 108   {NULL,},
 109 };
 110
 111
 112
 113 /*
 114  * Finish off the partially created hw device.  Attach our local
 115  * callbacks.  Wire up our port names etc.
 116  */
 117 static hw_port_event_method lm32cpu_port_event;
 118
 119
 120 static void
 121 lm32cpu_finish (struct hw *me)
 122 {
 123   struct lm32cpu *controller;
 124
 125   controller = HW_ZALLOC (me, struct lm32cpu);
 126   set_hw_data (me, controller);
 127   set_hw_ports (me, lm32cpu_ports);
 128   set_hw_port_event (me, lm32cpu_port_event);
 129
 130   /* Initialize the pending interrupt flags.  */
 131   controller->event = NULL;
 132 }
 133
 134
 135 /* An event arrives on an interrupt port.  */
 136 static unsigned int s_ui_ExtIntrs = 0;
 137
 138
 139 static void
 140 deliver_lm32cpu_interrupt (struct hw *me, void *data)
 141 {
 142   static unsigned int ip, im, im_and_ip_result;
 143   struct lm32cpu *controller = hw_data (me);
 144   SIM_DESC sd = hw_system (me);
 145   sim_cpu *cpu = STATE_CPU (sd, 0);     /* NB: fix CPU 0.  */
 146
 147
 148   HW_TRACE ((me, "interrupt-check event"));
 149
 150
 151   /*
 152    * Determine if an external interrupt is active
 153    * and needs to cause an exception.
 154    */
 155   im = lm32bf_h_csr_get (cpu, LM32_CSR_IM);
 156   ip = lm32bf_h_csr_get (cpu, LM32_CSR_IP);
 157   im_and_ip_result = im & ip;
 158
 159
 160   if ((lm32bf_h_csr_get (cpu, LM32_CSR_IE) & 1) && (im_and_ip_result != 0))
 161     {
 162       /* Save PC in exception address register.  */
 163       lm32bf_h_gr_set (cpu, 30, lm32bf_h_pc_get (cpu));
 164       /* Restart at interrupt offset in handler exception table.  */
 165       lm32bf_h_pc_set (cpu,
 166                        lm32bf_h_csr_get (cpu,
 167                                          LM32_CSR_EBA) +
 168                        LM32_EID_INTERRUPT * 32);
 169       /* Save interrupt enable and then clear.  */
 170       lm32bf_h_csr_set (cpu, LM32_CSR_IE, 0x2);
 171     }
 172
 173   /* reschedule soon.  */
 174   if (controller->event != NULL)
 175     hw_event_queue_deschedule (me, controller->event);
 176   controller->event = NULL;
 177
 178
 179   /* if there are external interrupts, schedule an interrupt-check again.
 180    * NOTE: THIS MAKES IT VERY INEFFICIENT. INSTEAD, TRIGGER THIS
 181    * CHECk_EVENT WHEN THE USER ENABLES IE OR USER MODIFIES IM REGISTERS.
 182    */
 183   if (s_ui_ExtIntrs != 0)
 184     controller->event =
 185       hw_event_queue_schedule (me, 1, deliver_lm32cpu_interrupt, data);
 186 }
 187
 188
 189
 190 /* Handle an event on one of the CPU's ports.  */
 191 static void
 192 lm32cpu_port_event (struct hw *me,
 193                     int my_port,
 194                     struct hw *source, int source_port, int level)
 195 {
 196   struct lm32cpu *controller = hw_data (me);
 197   SIM_DESC sd = hw_system (me);
 198   sim_cpu *cpu = STATE_CPU (sd, 0);     /* NB: fix CPU 0.  */
 199
 200
 201   HW_TRACE ((me, "interrupt event on port %d, level %d", my_port, level));
 202
 203
 204
 205   /*
 206    * Activate IP if the interrupt's activated; don't do anything if
 207    * the interrupt's deactivated.
 208    */
 209   if (level == 1)
 210     {
 211       /*
 212        * save state of external interrupt.
 213        */
 214       s_ui_ExtIntrs |= (1 << my_port);
 215
 216       /* interrupt-activated so set IP.  */
 217       lm32bf_h_csr_set (cpu, LM32_CSR_IP,
 218                         lm32bf_h_csr_get (cpu, LM32_CSR_IP) | (1 << my_port));
 219
 220       /*
 221        * Since interrupt is activated, queue an immediate event
 222        * to check if this interrupt is serviceable.
 223        */
 224       if (controller->event != NULL)
 225         hw_event_queue_deschedule (me, controller->event);
 226
 227
 228       /*
 229        * Queue an immediate event to check if this interrupt must be serviced;
 230        * this will happen after the current instruction is complete.
 231        */
 232       controller->event = hw_event_queue_schedule (me,
 233                                                    0,
 234                                                    deliver_lm32cpu_interrupt,
 235                                                    0);
 236     }
 237   else
 238     {
 239       /*
 240        * save state of external interrupt.
 241        */
 242       s_ui_ExtIntrs &= ~(1 << my_port);
 243     }
 244 }
 245
 246
 247 const struct hw_descriptor dv_lm32cpu_descriptor[] = {
 248   {"lm32cpu", lm32cpu_finish,},
 249   {NULL},
 250 };