sim/m32r/m32r-sim.h

   1 /* collection of junk waiting time to sort out
   2    Copyright (C) 1996-2024 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef M32R_SIM_H
  21 #define M32R_SIM_H
  22
  23 #include "symcat.h"
  24
  25 /* GDB register numbers.  */
  26 #define PSW_REGNUM      16
  27 #define CBR_REGNUM      17
  28 #define SPI_REGNUM      18
  29 #define SPU_REGNUM      19
  30 #define BPC_REGNUM      20
  31 #define PC_REGNUM       21
  32 #define ACCL_REGNUM     22
  33 #define ACCH_REGNUM     23
  34 #define ACC1L_REGNUM    24
  35 #define ACC1H_REGNUM    25
  36 #define BBPSW_REGNUM    26
  37 #define BBPC_REGNUM     27
  38 #define EVB_REGNUM      28
  39
  40 extern int m32r_decode_gdb_ctrl_regnum (int);
  41
  42 /* The other cpu cores reuse m32rbf funcs to avoid duplication, but they don't
  43    provide externs to access, and we can't e.g. include decode.h in decodex.h
  44    because of all the redefinitions of cgen macros.  */
  45
  46 extern void m32rbf_model_insn_before (SIM_CPU *, int);
  47 extern void m32rbf_model_insn_after (SIM_CPU *, int, int);
  48 extern CPUREG_FETCH_FN m32rbf_fetch_register;
  49 extern CPUREG_STORE_FN m32rbf_store_register;
  50 extern UQI  m32rbf_h_psw_get (SIM_CPU *);
  51 extern void m32rbf_h_psw_set (SIM_CPU *, UQI);
  52 extern UQI  m32r2f_h_psw_get (SIM_CPU *);
  53 extern void m32r2f_h_psw_set (SIM_CPU *, UQI);
  54 extern UQI  m32rxf_h_psw_get (SIM_CPU *);
  55 extern void m32rxf_h_psw_set (SIM_CPU *, UQI);
  56 extern void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
  57 extern void m32r2f_h_bpsw_set (SIM_CPU *, UQI);
  58 extern void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
  59 extern SI   m32rbf_h_gr_get (SIM_CPU *, UINT);
  60 extern void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  61 extern USI  m32rbf_h_cr_get (SIM_CPU *, UINT);
  62 extern void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  63
  64 /* Cover macros for hardware accesses.
  65    FIXME: Eventually move to cgen.  */
  66 #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
  67
  68 extern USI  m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
  69 extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
  70 extern USI  m32r2f_h_cr_get_handler (SIM_CPU *, UINT);
  71 extern void m32r2f_h_cr_set_handler (SIM_CPU *, UINT, USI);
  72 extern USI  m32rxf_h_cr_get_handler (SIM_CPU *, UINT);
  73 extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI);
  74
  75 #ifndef GET_H_CR
  76 #define GET_H_CR(regno) \
  77   XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
  78 #define SET_H_CR(regno, val) \
  79   XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
  80 #endif
  81
  82 extern UQI  m32rbf_h_psw_get_handler (SIM_CPU *);
  83 extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
  84 extern UQI  m32r2f_h_psw_get_handler (SIM_CPU *);
  85 extern void m32r2f_h_psw_set_handler (SIM_CPU *, UQI);
  86 extern UQI  m32rxf_h_psw_get_handler (SIM_CPU *);
  87 extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI);
  88
  89 #ifndef  GET_H_PSW
  90 #define GET_H_PSW() \
  91   XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
  92 #define SET_H_PSW(val) \
  93   XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
  94 #endif
  95
  96 /* FIXME: These prototypes are necessary because the cgen generated
  97    cpu.h, cpux.h and cpu2.h headers do not provide them, and functions
  98    which take or return parameters that are larger than an int must be
  99    prototyed in order for them to work correctly.
 100
 101    The correct solution is to fix the code in cgen/sim.scm to generate
 102    prototypes for each of the functions it generates.  */
 103 extern DI   m32rbf_h_accum_get_handler (SIM_CPU *);
 104 extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
 105 extern DI   m32r2f_h_accum_get_handler (SIM_CPU *);
 106 extern void m32r2f_h_accum_set_handler (SIM_CPU *, DI);
 107 extern DI   m32rxf_h_accum_get_handler (SIM_CPU *);
 108 extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI);
 109
 110 extern DI   m32r2f_h_accums_get_handler (SIM_CPU *, UINT);
 111 extern void m32r2f_h_accums_set_handler (SIM_CPU *, UINT, DI);
 112 extern DI   m32rxf_h_accums_get_handler (SIM_CPU *, UINT);
 113 extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI);
 114
 115 #ifndef  GET_H_ACCUM
 116 #define GET_H_ACCUM() \
 117   XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
 118 #define SET_H_ACCUM(val) \
 119   XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
 120 #endif
 121 \f
 122 /* Misc. profile data.  */
 123
 124 typedef struct {
 125   /* nop insn slot filler count */
 126   unsigned int fillnop_count;
 127   /* number of parallel insns */
 128   unsigned int parallel_count;
 129
 130   /* FIXME: generalize this to handle all insn lengths, move to common.  */
 131   /* number of short insns, not including parallel ones */
 132   unsigned int short_count;
 133   /* number of long insns */
 134   unsigned int long_count;
 135
 136   /* Working area for computing cycle counts.  */
 137   unsigned long insn_cycles; /* FIXME: delete */
 138   unsigned long cti_stall;
 139   unsigned long load_stall;
 140   unsigned long biggest_cycles;
 141
 142   /* Bitmask of registers loaded by previous insn.  */
 143   unsigned int load_regs;
 144   /* Bitmask of registers loaded by current insn.  */
 145   unsigned int load_regs_pending;
 146 } M32R_MISC_PROFILE;
 147
 148 /* Initialize the working area.  */
 149 void m32r_init_insn_cycles (SIM_CPU *, int);
 150 /* Update the totals for the insn.  */
 151 void m32r_record_insn_cycles (SIM_CPU *, int);
 152
 153 /* This is invoked by the nop pattern in the .cpu file.  */
 154 #define PROFILE_COUNT_FILLNOPS(cpu, addr) \
 155 do { \
 156   if (PROFILE_INSN_P (cpu) \
 157       && (addr & 3) != 0) \
 158     ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
 159 } while (0)
 160
 161 /* This is invoked by the execute section of mloop{,x}.in.  */
 162 #define PROFILE_COUNT_PARINSNS(cpu) \
 163 do { \
 164   if (PROFILE_INSN_P (cpu)) \
 165     ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
 166 } while (0)
 167
 168 /* This is invoked by the execute section of mloop{,x}.in.  */
 169 #define PROFILE_COUNT_SHORTINSNS(cpu) \
 170 do { \
 171   if (PROFILE_INSN_P (cpu)) \
 172     ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
 173 } while (0)
 174
 175 /* This is invoked by the execute section of mloop{,x}.in.  */
 176 #define PROFILE_COUNT_LONGINSNS(cpu) \
 177 do { \
 178   if (PROFILE_INSN_P (cpu)) \
 179     ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
 180 } while (0)
 181 \f
 182 #define GETTWI GETTSI
 183 #define SETTWI SETTSI
 184 \f
 185 /* Additional execution support.  */
 186
 187 \f
 188 /* Hardware/device support.
 189    ??? Will eventually want to move device stuff to config files.  */
 190
 191 /* Exception, Interrupt, and Trap addresses */
 192 #define EIT_SYSBREAK_ADDR       0x10
 193 #define EIT_RSVD_INSN_ADDR      0x20
 194 #define EIT_ADDR_EXCP_ADDR      0x30
 195 #define EIT_TRAP_BASE_ADDR      0x40
 196 #define EIT_EXTERN_ADDR         0x80
 197 #define EIT_RESET_ADDR          0x7ffffff0
 198 #define EIT_WAKEUP_ADDR         0x7ffffff0
 199
 200 /* Special purpose traps.  */
 201 #define TRAP_SYSCALL    0
 202 #define TRAP_BREAKPOINT 1
 203
 204 /* Handle the trap insn.  */
 205 USI m32r_trap (SIM_CPU *, PCADDR, int);
 206 \f
 207 struct m32r_sim_cpu {
 208   M32R_MISC_PROFILE m32r_misc_profile;
 209 #define CPU_M32R_MISC_PROFILE(cpu) (& M32R_SIM_CPU (cpu)->m32r_misc_profile)
 210
 211   /* CPU specific parts go here.
 212      Note that in files that don't need to access these pieces WANT_CPU_FOO
 213      won't be defined and thus these parts won't appear.  This is ok in the
 214      sense that things work.  It is a source of bugs though.
 215      One has to of course be careful to not take the size of this
 216      struct and no structure members accessed in non-cpu specific files can
 217      go after here.  Oh for a better language.  */
 218 #if defined (WANT_CPU_M32RBF)
 219   M32RBF_CPU_DATA cpu_data;
 220 #endif
 221 #if defined (WANT_CPU_M32RXF)
 222   M32RXF_CPU_DATA cpu_data;
 223 #elif defined (WANT_CPU_M32R2F)
 224   M32R2F_CPU_DATA cpu_data;
 225 #endif
 226 };
 227 #define M32R_SIM_CPU(cpu) ((struct m32r_sim_cpu *) CPU_ARCH_DATA (cpu))
 228
 229 #endif /* M32R_SIM_H */