sim/mips/micromips.igen

   1 // Simulator definition for the micromips ASE.
   2 // Copyright (C) 2005-2024 Free Software Foundation, Inc.
   3 // Contributed by Imagination Technologies, Ltd.
   4 // Written by Andrew Bennett <andrew.bennett@imgtec.com>
   5 //
   6 // This file is part of the MIPS sim.
   7 //
   8 // This program is free software; you can redistribute it and/or modify
   9 // it under the terms of the GNU General Public License as published by
  10 // the Free Software Foundation; either version 3 of the License, or
  11 // (at your option) any later version.
  12 //
  13 // This program is distributed in the hope that it will be useful,
  14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 // GNU General Public License for more details.
  17 //
  18 // You should have received a copy of the GNU General Public License
  19 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20
  21 :compute:::int:TBASE:BASE:((BASE < 2) ? (16 + BASE) \: BASE)
  22 :compute:::int:TRD:RD:((RD < 2) ? (16 + RD) \: RD)
  23 :compute:::int:TRS:RS:((RS < 2) ? (16 + RS) \: RS)
  24 :compute:::int:TRT:RT:((RT < 2) ? (16 + RT) \: RT)
  25 :compute:::int:TRT_S:RT_S:((RT_S == 1 ) ? 17 \: RT_S)
  26 :compute:::int:ERT:RT:(compute_movep_src_reg (SD_, RT))
  27 :compute:::int:ERS:RS:(compute_movep_src_reg (SD_, RS))
  28
  29 :compute:::int:IMM_DEC1:IMMEDIATE:((IMMEDIATE == 7) ? -1 \: ((IMMEDIATE == 0) ? 1 \: IMMEDIATE << 2))
  30 :compute:::int:IMM_DEC2:IMMEDIATE:((IMMEDIATE < 8) ? IMMEDIATE \: (IMMEDIATE - 16))
  31 :compute:::int:IMM_DEC3:IMMEDIATE:((IMMEDIATE < 2) ? IMMEDIATE + 256 \: ((IMMEDIATE < 256) ? IMMEDIATE \: ((IMMEDIATE < 510) ? IMMEDIATE - 512 \: IMMEDIATE - 768)))
  32 :compute:::int:IMM_DEC4:IMMEDIATE:(compute_andi16_imm (SD_, IMMEDIATE))
  33 :compute:::int:IMM_DEC5:IMMEDIATE:((IMMEDIATE < 15) ? IMMEDIATE \: -1)
  34 :compute:::int:IMM_DEC6:IMMEDIATE:((IMMEDIATE < 127) ? IMMEDIATE \: -1)
  35
  36 :compute:::int:SHIFT_DEC:SHIFT:((SHIFT == 0) ? 8 \: SHIFT)
  37
  38 :compute:::int:IMM_SHIFT_1BIT:IMMEDIATE:(IMMEDIATE << 1)
  39 :compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
  40
  41 :function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
  42 *micromips32:
  43 *micromips64:
  44 *micromipsdsp:
  45 {
  46   instruction_word delay_insn;
  47   sim_events_slip (SD, 1);
  48   DSPC = CIA;
  49   CIA = nia;
  50   STATE |= simDELAYSLOT;
  51   ENGINE_ISSUE_PREFIX_HOOK();
  52   micromips_instruction_decode (SD, CPU, CIA, delayslot_instruction_size);
  53   STATE &= ~simDELAYSLOT;
  54   return target;
  55 }
  56
  57 :function:::address_word:process_isa_mode:address_word target
  58 *micromips32:
  59 *micromips64:
  60 {
  61   struct mips_sim_state *state = MIPS_SIM_STATE (SD);
  62   state->isa_mode = target & 0x1;
  63   return (target & (-(1 << 1)));
  64 }
  65
  66 :function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
  67 *micromips32:
  68 *micromips64:
  69 {
  70   GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
  71   return (process_isa_mode (SD_,
  72         delayslot_micromips (SD_, GPR[rs], nia, delayslot_instruction_size)));
  73 }
  74
  75 :function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
  76 *micromips32:
  77 *micromips64:
  78 {
  79   RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
  80   return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
  81 }
  82
  83
  84 :function:::uint32_t:compute_movep_src_reg:int reg
  85 *micromips32:
  86 *micromips64:
  87 {
  88   switch (reg)
  89     {
  90     case 0: return 0;
  91     case 1: return 17;
  92     case 2: return 2;
  93     case 3: return 3;
  94     case 4: return 16;
  95     case 5: return 18;
  96     case 6: return 19;
  97     case 7: return 20;
  98     default: return 0;
  99     }
 100 }
 101
 102 :function:::uint32_t:compute_andi16_imm:int encoded_imm
 103 *micromips32:
 104 *micromips64:
 105 {
 106   switch (encoded_imm)
 107     {
 108     case 0: return 128;
 109     case 1: return 1;
 110     case 2: return 2;
 111     case 3: return 3;
 112     case 4: return 4;
 113     case 5: return 7;
 114     case 6: return 8;
 115     case 7: return 15;
 116     case 8: return 16;
 117     case 9: return 31;
 118     case 10: return 32;
 119     case 11: return 63;
 120     case 12: return 64;
 121     case 13: return 255;
 122     case 14: return 32768;
 123     case 15: return 65535;
 124     default: return 0;
 125     }
 126 }
 127
 128 :function:::FP_formats:convert_fmt_micromips:int fmt
 129 *micromips32:
 130 *micromips64:
 131 {
 132   switch (fmt)
 133     {
 134     case 0: return fmt_single;
 135     case 1: return fmt_double;
 136     case 2: return fmt_ps;
 137     default: return fmt_unknown;
 138     }
 139 }
 140
 141 :function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
 142 *micromips32:
 143 *micromips64:
 144 {
 145   switch (fmt)
 146     {
 147     case 0: return fmt_single;
 148     case 1: return fmt_word;
 149     case 2: return fmt_long;
 150     default: return fmt_unknown;
 151     }
 152 }
 153
 154
 155 :function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
 156 *micromips32:
 157 *micromips64:
 158 {
 159   switch (fmt)
 160     {
 161     case 0: return fmt_double;
 162     case 1: return fmt_word;
 163     case 2: return fmt_long;
 164     default: return fmt_unknown;
 165     }
 166 }
 167
 168
 169 011011,3.RD,6.IMMEDIATE,1:POOL16E:16::ADDIUR1SP
 170 "addiur1sp r<TRD>, <IMMEDIATE>"
 171 *micromips32:
 172 *micromips64:
 173 {
 174   do_addiu (SD_, SPIDX, TRD, IMMEDIATE << 2);
 175 }
 176
 177
 178 011011,3.RD,3.RS,3.IMMEDIATE,0:POOL16E:16::ADDIUR2
 179 "addiur2 r<TRD>, r<TRS>, <IMM_DEC1>"
 180 *micromips32:
 181 *micromips64:
 182 {
 183   do_addiu (SD_, TRS, TRD, IMM_DEC1);
 184 }
 185
 186
 187 010011,5.RD,4.IMMEDIATE,0:POOL16D:16::ADDIUS5
 188 "addius5 r<RD>, <IMM_DEC2>"
 189 *micromips32:
 190 *micromips64:
 191 {
 192   do_addiu (SD_, RD, RD, IMM_DEC2);
 193 }
 194
 195
 196 010011,9.IMMEDIATE,1:POOL16D:16::ADDIUSP
 197 "addiusp <IMM_DEC3>"
 198 *micromips32:
 199 *micromips64:
 200 {
 201   do_addiu (SD_, SPIDX, SPIDX, IMM_DEC3 << 2);
 202 }
 203
 204
 205 000001,3.RD,3.RT,3.RS,0:POOL16A:16::ADDU16
 206 "addu16 r<TRD>, r<TRS>, r<TRT>"
 207 *micromips32:
 208 *micromips64:
 209 {
 210   do_addu (SD_, TRS, TRT, TRD);
 211 }
 212
 213
 214 001011,3.RD,3.RS,4.IMMEDIATE:MICROMIPS:16::ANDI16
 215 "andi16 r<TRD>, r<TRS>, <IMM_DEC4>"
 216 *micromips32:
 217 *micromips64:
 218 {
 219   do_andi (SD_, TRS, TRD, IMM_DEC4);
 220 }
 221
 222
 223 010001,0010,3.RT,3.RS:POOL16C:16::AND16
 224 "and16 r<TRT>, r<TRS>"
 225 *micromips32:
 226 *micromips64:
 227 {
 228   do_and (SD_, TRS, TRT, TRT);
 229 }
 230
 231
 232 110011,10.IMMEDIATE:MICROMIPS:16::B16
 233 "b16 <IMMEDIATE>"
 234 *micromips32:
 235 *micromips64:
 236 {
 237   NIA = delayslot_micromips (SD_, NIA + (EXTEND11 (IMMEDIATE << 1)),
 238                                   NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 239 }
 240
 241
 242 100011,3.RS,7.IMMEDIATE:MICROMIPS:16::BEQZ16
 243 "beqz16 r<TRS>, <IMMEDIATE>"
 244 *micromips32:
 245 *micromips64:
 246 {
 247   if (GPR[TRS] == 0)
 248     NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),
 249                                     NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 250 }
 251
 252
 253 101011,3.RS,7.IMMEDIATE:MICROMIPS:16::BNEZ16
 254 "bnez16 r<TRS>, <IMMEDIATE>"
 255 *micromips32:
 256 *micromips64:
 257 {
 258   if (GPR[TRS] != 0)
 259     NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),
 260                                     NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 261 }
 262
 263
 264 010001,101000,4.CODE:POOL16C:16::BREAK16
 265 "break16 %#lx<CODE>"
 266 *micromips32:
 267 *micromips64:
 268 {
 269   do_break16 (SD_, instruction_0);
 270 }
 271
 272
 273 010001,01110,5.RS:POOL16C:16::JALR16
 274 "jalr16 r<RS>"
 275 *micromips32:
 276 *micromips64:
 277 {
 278   NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
 279 }
 280
 281
 282 010001,01111,5.RS:POOL16C:16::JALRS16
 283 "jalrs16 r<RS>"
 284 *micromips32:
 285 *micromips64:
 286 {
 287   NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
 288 }
 289
 290
 291 010001,01100,5.RS:POOL16C:16::JR16
 292 "jr16 r<RS>"
 293 *micromips32:
 294 *micromips64:
 295 {
 296   NIA = process_isa_mode (SD_,
 297         delayslot_micromips (SD_, GPR[RS], NIA, MICROMIPS_DELAYSLOT_SIZE_ANY));
 298 }
 299
 300
 301 010001,11000,5.IMMEDIATE:POOL16C:16::JRADDIUSP
 302 "jraddiusp <IMMEDIATE>"
 303 *micromips32:
 304 *micromips64:
 305 {
 306   address_word temp = RA;
 307   do_addiu (SD_, SPIDX, SPIDX, IMMEDIATE << 2);
 308   NIA = process_isa_mode (SD_, temp);
 309 }
 310
 311
 312 010001,01101,5.RS:POOL16C:16::JRC
 313 "jrc r<RS>"
 314 *micromips32:
 315 *micromips64:
 316 {
 317   NIA = process_isa_mode (SD_, GPR[RS]);
 318 }
 319
 320
 321 000010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LBU16
 322 "lbu16 r<TRT>, <IMM_DEC5>(r<TBASE>)"
 323 *micromips32:
 324 *micromips64:
 325 {
 326   /* LBU can have a negative offset.  As the offset argument to do_load is
 327      unsigned we need to do the address calcuation before the function call so
 328      that the load address has been correctly calculated */
 329
 330   GPR[TRT] = do_load (SD_, AccessLength_BYTE, GPR[TBASE] + IMM_DEC5, 0);
 331 }
 332
 333
 334 001010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LHU16
 335 "lhu16 r<TRT>, <IMM_SHIFT_1BIT>(r<TBASE>)"
 336 *micromips32:
 337 *micromips64:
 338 {
 339   GPR[TRT] = do_load (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT);
 340 }
 341
 342
 343 111011,3.RD,7.IMMEDIATE:MICROMIPS:16::LI16
 344 "li16 r<TRD>, <IMM_DEC6>"
 345 *micromips32:
 346 *micromips64:
 347 {
 348   GPR[TRD] = IMM_DEC6;
 349 }
 350
 351
 352 011010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LW16
 353 "lw16 r<TRT>, <IMM_SHIFT_2BIT>(r<TBASE>)"
 354 *micromips32:
 355 *micromips64:
 356 {
 357   GPR[TRT] = EXTEND32 (
 358         do_load (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT));
 359 }
 360
 361 :%s::::LWMREGS:int lwmregs
 362 *micromips32:
 363 *micromips64:
 364 {
 365   if (lwmregs == 3)
 366     return "s0, s1, s2, s3, ra";
 367   else if (lwmregs == 2)
 368     return "s0, s1, s2, ra";
 369   else if (lwmregs == 1)
 370     return "s0, s1, ra";
 371   else if (lwmregs == 0)
 372     return "s0, ra";
 373   else
 374     return "";
 375 }
 376
 377 010001,0100,2.LWMREGS,4.IMMEDIATE:POOL16C:16::LWM16
 378 "lwm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"
 379 *micromips32:
 380 *micromips64:
 381 {
 382   int address = GPR[SPIDX] + IMM_SHIFT_2BIT;
 383   int reg_offset;
 384
 385   for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)
 386     GPR[16 + reg_offset] = EXTEND32 (
 387         do_load (SD_, AccessLength_WORD, address, reg_offset * 4));
 388
 389   RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address, reg_offset * 4));
 390 }
 391
 392
 393 011001,3.RT,7.IMMEDIATE:MICROMIPS:16::LWGP
 394 "lwgp r<TRT>, <IMM_SHIFT_2BIT>(gp)"
 395 *micromips32:
 396 *micromips64:
 397 {
 398   GPR[TRT] = EXTEND32 (
 399         do_load (SD_, AccessLength_WORD, GPR[28], IMM_SHIFT_2BIT));
 400 }
 401
 402
 403 010010,5.RT,5.IMMEDIATE:MICROMIPS:16::LWSP
 404 "lwsp r<RT>, <IMM_SHIFT_2BIT>(sp)"
 405 *micromips32:
 406 *micromips64:
 407 {
 408   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT));
 409 }
 410
 411
 412 010001,10000,5.RD:POOL16C:16::MFHI16
 413 "mfhi16 r<RD>"
 414 *micromips32:
 415 *micromips64:
 416 {
 417   do_mfhi (SD_, RD);
 418 }
 419
 420
 421 010001,10010,5.RD:POOL16C:16::MFLO16
 422 "mflo16 r<RD>"
 423 *micromips32:
 424 *micromips64:
 425 {
 426   do_mflo (SD_, RD);
 427 }
 428
 429
 430 000011,5.RD,5.RS:MICROMIPS:16::MOVE16
 431 "nop":RD==0&&RS==0
 432 "move16 r<RD>, r<RS>"
 433 *micromips32:
 434 *micromips64:
 435 {
 436   GPR[RD] = GPR[RS];
 437 }
 438
 439
 440 :%s::::DESTREGS:int regs
 441 *micromips32:
 442 *micromips64:
 443 {
 444   switch (regs)
 445     {
 446     case 0: return "a1, a2,";
 447     case 1: return "a1, a3,";
 448     case 2: return "a2, a3,";
 449     case 3: return "a0, s5,";
 450     case 4: return "a0, s6,";
 451     case 5: return "a0, a1,";
 452     case 6: return "a0, a2,";
 453     case 7: return "a0, a3,";
 454     default: return "";
 455     }
 456 }
 457
 458 100001,3.DESTREGS,3.RT,3.RS,0:MICROMIPS:16::MOVEP
 459 "movep %s<DESTREGS> r<ERS>, r<ERT>"
 460 *micromips32:
 461 *micromips64:
 462 {
 463   int rd;
 464   int re;
 465   int dest = DESTREGS;
 466
 467   if (dest == 0 || dest == 1)
 468     rd = 5;
 469   else if (dest == 2)
 470     rd = 6;
 471   else
 472     rd = 4;
 473
 474   if (dest == 0 || dest == 6)
 475     re = 6;
 476   else if (dest == 1 || dest == 2 || dest == 7)
 477     re = 7;
 478   else if (dest == 3)
 479     re = 21;
 480   else if (dest == 4)
 481     re = 22;
 482   /* assume dest is 5 */
 483   else
 484     re = 5;
 485
 486   GPR[rd] = GPR[ERS];
 487   GPR[re] = GPR[ERT];
 488 }
 489
 490
 491 010001,0000,3.RT,3.RS:POOL16C:16::NOT16
 492 "not16 r<TRT>, r<TRS>"
 493 *micromips32:
 494 *micromips64:
 495 {
 496   do_nor (SD_, 0, TRS, TRT);
 497 }
 498
 499
 500 010001,0011,3.RT,3.RS:POOL16C:16::OR16
 501 "or16 r<TRT>, r<TRS>"
 502 *micromips32:
 503 *micromips64:
 504 {
 505   do_or (SD_, TRS, TRT, TRT);
 506 }
 507
 508
 509 100010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SB16
 510 "sb16 r<TRT_S>, <IMMEDIATE>(r<TBASE>)"
 511 *micromips32:
 512 *micromips64:
 513 {
 514   do_store (SD_, AccessLength_BYTE, GPR[TBASE], IMMEDIATE, GPR[TRT_S]);
 515 }
 516
 517
 518 010001,101100,4.CODE:POOL16C:16::SDBBP16
 519 "sdbbp16 %#lx<CODE>"
 520 *micromips32:
 521 *micromips64:
 522 {
 523   SignalException (DebugBreakPoint, instruction_0);
 524 }
 525
 526
 527 101010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SH16
 528 "sh16 r<TRT_S>, <IMM_SHIFT_1BIT>(r<TBASE>)"
 529 *micromips32:
 530 *micromips64:
 531 {
 532   do_store (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT, GPR[TRT_S]);
 533 }
 534
 535
 536 001001,3.RD,3.RT,3.SHIFT,0:POOL16B:16::SLL16
 537 "sll16 r<TRD>, r<TRT>, <SHIFT_DEC>"
 538 *micromips32:
 539 *micromips64:
 540 {
 541   do_sll (SD_, TRT, TRD, SHIFT_DEC);
 542 }
 543
 544
 545 001001,3.RD,3.RT,3.SHIFT,1:POOL16B:16::SRL16
 546 "srl16 r<TRD>, r<TRT>, <SHIFT_DEC>"
 547 *micromips32:
 548 *micromips64:
 549 {
 550   do_srl (SD_, TRT, TRD, SHIFT_DEC);
 551 }
 552
 553
 554 000001,3.RD,3.RT,3.RS,1:POOL16A:16::SUBU16
 555 "subu16 r<TRD>, r<TRS>, r<TRT>"
 556 *micromips32:
 557 *micromips64:
 558 {
 559   do_subu (SD_, TRS, TRT, TRD);
 560 }
 561
 562
 563 111010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SW16
 564 "sw16 r<TRT_S>, <IMM_SHIFT_2BIT>(r<TBASE>)"
 565 *micromips32:
 566 *micromips64:
 567 {
 568   do_store (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT, GPR[TRT_S]);
 569 }
 570
 571
 572 110010,5.RT,5.IMMEDIATE:MICROMIPS:16::SWSP
 573 "swsp r<RT>, <IMM_SHIFT_2BIT>(sp)"
 574 *micromips32:
 575 *micromips64:
 576 {
 577   do_store (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT, GPR[RT]);
 578 }
 579
 580
 581 010001,0101,2.LWMREGS,4.IMMEDIATE:POOL16C:16::SWM16
 582 "swm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"
 583 *micromips32:
 584 *micromips64:
 585 {
 586   int address = GPR[SPIDX] + IMM_SHIFT_2BIT;
 587   int reg_offset;
 588
 589   for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)
 590     do_store (SD_, AccessLength_WORD, address, reg_offset * 4,
 591         GPR[16 + reg_offset]);
 592
 593   do_store (SD_, AccessLength_WORD, address, reg_offset * 4, RA);
 594 }
 595
 596
 597 010001,0001,3.RT,3.RS:POOL16C:16::XOR16
 598 "xor16 r<TRT>, r<TRS>"
 599 *micromips32:
 600 *micromips64:
 601 {
 602   do_xor (SD_, TRS, TRT, TRT);
 603 }
 604
 605
 606 000000,5.RT,5.RS,5.RD,00100,010000:POOL32A:32::ADD
 607 "add r<RD>, r<RS>, r<RT>"
 608 *micromips32:
 609 *micromips64:
 610 {
 611   do_add (SD_, RS, RT, RD);
 612 }
 613
 614
 615 000100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDI
 616 "addi r<RT>, r<RS>, <IMMEDIATE>"
 617 *micromips32:
 618 *micromips64:
 619 {
 620   do_addi (SD_, RS, RT, IMMEDIATE);
 621 }
 622
 623
 624 001100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDIU
 625 "li r<RT>, <IMMEDIATE>":RS==0
 626 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 627 *micromips32:
 628 *micromips64:
 629 {
 630   do_addiu (SD_, RS, RT, IMMEDIATE);
 631 }
 632
 633
 634 011110,3.RS,23.IMMEDIATE:MICROMIPS:32::ADDIUPC
 635 "addiupc r<TRS>, <IMM_SHIFT_2BIT>"
 636 *micromips32:
 637 *micromips64:
 638 {
 639   GPR[TRS] = EXTEND32 ((CIA & ~3) + EXTEND25 (IMM_SHIFT_2BIT));
 640 }
 641
 642
 643 000000,5.RT,5.RS,5.RD,00101,010000:POOL32A:32::ADDU
 644 "addu r<RD>, r<RS>, r<RT>"
 645 *micromips32:
 646 *micromips64:
 647 {
 648   do_addu (SD_, RS, RT, RD);
 649 }
 650
 651
 652 000000,5.RT,5.RS,5.RD,01001,010000:POOL32A:32::AND
 653 "and r<RD>, r<RS>, r<RT>"
 654 *micromips32:
 655 *micromips64:
 656 {
 657   do_and (SD_, RS, RT, RD);
 658 }
 659
 660
 661 110100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ANDI
 662 "andi r<RT>, r<RS>, <IMMEDIATE>"
 663 *micromips32:
 664 *micromips64:
 665 {
 666   do_andi (SD_, RS, RT, IMMEDIATE);
 667 }
 668
 669
 670 010000,1110,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32,f::BC1a
 671 "bc1%s<TF> <IMMEDIATE>":CC == 0
 672 "bc1%s<TF> <CC>, <IMMEDIATE>"
 673 *micromips32:
 674 *micromips64:
 675 {
 676   check_fpu (SD_);
 677   if (GETFCC(CC) == TF)
 678     {
 679       address_word dest = NIA + (EXTEND16 (IMMEDIATE) << 1);
 680       NIA = delayslot_micromips (SD_, dest, NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
 681     }
 682 }
 683
 684
 685 010000,1010,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32::BC2a
 686 "bc2%s<TF> <CC>, <IMMEDIATE>":CC == 0
 687 "bc2%s<TF> <CC>, <IMMEDIATE>"
 688 *micromips32:
 689 *micromips64:
 690
 691
 692 100101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BEQ
 693 "b <IMMEDIATE>":RT == 0 && RS == 0
 694 "beq r<RS>, r<RT>, <IMMEDIATE>"
 695 *micromips32:
 696 *micromips64:
 697 {
 698   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 699   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 700     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 701                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 702 }
 703
 704 010000,00010,5.RS,16.IMMEDIATE:POOL32I:32::BGEZ
 705 "bgez r<RS>, <IMMEDIATE>"
 706 *micromips32:
 707 *micromips64:
 708 {
 709   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 710   if ((signed_word) GPR[RS] >= 0)
 711     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 712                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 713 }
 714
 715
 716 010000,00111,5.RS,16.IMMEDIATE:POOL32I:32::BEQZC
 717 "beqzc r<RS>, <IMMEDIATE>"
 718 *micromips32:
 719 *micromips64:
 720 {
 721   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 722   if (GPR[RS] == 0)
 723     NIA = NIA + offset;
 724 }
 725
 726
 727 010000,00011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZAL
 728 "bal <IMMEDIATE>":RS == 0
 729 "bgezal r<RS>, <IMMEDIATE>"
 730 *micromips32:
 731 *micromips64:
 732 {
 733   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 734   if (RS == 31)
 735     Unpredictable ();
 736   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;
 737   if ((signed_word) GPR[RS] >= 0)
 738     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 739                                MICROMIPS_DELAYSLOT_SIZE_32);
 740 }
 741
 742
 743 010000,00110,5.RS,16.IMMEDIATE:POOL32I:32::BGTZ
 744 "bgtz r<RS>, <IMMEDIATE>"
 745 *micromips32:
 746 *micromips64:
 747 {
 748   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 749   if ((signed_word) GPR[RS] > 0)
 750     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 751                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 752 }
 753
 754
 755 010000,10011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZALS
 756 "bal <IMMEDIATE>":RS == 0
 757 "bgezals r<RS>, <IMMEDIATE>"
 758 *micromips32:
 759 *micromips64:
 760 {
 761   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 762   if (RS == 31)
 763     Unpredictable ();
 764   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;
 765   if ((signed_word) GPR[RS] >= 0)
 766     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 767                                MICROMIPS_DELAYSLOT_SIZE_16);
 768 }
 769
 770
 771 010000,00100,5.RS,16.IMMEDIATE:POOL32I:32::BLEZ
 772 "blez r<RS>, <IMMEDIATE>"
 773 *micromips32:
 774 *micromips64:
 775 {
 776   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 777   /* NOTE: The branch occurs AFTER the next instruction has been
 778      executed */
 779   if ((signed_word) GPR[RS] <= 0)
 780     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 781                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 782 }
 783
 784
 785 010000,00000,5.RS,16.IMMEDIATE:POOL32I:32::BLTZ
 786 "bltz r<RS>, <IMMEDIATE>"
 787 *micromips32:
 788 *micromips64:
 789 {
 790   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 791   if ((signed_word) GPR[RS] < 0)
 792     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 793                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 794 }
 795
 796
 797 010000,00001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZAL
 798 "bltzal r<RS>, <IMMEDIATE>"
 799 *micromips32:
 800 *micromips64:
 801 {
 802   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 803   if (RS == 31)
 804     Unpredictable ();
 805   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;
 806   /* NOTE: The branch occurs AFTER the next instruction has been
 807      executed */
 808   if ((signed_word) GPR[RS] < 0)
 809     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 810                                MICROMIPS_DELAYSLOT_SIZE_32);
 811 }
 812
 813 010000,10001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZALS
 814 "bltzals r<RS>, <IMMEDIATE>"
 815 *micromips32:
 816 *micromips64:
 817 {
 818   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 819   if (RS == 31)
 820     Unpredictable ();
 821   RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;
 822   if ((signed_word) GPR[RS] < 0)
 823     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 824                                MICROMIPS_DELAYSLOT_SIZE_16);
 825 }
 826
 827
 828 101101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BNE
 829 "bne r<RS>, r<RT>, <IMMEDIATE>"
 830 *micromips32:
 831 *micromips64:
 832 {
 833   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 834   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 835     NIA = delayslot_micromips (SD_, NIA + offset, NIA,
 836                                MICROMIPS_DELAYSLOT_SIZE_ANY);
 837 }
 838
 839
 840 010000,00101,5.RS,16.IMMEDIATE:POOL32I:32::BNEZC
 841 "bnezc r<RS>, <IMMEDIATE>"
 842 *micromips32:
 843 *micromips64:
 844 {
 845   address_word offset = EXTEND16 (IMMEDIATE) << 1;
 846   if ((signed_word) GPR[RS] != 0)
 847     NIA = NIA + offset;
 848 }
 849
 850
 851 000000,20.CODE,000111:POOL32A:32::BREAK
 852 "break %#lx<CODE>"
 853 *micromips32:
 854 *micromips64:
 855 {
 856   do_break (SD_, instruction_0);
 857 }
 858
 859
 860 001000,5.OP,5.BASE,0110,12.IMMEDIATE:POOL32B:32::CACHE
 861 "cache <OP>, <IMMEDIATE>(r<BASE>)"
 862 *micromips32:
 863 *micromips64:
 864 {
 865   address_word base = GPR[BASE];
 866   address_word offset = EXTEND12 (IMMEDIATE);
 867   address_word vaddr = loadstore_ea (SD_, base, offset);
 868   address_word paddr = vaddr;
 869   CacheOp (OP, vaddr, paddr, instruction_0);
 870 }
 871
 872
 873 011000,5.OP,5.BASE,1010011,9.IMMEDIATE:POOL32C:32::CACHEE
 874 "cachee <OP>, <IMMEDIATE>(r<BASE>)"
 875 *micromips32:
 876 *micromips64:
 877
 878
 879 010101,5.RT,5.FS,0001000000,111011:POOL32F:32,f::CFC1
 880 "cfc1 r<RT>, f<FS>"
 881 *micromips32:
 882 *micromips64:
 883 {
 884   do_cfc1 (SD_, RT, FS);
 885 }
 886
 887
 888 000000,5.RT,5.IMPL,1100110100,111100:POOL32A:32::CFC2
 889 "cfc2 r<RT>, <IMPL>"
 890 *micromips32:
 891 *micromips64:
 892
 893
 894 000000,5.RT,5.RS,0100101100,111100:POOL32A:32::CLO
 895 "clo r<RT>, r<RS>"
 896 *micromips32:
 897 *micromips64:
 898 {
 899   do_clo (SD_, RT, RS);
 900 }
 901
 902
 903 000000,5.RT,5.RS,0101101100,111100:POOL32A:32::CLZ
 904 "clz r<RT>, r<RS>"
 905 *micromips32:
 906 *micromips64:
 907 {
 908   do_clz (SD_, RT, RS);
 909 }
 910
 911
 912 000000,23.COFUN,010:POOL32A:32::COP2
 913 "cop2 <COFUN>"
 914 *micromips32:
 915 *micromips64:
 916
 917
 918 010101,5.RT,5.FS,0001100000,111011:POOL32F:32,f::CTC1
 919 "ctc1 r<RT>, f<FS>"
 920 *micromips32:
 921 *micromips64:
 922 {
 923   do_ctc1 (SD_, RT, FS);
 924 }
 925
 926
 927 000000,5.RT,5.IMPL,1101110100,111100:POOL32A:32::CTC2
 928 "ctc2 r<RT>, <IMPL>"
 929 *micromips32:
 930 *micromips64:
 931
 932
 933 000000,00000000001110001101,111100:POOL32A:32::DERET
 934 "deret"
 935 *micromips32:
 936 *micromips64:
 937
 938
 939 000000,00000,5.RS,0100011101,111100:POOL32A:32::DI
 940 "di":RS == 0
 941 "di r<RS>"
 942 *micromips32:
 943 *micromips64:
 944 {
 945   do_di (SD_, RS);
 946 }
 947
 948 000000,5.RT,5.RS,1010101100,111100:POOL32A:32::DIV
 949 "div r<RS>, r<RT>"
 950 *micromips32:
 951 *micromips64:
 952 {
 953   do_div (SD_, RS, RT);
 954 }
 955
 956
 957 000000,5.RT,5.RS,1011101100,111100:POOL32A:32::DIVU
 958 "divu r<RS>, r<RT>"
 959 *micromips32:
 960 *micromips64:
 961 {
 962   do_divu (SD_, RS, RT);
 963 }
 964
 965
 966 000000,00000000000001100000,000000:POOL32A:32::EHB
 967 "ehb"
 968 *micromips32:
 969 *micromips64:
 970
 971
 972 000000,00000,5.RS,0101011101,111100:POOL32A:32::EI
 973 "ei":RS == 0
 974 "ei r<RS>"
 975 *micromips32:
 976 *micromips64:
 977 {
 978   do_ei (SD_, RS);
 979 }
 980
 981 000000,00000000001111001101,111100:POOL32A:32::ERET
 982 "eret"
 983 *micromips32:
 984 *micromips64:
 985 {
 986   if (SR & status_ERL)
 987     {
 988       /* Oops, not yet available */
 989       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
 990       NIA = EPC;
 991       SR &= ~status_ERL;
 992     }
 993   else
 994     {
 995       NIA = EPC;
 996       SR &= ~status_EXL;
 997     }
 998 }
 999
1000
1001 000000,5.RT,5.RS,5.MSBD,5.LSB,101100:POOL32A:32::EXT
1002 "ext r<RT>, r<RS>, <LSB>, <MSBD+1>"
1003 *micromips32:
1004 *micromips64:
1005 {
1006   do_ext (SD_, RT, RS, LSB, MSBD);
1007 }
1008
1009
1010 000000,5.RT,5.RS,5.MSBD,5.LSB,001100:POOL32A:32::INS
1011 "ins r<RT>, r<RS>, <LSB>, <MSBD-LSB+1>"
1012 *micromips32:
1013 *micromips64:
1014 {
1015   do_ins (SD_, RT, RS, LSB, MSBD);
1016 }
1017
1018
1019 110101,26.IMMEDIATE:MICROMIPS:32::J
1020 "j <IMM_SHIFT_1BIT>"
1021 *micromips32:
1022 *micromips64:
1023 {
1024   address_word region = (NIA & MASK (63, 27));
1025   NIA = delayslot_micromips (SD_, region | (IMM_SHIFT_1BIT), NIA,
1026                              MICROMIPS_DELAYSLOT_SIZE_ANY);
1027 }
1028
1029
1030 111101,26.IMMEDIATE:MICROMIPS:32::JAL
1031 "jal <IMM_SHIFT_1BIT>"
1032 *micromips32:
1033 *micromips64:
1034 {
1035   /* NOTE: The region used is that of the delay slot and NOT the
1036      current instruction */
1037   address_word region = (NIA & MASK (63, 27));
1038   NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA,
1039                           MICROMIPS_DELAYSLOT_SIZE_32);
1040 }
1041
1042
1043 011101,26.IMMEDIATE:MICROMIPS:32::JALS
1044 "jals <IMM_SHIFT_1BIT>"
1045 *micromips32:
1046 *micromips64:
1047 {
1048   address_word region = (NIA & MASK (63, 27));
1049   NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA,
1050                           MICROMIPS_DELAYSLOT_SIZE_16);
1051 }
1052
1053 000000,5.RT!0,5.RS,0000111100,111100:POOL32A:32::JALR
1054 "jalr r<RS>":RT == 31
1055 "jalr r<RT>, r<RS>"
1056 *micromips32:
1057 *micromips64:
1058 {
1059   if (RS == RT)
1060     Unpredictable ();
1061   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1062 }
1063
1064 000000,5.RT,5.RS,0100111100,111100:POOL32A:32::JALRS
1065 "jalrs r<RT>, r<RS>"
1066 *micromips32:
1067 *micromips64:
1068 {
1069   if (RS == RT)
1070     Unpredictable ();
1071   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
1072 }
1073
1074
1075 111100,26.IMMEDIATE:MICROMIPS:32::JALX
1076 "jalx <IMM_SHIFT_2BIT>"
1077 *micromips32:
1078 *micromips64:
1079 {
1080   struct mips_sim_state *state = MIPS_SIM_STATE (SD);
1081   address_word region = (NIA & MASK (63, 26));
1082   NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_2BIT)) | ISA_MODE_MIPS32,
1083                           NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1084   state->isa_mode = ISA_MODE_MIPS32;
1085 }
1086
1087 000000,00000,5.RS,0000111100,111100:POOL32A:32::JR
1088 "jr r<RS>"
1089 *micromips32:
1090 *micromips64:
1091 {
1092   NIA = process_isa_mode (SD_,
1093                           delayslot_micromips (SD_, GPR[RS], NIA,
1094                                                MICROMIPS_DELAYSLOT_SIZE_32));
1095 }
1096
1097
1098 000000,5.RT,5.RS,0001111100,111100:POOL32A:32::JALR.HB
1099 "jalr.hb r<RT>, r<RS>"
1100 *micromips32:
1101 *micromips64:
1102 {
1103   if (RS == RT)
1104     Unpredictable ();
1105   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1106 }
1107
1108
1109 000000,5.RT,5.RS,0101111100,111100:POOL32A:32::JALRS.HB
1110 "jalrs.hb r<RT>, r<RS>"
1111 *micromips32:
1112 *micromips64:
1113 {
1114   if (RS == RT)
1115     Unpredictable ();
1116   NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
1117 }
1118
1119
1120 000000,00000,5.RS,0111111100,111100:POOL32A:32::JR.HB
1121 "jr.hb r<RS>"
1122 *micromips32:
1123 *micromips64:
1124 {
1125   NIA = process_isa_mode (SD_,
1126                           delayslot_micromips (SD_, GPR[RS], NIA,
1127                                                MICROMIPS_DELAYSLOT_SIZE_32));
1128 }
1129
1130
1131 000111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LB
1132 "lb r<RT>, <IMMEDIATE>(r<BASE>)"
1133 *micromips32:
1134 *micromips64:
1135 {
1136   do_lb (SD_, RT, IMMEDIATE, BASE);
1137 }
1138
1139
1140 011000,5.RT,5.BASE,0110100,9.IMMEDIATE:POOL32C:32::LBE
1141 "lbe r<RT>, <IMMEDIATE>(r<BASE>)"
1142 *micromips32:
1143 *micromips64:
1144
1145
1146 000101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LBU
1147 "lbu r<RT>, <IMMEDIATE>(r<BASE>)"
1148 *micromips32:
1149 *micromips64:
1150 {
1151   do_lbu (SD_, RT, IMMEDIATE, BASE);
1152 }
1153
1154
1155 011000,5.RT,5.BASE,0110000,9.IMMEDIATE:POOL32C:32::LBUE
1156 "lbue r<RT>, <IMMEDIATE>(r<BASE>)"
1157 *micromips32:
1158 *micromips64:
1159
1160
1161 101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1a
1162 "ldc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1163 *micromips32:
1164 {
1165   check_fpu (SD_);
1166   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (IMMEDIATE)));
1167 }
1168
1169
1170 101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1b
1171 "ldc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1172 *micromips64:
1173 {
1174   check_fpu (SD_);
1175   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
1176                           EXTEND16 (IMMEDIATE)));
1177 }
1178
1179
1180 001000,5.RT,5.BASE,0010,12.IMMEDIATE:POOL32B:32::LDC2
1181 "ldc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1182 *micromips32:
1183 *micromips64:
1184
1185
1186 001111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LH
1187 "lh r<RT>, <IMMEDIATE>(r<BASE>)"
1188 *micromips32:
1189 *micromips64:
1190 {
1191   do_lh (SD_, RT, IMMEDIATE, BASE);
1192 }
1193
1194
1195 011000,5.RT,5.BASE,0110101,9.IMMEDIATE:POOL32C:32::LHE
1196 "lhe r<RT>, <IMMEDIATE>(r<BASE>)"
1197 *micromips32:
1198 *micromips64:
1199
1200
1201 001101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LHU
1202 "lhu r<RT>, <IMMEDIATE>(r<BASE>)"
1203 *micromips32:
1204 *micromips64:
1205 {
1206   do_lhu (SD_, RT, IMMEDIATE, BASE);
1207 }
1208
1209
1210 011000,5.RT,5.BASE,0110001,9.IMMEDIATE:POOL32C:32::LHUE
1211 "lhue r<RT>, <IMMEDIATE>(r<BASE>)"
1212 *micromips32:
1213 *micromips64:
1214
1215
1216 011000,5.RT,5.BASE,0011,12.IMMEDIATE:POOL32C:32::LL
1217 "ll r<RT>, <IMMEDIATE>(r<BASE>)"
1218 *micromips32:
1219 *micromips64:
1220 {
1221   do_ll (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1222 }
1223
1224
1225 011000,5.RT,5.BASE,0110110,9.IMMEDIATE:POOL32C:32::LLE
1226 "lle r<RT>, <IMMEDIATE>(r<BASE>)"
1227 *micromips32:
1228 *micromips64:
1229
1230
1231 010000,01101,5.RS,16.IMMEDIATE:POOL32I:32::LUI
1232 "lui r<RS>, <IMMEDIATE>"
1233 *micromips32:
1234 *micromips64:
1235 {
1236   do_lui (SD_, RS, IMMEDIATE);
1237 }
1238
1239
1240 010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:32,f::LUXC1
1241 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
1242 *micromips32:
1243 {
1244   do_luxc1_32 (SD_, FD, INDEX, BASE);
1245 }
1246
1247
1248 010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:64,f::LUXC1
1249 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
1250 *micromips64:
1251 {
1252   check_fpu (SD_);
1253   check_u64 (SD_, instruction_0);
1254   do_luxc1_64 (SD_, FD, INDEX, BASE);
1255 }
1256
1257
1258 111111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LW
1259 "lw r<RT>, <IMMEDIATE>(r<BASE>)"
1260 *micromips32:
1261 *micromips64:
1262 {
1263   do_lw (SD_, RT, IMMEDIATE, BASE);
1264 }
1265
1266
1267 100111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LWC1
1268 "lwc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1269 *micromips32:
1270 *micromips64:
1271 {
1272   do_lwc1 (SD_, FT, IMMEDIATE, BASE);
1273 }
1274
1275
1276 001000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32B:32::LWC2
1277 "lwc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1278 *micromips32:
1279 *micromips64:
1280
1281
1282 011000,5.RT,5.BASE,0110111,9.IMMEDIATE:POOL32C:32::LWE
1283 "lwe r<RT>, <IMMEDIATE>(r<BASE>)"
1284 *micromips32:
1285 *micromips64:
1286
1287
1288 011000,5.RT,5.BASE,0110011,9.IMMEDIATE:POOL32C:32::LWEE
1289 "lwee r<RT>, <IMMEDIATE>(r<BASE>)"
1290 *micromips32:
1291 *micromips64:
1292
1293
1294 011000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32C:32::LWL
1295 "lwl r<RT>, <IMMEDIATE>(r<BASE>)"
1296 *micromips32:
1297 *micromips64:
1298 {
1299   do_lwl (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1300 }
1301
1302
1303 011000,5.RT,5.BASE,0110010,9.IMMEDIATE:POOL32C:32::LWLE
1304 "lwle r<RT>, <IMMEDIATE>(r<BASE>)"
1305 *micromips32:
1306 *micromips64:
1307
1308 :%s::::LWM32REGS:int lwmregs
1309 *micromips32:
1310 *micromips64:
1311 {
1312   if (lwmregs & 0x10)
1313     {
1314       switch (lwmregs & 0xf)
1315         {
1316         case 0:
1317           return "ra";
1318         case 1:
1319           return "s0, ra";
1320         case 2:
1321           return "s0, s1, ra";
1322         case 3:
1323           return "s0, s1, s2, ra";
1324         case 4:
1325           return "s0, s1, s2, s3, ra";
1326         case 5:
1327           return "s0, s1, s2, s3, s4, ra";
1328         case 6:
1329           return "s0, s1, s2, s3, s4, s5, ra";
1330         case 7:
1331           return "s0, s1, s2, s3, s4, s5, s6, ra";
1332         case 8:
1333           return "s0, s1, s2, s3, s4, s5, s6, s7, ra";
1334         case 9:
1335           return "s0, s1, s2, s3, s4, s5, s6, s7, s8, ra";
1336         default:
1337           return "";
1338         }
1339     }
1340   else
1341     {
1342       switch (lwmregs & 0xf)
1343         {
1344         case 1:
1345           return "s0";
1346         case 2:
1347           return "s0, s1";
1348         case 3:
1349           return "s0, s1, s2";
1350         case 4:
1351           return "s0, s1, s2, s3";
1352         case 5:
1353           return "s0, s1, s2, s3, s4";
1354         case 6:
1355           return "s0, s1, s2, s3, s4, s5";
1356         case 7:
1357           return "s0, s1, s2, s3, s4, s5, s6";
1358         case 8:
1359           return "s0, s1, s2, s3, s4, s5, s6, s7";
1360         case 9:
1361           return "s0, s1, s2, s3, s4, s5, s6, s7, s8";
1362         default:
1363           return "";
1364         }
1365     }
1366 }
1367
1368 001000,5.LWM32REGS,5.BASE,0101,12.IMMEDIATE:POOL32B:32::LWM32
1369 "lwm32 %s<LWM32REGS>, <IMMEDIATE>(r<BASE>)"
1370 *micromips32:
1371 *micromips64:
1372 {
1373   int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE);
1374   int reg_offset;
1375   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
1376     {
1377       int dst = (reg_offset == 8) ? 30 : 16 + reg_offset;
1378       GPR[dst] = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base,
1379                                     4 * reg_offset));
1380     }
1381
1382   if (LWM32REGS & 0x10)
1383     RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base,
1384                             4 * reg_offset));
1385 }
1386
1387
1388 001000,5.RD,5.BASE,0001,12.IMMEDIATE:POOL32B:32::LWP
1389 "lwp r<RD>, <IMMEDIATE>(r<BASE>)"
1390 *micromips32:
1391 *micromips64:
1392 {
1393   if (BASE == RD || RD == 31)
1394     Unpredictable ();
1395   else
1396     {
1397       do_lw (SD_, RD, EXTEND12 (IMMEDIATE), BASE);
1398       do_lw (SD_, RD + 1, EXTEND12 (IMMEDIATE) + 4, BASE);
1399     }
1400 }
1401
1402
1403 011000,5.RT,5.BASE,0001,12.IMMEDIATE:POOL32C:32::LWR
1404 "lwr r<RT>, <IMMEDIATE>(r<BASE>)"
1405 *micromips32:
1406 *micromips64:
1407 {
1408   do_lwr (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1409 }
1410
1411
1412 011000,5.RT,5.BASE,1110,12.IMMEDIATE:POOL32C:32::LWU
1413 "lwu r<RT>, <IMMEDIATE>(r<BASE>)"
1414 *micromips32:
1415 *micromips64:
1416 {
1417   do_lwu (SD_, RT, IMMEDIATE, BASE, instruction_0);
1418 }
1419
1420
1421 010101,5.INDEX,5.BASE,5.FD,00001,001000:POOL32F:32,f::LWXC1
1422 "lwxc1 f<FD>, <INDEX>(r<BASE>)"
1423 *micromips32:
1424 *micromips64:
1425 {
1426   do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0);
1427 }
1428
1429
1430 000000,5.INDEX,5.BASE,5.RD,00100,011000:POOL32A:32::LWXS
1431 "lwxs r<RD>, r<INDEX>(r<BASE>)"
1432 *micromips32:
1433 *micromips64:
1434 {
1435   GPR[RD] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE],
1436                                GPR[INDEX] * 4));
1437 }
1438
1439
1440 000000,5.RT,5.RS,1100101100,111100:POOL32A:32::MADD
1441 "madd r<RS>, r<RT>"
1442 *micromips32:
1443 *micromips64:
1444 {
1445   do_madd (SD_, RS, RT);
1446 }
1447
1448
1449 000000,5.RT,5.RS,1101101100,111100:POOL32A:32::MADDU
1450 "maddu r<RS>, r<RT>"
1451 *micromips32:
1452 *micromips64:
1453 {
1454   do_maddu (SD_, RS, RT);
1455 }
1456
1457
1458 000000,5.RT,5.RS,00,3.SEL,00011,111100:POOL32A:32::MFC0
1459 "mfc0 r<RS>, r<RT>": SEL == 0
1460 "mfc0 r<RS>, r<RT>, <SEL>"
1461 *micromips32:
1462 *micromips64:
1463 {
1464   DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RS, SEL);
1465 }
1466
1467
1468 010101,5.RT,5.FS,0010000000,111011:POOL32F:32,f::MFC1
1469 "mfc1 r<RT>, f<FS>"
1470 *micromips32:
1471 *micromips64:
1472 {
1473   do_mfc1b (SD_, RT, FS);
1474 }
1475
1476
1477 000000,5.RT,5.IMPL,0100110100,111100:POOL32A:32::MFC2
1478 "mfc2 r<RT>, <IMPL>"
1479 *micromips32:
1480 *micromips64:
1481
1482
1483 010101,5.RT,5.FS,0011000000,111011:POOL32F:32,f::MFHC1
1484 "mfhc1 r<RT>, f<FS>"
1485 *micromips32:
1486 *micromips64:
1487 {
1488   do_mfhc1 (SD_, RT, FS);
1489 }
1490
1491
1492 000000,5.RT,5.IMPL,1000110100,111100:POOL32A:32::MFHC2
1493 "mfhc2 r<RT>, <IMPL>"
1494 *micromips32:
1495 *micromips64:
1496
1497
1498 000000,00000,5.RS,0000110101,111100:POOL32A:32::MFHI
1499 "mfhi r<RS>"
1500 *micromips32:
1501 *micromips64:
1502 {
1503   do_mfhi (SD_, RS);
1504 }
1505
1506
1507 000000,00000,5.RS,0001110101,111100:POOL32A:32::MFLO
1508 "mflo r<RS>"
1509 *micromips32:
1510 *micromips64:
1511 {
1512   do_mflo (SD_, RS);
1513 }
1514
1515
1516 // MOVF
1517 // MOVT
1518 010101,5.RT,5.RS,3.CC,0,1.TF,00101,111011:POOL32F:32::MOVtf
1519 "mov%s<TF> r<RT>, r<RS>, CC"
1520 *micromips32:
1521 *micromips64:
1522 {
1523   do_movtf (SD_, TF, RT, RS, CC);
1524 }
1525
1526
1527 000000,5.RT,5.RS,5.RD,00000,011000:POOL32A:32::MOVN
1528 "movn r<RD>, r<RS>, r<RT>"
1529 *micromips32:
1530 *micromips64:
1531 {
1532   do_movn (SD_, RD, RS, RT);
1533 }
1534
1535
1536 000000,5.RT,5.RS,5.RD,00001,011000:POOL32A:32::MOVZ
1537 "movz r<RD>, r<RS>, r<RT>"
1538 *micromips32:
1539 *micromips64:
1540 {
1541   do_movz (SD_, RD, RS, RT);
1542 }
1543
1544
1545 000000,5.RT,5.RS,1110101100,111100:POOL32A:32::MSUB
1546 "msub r<RS>, r<RT>"
1547 *micromips32:
1548 *micromips64:
1549 {
1550   do_msub (SD_, RS, RT);
1551 }
1552
1553
1554 000000,5.RT,5.RS,1111101100,111100:POOL32A:32::MSUBU
1555 "msubu r<RS>, r<RT>"
1556 *micromips32:
1557 *micromips64:
1558 {
1559   do_msubu (SD_, RS, RT);
1560 }
1561
1562
1563 000000,5.RT,5.RS,00,3.SEL,01011,111100:POOL32A:32::MTC0
1564 "mtc0 r<RS>, r<RT>": SEL == 0
1565 "mtc0 r<RS>, r<RT>, <SEL>"
1566 *micromips32:
1567 *micromips64:
1568 {
1569   DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RS, SEL);
1570 }
1571
1572
1573 010101,5.RT,5.FS,0010100000,111011:POOL32F:32,f::MTC1
1574 "mtc1 r<RT>, f<FS>"
1575 *micromips32:
1576 *micromips64:
1577 {
1578   do_mtc1b (SD_, RT, FS);
1579 }
1580
1581
1582 000000,5.RT,5.IMPL,0101110100,111100:POOL32A:32::MTC2
1583 "mtc2 r<RT>, <IMPL>"
1584 *micromips32:
1585 *micromips64:
1586
1587
1588 010101,5.RT,5.FS,0011100000,111011:POOL32F:32,f::MTHC1
1589 "mthc1 r<RT>, f<FS>"
1590 *micromips32:
1591 *micromips64:
1592 {
1593   do_mthc1 (SD_, RT, FS);
1594 }
1595
1596
1597 000000,5.RT,5.IMPL,1001110100,111100:POOL32A:32::MTHC2
1598 "mthc2 r<RT>, <IMPL>"
1599 *micromips32:
1600 *micromips64:
1601
1602
1603 000000,00000,5.RS,0010110101,111100:POOL32A:32::MTHI
1604 "mthi r<RS>"
1605 *micromips32:
1606 *micromips64:
1607 {
1608   do_mthi (SD_, RS);
1609 }
1610
1611
1612 000000,00000,5.RS,0011110101,111100:POOL32A:32::MTLO
1613 "mtlo r<RS>"
1614 *micromips32:
1615 *micromips64:
1616 {
1617   do_mtlo (SD_, RS);
1618 }
1619
1620
1621 000000,5.RT,5.RS,5.RD,01000,010000:POOL32A:32::MUL
1622 "mul r<RD>, r<RS>, r<RT>"
1623 *micromips32:
1624 *micromips64:
1625 {
1626   do_mul (SD_, RD, RS, RT);
1627 }
1628
1629
1630 000000,5.RT,5.RS,1000101100,111100:POOL32A:32::MULT
1631 "mult r<RS>, r<RT>"
1632 *micromips32:
1633 *micromips64:
1634 {
1635   do_mult (SD_, RS, RT, 0);
1636 }
1637
1638
1639 000000,5.RT,5.RS,1001101100,111100:POOL32A:32::MULTU
1640 "multu r<RS> r<RT>"
1641 *micromips32:
1642 *micromips64:
1643 {
1644   do_multu (SD_, RS, RT, 0);
1645 }
1646
1647
1648 000000,00000000000000000000,000000:POOL32A:32::NOP
1649 "nop"
1650 *micromips32:
1651 *micromips64:
1652 {
1653 }
1654
1655
1656 000000,5.RT,5.RS,5.RD,01011,010000:POOL32A:32::NOR
1657 "nor r<RD>, r<RS>, r<RT>"
1658 *micromips32:
1659 *micromips64:
1660 {
1661   do_nor (SD_, RS, RT, RD);
1662 }
1663
1664
1665 000000,5.RT,5.RS,5.RD,01010,010000:POOL32A:32::OR
1666 "or r<RD>, r<RS>, r<RT>"
1667 *micromips32:
1668 *micromips64:
1669 {
1670   do_or (SD_, RS, RT, RD);
1671 }
1672
1673
1674 010100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ORI
1675 "ori r<RT>, r<RS>, <IMMEDIATE>"
1676 *micromips32:
1677 *micromips64:
1678 {
1679   do_ori (SD_, RS, RT, IMMEDIATE);
1680 }
1681
1682
1683 000000,00000000000010100000,000000:POOL32A:32::PAUSE
1684 "pause"
1685 *micromips32:
1686 *micromips64:
1687
1688
1689 011000,5.HINT,5.BASE,0010,12.IMMEDIATE:POOL32C:32::PREF
1690 "pref <HINT>, <IMMEDIATE>(r<BASE>)"
1691 *micromips32:
1692 *micromips64:
1693 {
1694   do_pref (SD_, HINT, EXTEND12 (IMMEDIATE), BASE);
1695 }
1696
1697
1698 011000,5.HINT,5.BASE,1010010,9.IMMEDIATE:POOL32C:32::PREFE
1699 "prefe <HINT>, <IMMEDIATE>(r<BASE>)"
1700 *micromips32:
1701 *micromips64:
1702
1703
1704 010101,5.INDEX,5.BASE,5.HINT,00110,100000:POOL32F:32::PREFX
1705 "prefx <HINT>, r<INDEX>(r<BASE>)"
1706 *micromips32:
1707 *micromips64:
1708 {
1709   do_prefx (SD_, HINT, INDEX, BASE);
1710 }
1711
1712 000000,5.RT,5.RS,0110101100,111100:POOL32A:32::RDHWR
1713 "rdhwr r<RS>, r<RT>"
1714 *micromips32:
1715 *micromips64:
1716 {
1717   do_rdhwr (SD_, RT, RS);
1718 }
1719
1720 000000,5.RT,5.RS,1110000101,111100:POOL32A:32::RDPGPR
1721 "rdpgpr r<RS>, r<RT>"
1722 *micromips32:
1723 *micromips64:
1724
1725
1726 000000,5.RT,5.RS,5.SHIFT,00011,000000:POOL32A:32::ROTR
1727 "rotr r<RT>, r<RS>, <SHIFT>"
1728 *micromips32:
1729 *micromips64:
1730 {
1731   GPR[RT] = do_ror (SD_, GPR[RS], SHIFT);
1732 }
1733
1734
1735 000000,5.RT,5.RS,5.RD,00011,010000:POOL32A:32::ROTRV
1736 "rotrv r<RD>, r<RT>, r<RS>"
1737 *micromips32:
1738 *micromips64:
1739 {
1740   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
1741 }
1742
1743
1744 000110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SB
1745 "sb r<RT>, <IMMEDIATE>(r<BASE>)"
1746 *micromips32:
1747 *micromips64:
1748 {
1749   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]);
1750 }
1751
1752
1753 011000,5.RT,5.BASE,1010101,9.IMMEDIATE:POOL32C:32::SBE
1754 "sbe r<RT>, <IMMEDIATE>(r<BASE>)"
1755 *micromips32:
1756 *micromips64:
1757
1758
1759 011000,5.RT,5.BASE,1011,12.IMMEDIATE:POOL32C:32::SC
1760 "sc r<RT>, <IMMEDIATE>(r<BASE>)"
1761 *micromips32:
1762 *micromips64:
1763 {
1764   do_sc (SD_, RT, EXTEND12 (IMMEDIATE), BASE, instruction_0, 1);
1765 }
1766
1767
1768 011000,5.RT,5.BASE,1010110,9.IMMEDIATE:POOL32C:32::SCE
1769 "sce r<RT>, <IMMEDIATE>(r<BASE>)"
1770 *micromips32:
1771 *micromips64:
1772
1773
1774 000000,10.CODE,1101101101,111100:POOL32A:32::SDBBP
1775 "sdbbp %#lx<CODE>"
1776 *micromips32:
1777 *micromips64:
1778 {
1779   SignalException (DebugBreakPoint, instruction_0);
1780 }
1781
1782
1783 101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1a
1784 "sdc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1785 *micromips32:
1786 {
1787   do_sdc1 (SD_, FT, IMMEDIATE, BASE);
1788 }
1789
1790
1791 101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1b
1792 "sdc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1793 *micromips64:
1794 {
1795   check_fpu (SD_);
1796   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (IMMEDIATE),
1797             COP_SD (1, FT));
1798 }
1799
1800
1801 001000,5.RT,5.BASE,1010,12.IMMEDIATE:MICROMIPS:32::SDC2
1802 "sdc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1803 *micromips32:
1804 *micromips64:
1805
1806
1807 000000,5.RT,5.RS,0010101100,111100:POOL32A:32::SEB
1808 "seb r<RT>, r<RS>"
1809 *micromips32:
1810 *micromips64:
1811 {
1812   do_seb (SD_, RT, RS);
1813 }
1814
1815
1816 000000,5.RT,5.RS,0011101100,111100:POOL32A:32::SEH
1817 "seh r<RT>, r<RS>"
1818 *micromips32:
1819 *micromips64:
1820 {
1821   do_seh (SD_, RT, RS);
1822 }
1823
1824
1825 001110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SH
1826 "sh r<RT>, <IMMEDIATE>(r<BASE>)"
1827 *micromips32:
1828 *micromips64:
1829 {
1830   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (IMMEDIATE),
1831             GPR[RT]);
1832 }
1833
1834
1835 011000,5.RT,5.BASE,1010100,9.IMMEDIATE:POOL32C:32::SHE
1836 "she r<RT>, <IMMEDIATE>(r<BASE>)"
1837 *micromips32:
1838 *micromips64:
1839
1840
1841 000000,5.RT!0,5.RS!0,5.SHIFT,00000,000000:POOL32A:32::SLL
1842 "sll r<RT>, r<RS>, <SHIFT>"
1843 *micromips32:
1844 *micromips64:
1845 {
1846   do_sll (SD_, RS, RT, SHIFT);
1847 }
1848
1849
1850 000000,5.RT,5.RS,5.RD,00000,010000:POOL32A:32::SLLV
1851 "sllv r<RD>, r<RT>, r<RS>"
1852 *micromips32:
1853 *micromips64:
1854 {
1855   do_sllv (SD_, RS, RT, RD);
1856 }
1857
1858
1859 000000,5.RT,5.RS,5.RD,01101,010000:POOL32A:32::SLT
1860 "slt r<RD>, r<RS>, r<RT>"
1861 *micromips32:
1862 *micromips64:
1863 {
1864   do_slt (SD_, RS, RT, RD);
1865 }
1866
1867
1868 100100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTI
1869 "slti r<RT>, r<RS>, <IMMEDIATE>"
1870 *micromips32:
1871 *micromips64:
1872 {
1873   do_slti (SD_, RS, RT, IMMEDIATE);
1874 }
1875
1876
1877 101100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTIU
1878 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
1879 *micromips32:
1880 *micromips64:
1881 {
1882   do_sltiu (SD_, RS, RT, IMMEDIATE);
1883 }
1884
1885
1886 000000,5.RT,5.RS,5.RD,01110,010000:POOL32A:32::SLTU
1887 "sltu r<RD>, r<RS>, r<RT>"
1888 *micromips32:
1889 *micromips64:
1890 {
1891   do_sltu (SD_, RS, RT, RD);
1892 }
1893
1894
1895 000000,5.RT,5.RS,5.SHIFT,00010,000000:POOL32A:32::SRA
1896 "sra r<RT>, r<RS>, <SHIFT>"
1897 *micromips32:
1898 *micromips64:
1899 {
1900   do_sra (SD_, RS, RT, SHIFT);
1901 }
1902
1903
1904 000000,5.RT,5.RS,5.RD,00010,010000:POOL32A:32::SRAV
1905 "srav r<RD>, r<RT>, r<RS>"
1906 *micromips32:
1907 *micromips64:
1908 {
1909   do_srav (SD_, RS, RT, RD);
1910 }
1911
1912
1913 000000,5.RT,5.RS,5.SHIFT,00001,000000:POOL32A:32::SRL
1914 "srl r<RT>, r<RS>, <SHIFT>"
1915 *micromips32:
1916 *micromips64:
1917 {
1918   do_srl (SD_, RS, RT, SHIFT);
1919 }
1920
1921
1922 000000,5.RT,5.RS,5.RD,00001,010000:POOL32A:32::SRLV
1923 "srlv r<RD>, r<RT>, r<RS>"
1924 *micromips32:
1925 *micromips64:
1926 {
1927   do_srlv (SD_, RS, RT, RD);
1928 }
1929
1930
1931 000000,00000000000000100000,000000:POOL32A:32::SSNOP
1932 "ssnop"
1933 *micromips32:
1934 *micromips64:
1935 {
1936 }
1937
1938
1939 000000,5.RT,5.RS,5.RD,00110,010000:POOL32A:32::SUB
1940 "sub r<RD>, r<RS>, r<RT>"
1941 *micromips32:
1942 *micromips64:
1943 {
1944   do_sub (SD_, RD, RS, RT);
1945 }
1946
1947
1948 000000,5.RT,5.RS,5.RD,00111,010000:POOL32A:32::SUBU
1949 "subu r<RD>, r<RS>, r<RT>"
1950 *micromips32:
1951 *micromips64:
1952 {
1953   do_subu (SD_, RS, RT, RD);
1954 }
1955
1956
1957 010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:32,f::SUXC1
1958 "suxc1 f<FD>, r<INDEX>(r<BASE>)"
1959 *micromips32:
1960 {
1961   do_suxc1_32 (SD_, FD, INDEX, BASE);
1962 }
1963
1964
1965 010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:64,f::SUXC1
1966 "suxc1 f<FD>, r<INDEX>(r<BASE>)"
1967 *micromips64:
1968 {
1969   check_fpu (SD_);
1970   check_u64 (SD_, instruction_0);
1971   do_suxc1_64 (SD_, FD, INDEX, BASE);
1972 }
1973
1974 111110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SW
1975 "sw r<RT>, <IMMEDIATE>(r<BASE>)"
1976 *micromips32:
1977 *micromips64:
1978 {
1979   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]);
1980 }
1981
1982
1983 100110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SWC1
1984 "swc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1985 *micromips32:
1986 *micromips64:
1987 {
1988   do_swc1 (SD_, FT, IMMEDIATE, BASE, instruction_0);
1989 }
1990
1991
1992 001000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32B:32::SWC2
1993 "swc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1994 *micromips32:
1995 *micromips64:
1996
1997
1998 011000,5.RT,5.BASE,1010111,9.IMMEDIATE:POOL32C:32::SWE
1999 "swe r<RT>, <IMMEDIATE>(r<BASE>)"
2000 *micromips32:
2001 *micromips64:
2002
2003
2004 011000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32C:32::SWL
2005 "swl r<RT>, <IMMEDIATE>(r<BASE>)"
2006 *micromips32:
2007 *micromips64:
2008 {
2009   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE),
2010                  GPR[RT]);
2011 }
2012
2013
2014 011000,5.RT,5.BASE,1010000,9.IMMEDIATE:POOL32C:32::SWLE
2015 "swle r<RT>, <IMMEDIATE>(r<BASE>)"
2016 *micromips32:
2017 *micromips64:
2018
2019
2020 001000,5.LWM32REGS,5.BASE,1101,12.IMMEDIATE:POOL32B:32::SWM32
2021 "swm32 %s<LWM32REGS>, <IMMEDIATE>(r<BASE>)"
2022 *micromips32:
2023 *micromips64:
2024 {
2025   int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE);
2026   int reg_offset;
2027   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2028     {
2029       int src = (reg_offset == 8) ? 30 : 16 + reg_offset;
2030       do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset,
2031                 GPR[src]);
2032     }
2033
2034   if (LWM32REGS & 0x10)
2035     do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset, RA);
2036 }
2037
2038
2039 001000,5.RS1,5.BASE,1001,12.IMMEDIATE:POOL32B:32::SWP
2040 "swp r<RS1>, <IMMEDIATE>(r<BASE>)"
2041 *micromips32:
2042 *micromips64:
2043 {
2044   if (RS1 == 31)
2045     Unpredictable ();
2046   else
2047     {
2048       do_sw (SD_, RS1, EXTEND12 (IMMEDIATE), BASE);
2049       do_sw (SD_, RS1 + 1, EXTEND12 (IMMEDIATE) + 4, BASE);
2050     }
2051 }
2052
2053
2054 011000,5.RT,5.BASE,1001,12.IMMEDIATE:POOL32C:32::SWR
2055 "swr r<RT>, <IMMEDIATE>(r<BASE>)"
2056 *micromips32:
2057 *micromips64:
2058 {
2059   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE),
2060                   GPR[RT]);
2061 }
2062
2063
2064 011000,5.RT,5.BASE,1010001,9.IMMEDIATE:POOL32C:32::SWRE
2065 "swre r<RT>, <IMMEDIATE>(r<BASE>)"
2066 *micromips32:
2067 *micromips64:
2068
2069
2070 010101,5.INDEX,5.BASE,5.FD,00010,001000:POOL32F:32,f::SWXC1
2071 "swxc1 f<FD>, r<INDEX>(r<BASE>)"
2072 *micromips32:
2073 *micromips64:
2074 {
2075   do_swxc1 (SD_, FD, INDEX, BASE, instruction_0);
2076 }
2077
2078
2079 000000,00000,5.STYPE,0110101101,111100:POOL32A:32::SYNC
2080 "sync <STYPE>"
2081 *micromips32:
2082 *micromips64:
2083 {
2084   SyncOperation (STYPE);
2085 }
2086
2087
2088 010000,10000,5.BASE,16.IMMEDIATE:POOL32I:32::SYNCI
2089 "synci <IMMEDIATE>(r<BASE>)"
2090 *micromips32:
2091 *micromips64:
2092 {
2093 }
2094
2095 000000,10.CODE,1000101101,111100:POOL32A:32::SYSCALL
2096 "syscall %#lx<CODE>"
2097 *micromips32:
2098 *micromips64:
2099 {
2100   SignalException (SystemCall, instruction_0);
2101 }
2102
2103
2104 000000,5.RT,5.RS,4.CODE,000000,111100:POOL32A:32::TEQ
2105 "teq r<RS>, r<RT>"
2106 *micromips32:
2107 *micromips64:
2108 {
2109   do_teq (SD_, RS, RT, instruction_0);
2110 }
2111
2112
2113 010000,01110,5.RS,16.IMMEDIATE:POOL32I:32::TEQI
2114 "teqi r<RS>, <IMMEDIATE>"
2115 *micromips32:
2116 *micromips64:
2117 {
2118   do_teqi (SD_, RS, IMMEDIATE, instruction_0);
2119 }
2120
2121
2122 000000,5.RT,5.RS,4.CODE,001000,111100:POOL32A:32::TGE
2123 "tge r<RS>, r<RT>"
2124 *micromips32:
2125 *micromips64:
2126 {
2127   do_tge (SD_, RS, RT, instruction_0);
2128 }
2129
2130
2131 010000,01001,5.RS,16.IMMEDIATE:POOL32I:32::TGEI
2132 "tgei r<RS>, <IMMEDIATE>"
2133 *micromips32:
2134 *micromips64:
2135 {
2136   do_tgei (SD_, RS, IMMEDIATE, instruction_0);
2137 }
2138
2139
2140 010000,01011,5.RS,16.IMMEDIATE:POOL32I:32::TGEIU
2141 "tgeiu r<RS>, <IMMEDIATE>"
2142 *micromips32:
2143 *micromips64:
2144 {
2145   do_tgeiu (SD_, RS, IMMEDIATE, instruction_0);
2146 }
2147
2148
2149 000000,5.RT,5.RS,4.CODE,010000,111100:POOL32A:32::TGEU
2150 "tgeu r<RS>, r<RT>"
2151 *micromips32:
2152 *micromips64:
2153 {
2154   do_tgeu (SD_, RS, RT, instruction_0);
2155 }
2156
2157
2158 000000,00000000000000001101,111100:POOL32A:32::TLBP
2159 "tlbp"
2160 *micromips32:
2161 *micromips64:
2162
2163
2164 000000,00000000000001001101,111100:POOL32A:32::TLBR
2165 "tlbr"
2166 *micromips32:
2167 *micromips64:
2168
2169
2170 000000,00000000000010001101,111100:POOL32A:32::TLBWI
2171 "tlbwi"
2172 *micromips32:
2173 *micromips64:
2174
2175
2176 000000,00000000000011001101,111100:POOL32A:32::TLBWR
2177 "tlbwr"
2178 *micromips32:
2179 *micromips64:
2180
2181
2182 000000,5.RT,5.RS,4.CODE,100000,111100:POOL32A:32::TLT
2183 "tlt r<RS>, r<RT>, %#lx<CODE>"
2184 *micromips32:
2185 *micromips64:
2186 {
2187   do_tlt (SD_, RS, RT, instruction_0);
2188 }
2189
2190
2191 010000,01000,5.RS,16.IMMEDIATE:POOL32I:32::TLTI
2192 "tlti r<RS>, <IMMEDIATE>"
2193 *micromips32:
2194 *micromips64:
2195 {
2196   do_tlti (SD_, RS, IMMEDIATE, instruction_0);
2197 }
2198
2199
2200 010000,01010,5.RS,16.IMMEDIATE:POOL32I:32::TLTIU
2201 "tltiu r<RS>, <IMMEDIATE>"
2202 *micromips32:
2203 *micromips64:
2204 {
2205   do_tltiu (SD_, RS, IMMEDIATE, instruction_0);
2206 }
2207
2208
2209 000000,5.RT,5.RS,4.CODE,101000,111100:POOL32A:32::TLTU
2210 "tltu r<RS>, r<RT>"
2211 *micromips32:
2212 *micromips64:
2213 {
2214   do_tltu (SD_, RS, RT, instruction_0);
2215 }
2216
2217
2218 000000,5.RT,5.RS,4.CODE,110000,111100:POOL32A:32::TNE
2219 "tne r<RS>, r<RT>"
2220 *micromips32:
2221 *micromips64:
2222 {
2223   do_tne (SD_, RS, RT, instruction_0);
2224 }
2225
2226
2227 010000,01100,5.RS,16.IMMEDIATE:POOL32I:32::TNEI
2228 "tnei r<RS>, <IMMEDIATE>"
2229 *micromips32:
2230 *micromips64:
2231 {
2232   do_tnei (SD_, RS, IMMEDIATE, instruction_0);
2233 }
2234
2235
2236 000000,10.CODE,1001001101,111100:POOL32A:32::WAIT
2237 "wait"
2238 *micromips32:
2239 *micromips64:
2240
2241
2242 000000,5.RT,5.RS,1111000101,111100:POOL32A:32::WRPGPR
2243 "wrpgpr r<RS>, r<RT>"
2244 *micromips32:
2245 *micromips64:
2246
2247
2248 000000,5.RT,5.RS,0111101100,111100:POOL32A:32::WSBH
2249 "wsbh r<RT>, r<RS>"
2250 *micromips32:
2251 *micromips64:
2252 {
2253   do_wsbh (SD_, RT, RS);
2254 }
2255
2256
2257 000000,5.RT,5.RS,5.RD,01100,010000:POOL32A:32::XOR
2258 "xor r<RD>, r<RS>, r<RT>"
2259 *micromips32:
2260 *micromips64:
2261 {
2262   do_xor (SD_, RS, RT, RD);
2263 }
2264
2265
2266 011100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::XORI
2267 "xori r<RT>, r<RS>, <IMMEDIATE>"
2268 *micromips32:
2269 *micromips64:
2270 {
2271   do_xori (SD_, RS, RT, IMMEDIATE);
2272 }
2273
2274
2275 :%s::::FMT_MICROMIPS:int fmt
2276 *micromips32:
2277 *micromips64:
2278 {
2279   switch (fmt)
2280     {
2281     case 0: return "s";
2282     case 1: return "d";
2283     case 2: return "ps";
2284     default: return "?";
2285     }
2286 }
2287
2288
2289 :%s::::FMT_MICROMIPS_CVT_D:int fmt
2290 *micromips32:
2291 *micromips64:
2292 {
2293   switch (fmt)
2294     {
2295     case 0: return "s";
2296     case 1: return "w";
2297     case 2: return "l";
2298     default: return "?";
2299     }
2300 }
2301
2302
2303 :%s::::FMT_MICROMIPS_CVT_S:int fmt
2304 *micromips32:
2305 *micromips64:
2306 {
2307   switch (fmt)
2308     {
2309     case 0: return "d";
2310     case 1: return "w";
2311     case 2: return "l";
2312     default: return "?";
2313     }
2314 }
2315
2316
2317 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0001101,111011:POOL32F:32,f::ABS.fmt
2318 "abs.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2319 *micromips32:
2320 *micromips64:
2321 {
2322   do_abs_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2323               instruction_0);
2324 }
2325
2326
2327 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,110000:POOL32F:32,f::ADD.fmt
2328 "add.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2329 *micromips32:
2330 *micromips64:
2331 {
2332   do_add_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2333               instruction_0);
2334 }
2335
2336
2337 010101,5.FT,5.FS,5.FD,5.RS,011001:POOL32F:32,f::ALNV.PS
2338 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
2339 *micromips32:
2340 *micromips64:
2341 {
2342   do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0);
2343 }
2344
2345
2346 010101,5.FT,5.FS,3.CC,0,2.FMT_MICROMIPS!3,4.COND,111100:POOL32F:32,f::C.cond.fmt
2347 "c.%s<COND>.%s<FMT_MICROMIPS> f<FS>, f<FT>":CC == 0
2348 "c.%s<COND>.%s<FMT_MICROMIPS> <CC>, f<FS>, f<FT>"
2349 *micromips32:
2350 *micromips64:
2351 {
2352   do_c_cond_fmt (SD_, COND, convert_fmt_micromips (SD_, FMT_MICROMIPS), CC,
2353                  FS, FT, instruction_0);
2354 }
2355
2356
2357 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001100,111011:POOL32F:32,f::CEIL.L.fmt
2358 "ceil.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2359 *micromips32:
2360 *micromips64:
2361 {
2362   do_ceil_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS, instruction_0);
2363 }
2364
2365
2366 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01101100,111011:POOL32F:32,f::CEIL.W.fmt
2367 "ceil.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2368 *micromips32:
2369 *micromips64:
2370 {
2371   do_ceil_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS, instruction_0);
2372 }
2373
2374
2375 010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_D!3,1001101,111011:POOL32F:32,f::CVT.D.fmt
2376 "cvt.d.%s<FMT_MICROMIPS_CVT_D> f<FT>, f<FS>"
2377 *micromips32:
2378 *micromips64:
2379 {
2380   do_cvt_d_fmt (SD_, convert_fmt_micromips_cvt_d (SD_, FMT_MICROMIPS_CVT_D),
2381                 FT, FS, instruction_0);
2382 }
2383
2384
2385 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00000100,111011:POOL32F:32,f::CVT.L.fmt
2386 "cvt.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2387 *micromips32:
2388 *micromips64:
2389 {
2390   do_cvt_l_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0);
2391 }
2392
2393
2394 010101,5.FT,5.FS,5.FD,00110,000000:POOL32F:32,f::CVT.PS.S
2395 "cvt.ps.s f<FD>, f<FS>, f<FT>"
2396 *micromips32:
2397 *micromips64:
2398 {
2399   do_cvt_ps_s (SD_, FD, FS, FT, instruction_0);
2400 }
2401
2402
2403 010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_S!3,1101101,111011:POOL32F:32,f::CVT.S.fmt
2404 "cvt.s.%s<FMT_MICROMIPS_CVT_S> f<FT>, f<FS>"
2405 *micromips32:
2406 *micromips64:
2407 {
2408   do_cvt_s_fmt (SD_, convert_fmt_micromips_cvt_s (SD_, FMT_MICROMIPS_CVT_S),
2409                 FT, FS, instruction_0);
2410 }
2411
2412
2413 010101,5.FT,5.FS,00,10000100,111011:POOL32F:32,f::CVT.S.PL
2414 "cvt.s.pl f<FT>, f<FS>"
2415 *micromips32:
2416 *micromips64:
2417 {
2418   do_cvt_s_pl (SD_, FT, FS, instruction_0);
2419 }
2420
2421
2422 010101,5.FT,5.FS,00,10100100,111011:POOL32F:32,f::CVT.S.PU
2423 "cvt.s.pu f<FT>, f<FS>"
2424 *micromips32:
2425 *micromips64:
2426 {
2427   do_cvt_s_pu (SD_, FT, FS, instruction_0);
2428 }
2429
2430
2431 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00100100,111011:POOL32F:32,f::CVT.W.fmt
2432 "cvt.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2433 *micromips32:
2434 *micromips64:
2435 {
2436   do_cvt_w_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0);
2437 }
2438
2439
2440 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!2!3,11,110000:POOL32F:32,f::DIV.fmt
2441 "div.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2442 *micromips32:
2443 *micromips64:
2444 {
2445   do_div_fmt (SD_, FMT_MICROMIPS, FD, FS, FT, instruction_0);
2446 }
2447
2448
2449 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001100,111011:POOL32F:32,f::FLOOR.L.fmt
2450 "floor.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2451 *micromips32:
2452 *micromips64:
2453 {
2454   do_floor_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2455 }
2456
2457
2458 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101100,111011:POOL32F:32,f::FLOOR.W.fmt
2459 "floor.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2460 *micromips32:
2461 *micromips64:
2462 {
2463   do_floor_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2464 }
2465
2466
2467 010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MADD.fmt
2468 "madd.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2469 *micromips32:
2470 *micromips64:
2471 {
2472   do_madd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2473                FT, instruction_0);
2474 }
2475
2476 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0000001,111011:POOL32F:32,f::MOV.fmt
2477 "mov.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2478 *micromips32:
2479 *micromips64:
2480 {
2481   do_mov_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2482               instruction_0);
2483 }
2484
2485
2486 010101,5.FT,5.FS,3.CC,00,2.FMT_MICROMIPS!3,00,1.TF,100000:POOL32F:32,f::MOVtf.fmt
2487 "mov%s<TF>.%s<FMT_MICROMIPS> f<FT>, f<FS>, <CC>"
2488 *micromips32:
2489 *micromips64:
2490 {
2491   do_movtf_fmt (SD_, TF, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT,
2492                 FS, CC);
2493 }
2494
2495
2496 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,111000:POOL32F:32,f::MOVN.fmt
2497 "movn.%s<FMT_MICROMIPS> f<FD>, f<FS>, r<FT>"
2498 *micromips32:
2499 *micromips64:
2500 {
2501   do_movn_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT);
2502 }
2503
2504 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,111000:POOL32F:32,f::MOVZ.fmt
2505 "movz.%s<FMT_MICROMIPS> f<FD>, f<FS>, r<FT>"
2506 *micromips32:
2507 *micromips64:
2508 {
2509   do_movz_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT);
2510 }
2511
2512
2513 010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MSUB.fmt
2514 "msub.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2515 *micromips32:
2516 *micromips64:
2517 {
2518   do_msub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2519                FT, instruction_0);
2520 }
2521
2522 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,10,110000:POOL32F:32,f::MUL.fmt
2523 "mul.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2524 *micromips32:
2525 *micromips64:
2526 {
2527   do_mul_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2528               instruction_0);
2529 }
2530
2531
2532 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0101101,111011:POOL32F:32,f::NEG.fmt
2533 "neg.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2534 *micromips32:
2535 *micromips64:
2536 {
2537   do_neg_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2538               instruction_0);
2539 }
2540
2541
2542 010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMADD.fmt
2543 "nmadd.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2544 *micromips32:
2545 *micromips64:
2546 {
2547   do_nmadd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2548                 FT, instruction_0);
2549 }
2550
2551 010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMSUB.fmt
2552 "nmsub.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2553 *micromips32:
2554 *micromips64:
2555 {
2556   do_nmsub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2557                 FT, instruction_0);
2558 }
2559
2560
2561 010101,5.FT,5.FS,5.FD,00010,000000:POOL32F:32,f::PLL.PS
2562 "pll.ps f<FD>, f<FS>, f<FT>"
2563 *micromips32:
2564 *micromips64:
2565 {
2566   do_pll_ps (SD_, FD, FS, FT, instruction_0);
2567 }
2568
2569
2570 010101,5.FT,5.FS,5.FD,00011,000000:POOL32F:32,f::PLU.PS
2571 "plu.ps f<FD>, f<FS>, f<FT>"
2572 *micromips32:
2573 *micromips64:
2574 {
2575   do_plu_ps (SD_, FD, FS, FT, instruction_0);
2576 }
2577
2578
2579 010101,5.FT,5.FS,5.FD,00100,000000:POOL32F:32,f::PUL.PS
2580 "pul.ps f<FD>, f<FS>, f<FT>"
2581 *micromips32:
2582 *micromips64:
2583 {
2584   do_pul_ps (SD_, FD, FS, FT, instruction_0);
2585 }
2586
2587
2588 010101,5.FT,5.FS,5.FD,00101,000000:POOL32F:32,f::PUU.PS
2589 "puu.ps f<FD>, f<FS>, f<FT>"
2590 *micromips32:
2591 *micromips64:
2592 {
2593   do_puu_ps (SD_, FD, FS, FT, instruction_0);
2594 }
2595
2596
2597 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001000,111011:POOL32F:32,f::RECIP.fmt
2598 "recip.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2599 *micromips32:
2600 *micromips64:
2601 {
2602   do_recip_fmt (SD_, FMT_MICROMIPS, FT, FS);
2603 }
2604
2605
2606 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11001100,111011:POOL32F:32,f::ROUND.L.fmt
2607 "round.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2608 *micromips32:
2609 *micromips64:
2610 {
2611   do_round_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2612 }
2613
2614
2615 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11101100,111011:POOL32F:32,f::ROUND.W.fmt
2616 "round.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2617 *micromips32:
2618 *micromips64:
2619 {
2620   do_round_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2621 }
2622
2623
2624 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001000,111011:POOL32F:32,f::RSQRT.fmt
2625 "rsqrt.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2626 *micromips32:
2627 *micromips64:
2628 {
2629   do_rsqrt_fmt (SD_, FMT_MICROMIPS, FT, FS);
2630 }
2631
2632
2633 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101000,111011:POOL32F:32,f::SQRT.fmt
2634 "sqrt.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2635 *micromips32:
2636 *micromips64:
2637 {
2638   do_sqrt_fmt (SD_, FMT_MICROMIPS, FT, FS);
2639 }
2640
2641
2642 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,110000:POOL32F:32,f::SUB.fmt
2643 "sub.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2644 *micromips32:
2645 *micromips64:
2646 {
2647   do_sub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2648               instruction_0);
2649 }
2650
2651
2652 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10001100,111011:POOL32F:32,f::TRUNC.L.fmt
2653 "trunc.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2654 *micromips32:
2655 *micromips64:
2656 {
2657   do_trunc_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2658 }
2659
2660
2661 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10101100,111011:POOL32F:32,f::TRUNC.W.fmt
2662 "trunc.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2663 *micromips32:
2664 *micromips64:
2665 {
2666   do_trunc_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2667 }
2668
2669 001000,5.LWM32REGS,5.BASE,0111,12.OFFSET:POOL32B:64::LDM
2670 "ldm %s<LWM32REGS>, <OFFSET>(r<BASE>)"
2671 *micromips64:
2672 {
2673   int address_base = GPR[BASE] + EXTEND12 (OFFSET);
2674   int reg_offset;
2675   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2676     {
2677       int dst = (reg_offset == 8) ? 30 : 16 + reg_offset;
2678       GPR[dst] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base,
2679                                     8 * reg_offset));
2680     }
2681
2682   if (LWM32REGS & 0x10)
2683     RA = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base,
2684                             8 * reg_offset));
2685 }
2686
2687 001000,5.RD,5.BASE,0100,12.OFFSET:POOL32B:64::LDP
2688 "ldp r<RD>, <OFFSET>(r<BASE>)"
2689 *micromips64:
2690 {
2691   if (BASE == RD || RD == 31)
2692     Unpredictable ();
2693   else
2694     {
2695       check_u64 (SD_, instruction_0);
2696       GPR[RD] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
2697                                    EXTEND12 (OFFSET)));
2698       GPR[RD + 1] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
2699                                        EXTEND12 (OFFSET) + 8));
2700     }
2701 }
2702
2703 001000,5.LWM32REGS,5.BASE,1111,12.OFFSET:POOL32B:64::SDM
2704 "sdm %s<LWM32REGS>, <OFFSET>(r<BASE>)"
2705 *micromips64:
2706 {
2707   int address_base = GPR[BASE] + EXTEND12 (OFFSET);
2708   int reg_offset;
2709   for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2710     {
2711       int src = (reg_offset == 8) ? 30 : 16 + reg_offset;
2712       do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset,
2713                 GPR[src]);
2714     }
2715
2716   if (LWM32REGS & 0x10)
2717     do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset, RA);
2718 }
2719
2720 001000,5.RD,5.BASE,1100,12.OFFSET:POOL32B:64::SDP
2721 "sdp r<RD>, <OFFSET>(r<BASE>)"
2722 *micromips64:
2723 {
2724   if (RD == 31)
2725     Unpredictable ();
2726   else
2727     {
2728       check_u64 (SD_, instruction_0);
2729       do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
2730                 GPR[RD]);
2731       do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET) + 8,
2732                 GPR[RD + 1]);
2733     }
2734 }
2735
2736 010110,5.RT,5.RS,5.RD,00,100010000:POOL32S:64::DADD
2737 "dadd r<RD>, r<RS>, r<RT>"
2738 *micromips64:
2739 {
2740   check_u64 (SD_, instruction_0);
2741   do_dadd (SD_, RD, RS, RT);
2742 }
2743
2744 010110,5.RT,5.RS,10.IMMEDIATE,011100:POOL32S:64::DADDI
2745 "daddi r<RT>, r<RS>, <IMMEDIATE>"
2746 *micromips64:
2747 {
2748   check_u64 (SD_, instruction_0);
2749   do_daddi (SD_, RT, RS, IMMEDIATE);
2750 }
2751
2752 010111,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:64::DADDIU
2753 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
2754 *micromips64:
2755 {
2756   check_u64 (SD_, instruction_0);
2757   do_daddiu (SD_, RS, RT, IMMEDIATE);
2758 }
2759
2760 010110,5.RT,5.RS,5.RD,00,101010000:POOL32S:64::DADDU
2761 "daddu r<RD>, r<RS>, r<RT>"
2762 *micromips64:
2763 {
2764   check_u64 (SD_, instruction_0);
2765   do_daddu (SD_, RS, RT, RD);
2766 }
2767
2768 010110,5.RT,5.RS,0100101100,111100:POOL32S:64::DCLO
2769 "dclo r<RT>, r<RS>"
2770 *micromips64:
2771 {
2772   check_u64 (SD_, instruction_0);
2773   do_dclo (SD_, RT, RS);
2774 }
2775
2776 010110,5.RT,5.RS,0101101100,111100:POOL32S:64::DCLZ
2777 "dclz r<RT>, r<RS>"
2778 *micromips64:
2779 {
2780   check_u64 (SD_, instruction_0);
2781   do_dclz (SD_, RT, RS);
2782 }
2783
2784 010110,5.RT,5.RS,1010101100,111100:POOL32S:64::DDIV
2785 "ddiv r<RS>, r<RT>"
2786 *micromips64:
2787 {
2788   check_u64 (SD_, instruction_0);
2789   do_ddiv (SD_, RS, RT);
2790 }
2791
2792 010110,5.RT,5.RS,1011101100,111100:POOL32S:64::DDIVU
2793 "ddivu r<RS>, r<RT>"
2794 *micromips64:
2795 {
2796   check_u64 (SD_, instruction_0);
2797   do_ddivu (SD_, RS, RT);
2798 }
2799
2800 010110,5.RT,5.RS,5.SIZE,5.LSB,101100:POOL32S:64::DEXT
2801 "dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
2802 *micromips64:
2803 {
2804   check_u64 (SD_, instruction_0);
2805   do_dext (SD_, RT, RS, LSB, SIZE);
2806 }
2807
2808 010110,5.RT,5.RS,5.SIZE,5.LSB,100100:POOL32S:64::DEXTM
2809 "dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
2810 *micromips64:
2811 {
2812   check_u64 (SD_, instruction_0);
2813   do_dextm (SD_, RT, RS, LSB, SIZE);
2814 }
2815
2816 010110,5.RT,5.RS,5.SIZE,5.LSB,010100:POOL32S:64::DEXTU
2817 "dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
2818 *micromips64:
2819 {
2820   check_u64 (SD_, instruction_0);
2821   do_dextu (SD_, RT, RS, LSB, SIZE);
2822 }
2823
2824 010110,5.RT,5.RS,5.MSB,5.LSB,001100:POOL32S:64::DINS
2825 "dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
2826 *micromips64:
2827 {
2828   check_u64 (SD_, instruction_0);
2829   do_dins (SD_, RT, RS, LSB, MSB);
2830 }
2831
2832 010110,5.RT,5.RS,5.MSB,5.LSB,000100:POOL32S:64::DINSM
2833 "dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
2834 *micromips64:
2835 {
2836   check_u64 (SD_, instruction_0);
2837   do_dinsm (SD_, RT, RS, LSB, MSB);
2838 }
2839
2840 010110,5.RT,5.RS,5.MSB,5.LSB,110100:POOL32S:64::DINSU
2841 "dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
2842 *micromips64:
2843 {
2844   check_u64 (SD_, instruction_0);
2845   do_dinsu (SD_, RT, RS, LSB, MSB);
2846 }
2847
2848 010110,5.RT,5.RS,00,3.SEL,00011,111100:POOL32S:64::DMFC0
2849 "dmfc0 r<RT>, r<RS>": SEL == 0
2850 "dmfc0 r<RT>, r<RS>, <SEL>"
2851 *micromips64:
2852 {
2853   check_u64 (SD_, instruction_0);
2854   DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RS, SEL);
2855 }
2856
2857 010101,5.RT,5.FS,00,10010000,111011:POOL32F:64::DMFC1
2858 "dmfc1 r<RT>, f<FS>"
2859 *micromips64:
2860 {
2861   check_fpu (SD_);
2862   check_u64 (SD_, instruction_0);
2863   do_dmfc1b (SD_, RT, FS);
2864 }
2865
2866 010110,5.RT,5.RS,00,3.SEL,01011,111100:POOL32S:64::DMTC0
2867 "dmtc0 r<RT>, r<RS>": SEL == 0
2868 "dmtc0 r<RT>, r<RS>, <SEL>"
2869 *micromips64:
2870 {
2871   check_u64 (SD_, instruction_0);
2872   DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RS, SEL);
2873 }
2874
2875 010101,5.RT,5.FS,00,10110000,111011:POOL32F:64::DMTC1
2876 "dmtc1 r<RT>, f<FS>"
2877 *micromips64:
2878 {
2879   check_fpu (SD_);
2880   check_u64 (SD_, instruction_0);
2881   do_dmtc1b (SD_, RT, FS);
2882 }
2883
2884 010110,5.RT,5.RS,1000101100,111100:POOL32S:64::DMULT
2885 "dmult r<RS>, r<RT>"
2886 *micromips64:
2887 {
2888   check_u64 (SD_, instruction_0);
2889   do_dmult (SD_, RS, RT, 0);
2890 }
2891
2892 010110,5.RT,5.RS,1001101100,111100:POOL32S:64::DMULTU
2893 "dmultu r<RS>, r<RT>"
2894 *micromips64:
2895 {
2896   check_u64 (SD_, instruction_0);
2897   do_dmultu (SD_, RS, RT, 0);
2898 }
2899
2900 010110,5.RT,5.RS,5.SA,00,011000000:POOL32S:64::DROTR
2901 "drotr r<RT>, r<RS>, <SA>"
2902 *micromips64:
2903 {
2904   check_u64 (SD_, instruction_0);
2905   GPR[RT] = do_dror (SD_, GPR[RS], SA);
2906 }
2907
2908 010110,5.RT,5.RS,5.SA,00,011001000:POOL32S:64::DROTR32
2909 "drotr32 r<RT>, r<RS>, <SA+32>"
2910 *micromips64:
2911 {
2912   check_u64 (SD_, instruction_0);
2913   GPR[RT] = do_dror (SD_, GPR[RS], SA + 32);
2914 }
2915
2916 010110,5.RT,5.RS,5.RD,00,011010000:POOL32S:64::DROTRV
2917 "drotrv r<RD>, r<RT>, r<RS>"
2918 *micromips64:
2919 {
2920   check_u64 (SD_, instruction_0);
2921   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
2922 }
2923
2924 010110,5.RT,5.RS,0111101100,111100:POOL32S:64::DSBH
2925 "dsbh r<RT>, r<RS>"
2926 *micromips64:
2927 {
2928   check_u64 (SD_, instruction_0);
2929   do_dsbh (SD_, RT, RS);
2930 }
2931
2932 010110,5.RT,5.RS,1111101100,111100:POOL32S:64::DSHD
2933 "dshd r<RT>, r<RS>"
2934 *micromips64:
2935 {
2936   check_u64 (SD_, instruction_0);
2937   do_dshd (SD_, RS, RT);
2938 }
2939
2940 010110,5.RT,5.RS,5.SA,00,000000000:POOL32S:64::DSLL
2941 "dsll r<RT>, r<RS>, <SA>"
2942 *micromips64:
2943 {
2944   check_u64 (SD_, instruction_0);
2945   do_dsll (SD_, RS, RT, SA);
2946 }
2947
2948 010110,5.RT,5.RS,5.SA,00,000001000:POOL32S:64::DSLL32
2949 "dsll32 r<RT>, r<RS>, <SA>"
2950 *micromips64:
2951 {
2952   check_u64 (SD_, instruction_0);
2953   do_dsll32 (SD_, RT, RS, SA);
2954 }
2955
2956 010110,5.RT,5.RS,5.RD,00,000010000:POOL32S:64::DSLLV
2957 "dsllv r<RD>, r<RT>, r<RS>"
2958 *micromips64:
2959 {
2960   check_u64 (SD_, instruction_0);
2961   do_dsllv (SD_, RS, RT, RD);
2962 }
2963
2964 010110,5.RT,5.RS,5.SA,00,010000000:POOL32S:64::DSRA
2965 "dsra r<RT>, r<RS>, <SA>"
2966 *micromips64:
2967 {
2968   check_u64 (SD_, instruction_0);
2969   do_dsra (SD_, RS, RT, SA);
2970 }
2971
2972 010110,5.RT,5.RS,5.SA,00,010001000:POOL32S:64::DSRA32
2973 "dsra32 r<RT>, r<RS>, <SA>"
2974 *micromips64:
2975 {
2976   check_u64 (SD_, instruction_0);
2977   do_dsra32 (SD_, RT, RS, SA);
2978 }
2979
2980 010110,5.RT,5.RS,5.RD,00,010010000:POOL32S:64::DSRAV
2981 "dsrav r<RD>, r<RS>, r<RT>"
2982 *micromips64:
2983 {
2984   check_u64 (SD_, instruction_0);
2985   do_dsrav (SD_, RS, RT, RD);
2986 }
2987
2988 010110,5.RT,5.RS,5.SA,00,001000000:POOL32S:64::DSRL
2989 "dsrl r<RT>, r<RS>, <SA>"
2990 *micromips64:
2991 {
2992   check_u64 (SD_, instruction_0);
2993   do_dsrl (SD_, RS, RT, SA);
2994 }
2995
2996 010110,5.RT,5.RS,5.SA,00,001001000:POOL32S:64::DSRL32
2997 "dsrl32 r<RT>, r<RS>, <SA>"
2998 *micromips64:
2999 {
3000   check_u64 (SD_, instruction_0);
3001   do_dsrl32 (SD_, RT, RS, SA);
3002 }
3003
3004 010110,5.RT,5.RS,5.RD,00,001010000:POOL32S:64::DSRLV
3005 "dsrlv r<RD>, r<RT>, r<RS>"
3006 *micromips64:
3007 {
3008   check_u64 (SD_, instruction_0);
3009   do_dsrlv (SD_, RS, RT, RD);
3010 }
3011
3012 010110,5.RT,5.RS,5.RD,00,110001000:POOL32S:64::DSUB
3013 "dsub r<RD>, r<RS>, r<RT>"
3014 *micromips64:
3015 {
3016   check_u64 (SD_, instruction_0);
3017   do_dsub (SD_, RD, RS, RT);
3018 }
3019
3020 010110,5.RT,5.RS,5.RD,00,111001000:POOL32S:64::DSUBU
3021 "dsubu r<RD>, r<RS>, r<RT>"
3022 *micromips64:
3023 {
3024   check_u64 (SD_, instruction_0);
3025   do_dsubu (SD_, RS, RT, RD);
3026 }
3027
3028 110111,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::LD
3029 "ld r<RT>, <OFFSET>(r<BASE>)"
3030 *micromips64:
3031 {
3032   check_u64 (SD_, instruction_0);
3033   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3034                                EXTEND16 (OFFSET)));
3035 }
3036
3037 011000,5.RT,5.BASE,0100,12.OFFSET:POOL32C:64::LDL
3038 "ldl r<RT>, <OFFSET>(r<BASE>)"
3039 *micromips64:
3040 {
3041   check_u64 (SD_, instruction_0);
3042   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3043                           EXTEND12 (OFFSET), GPR[RT]);
3044 }
3045
3046 011000,5.RT,5.BASE,0101,12.OFFSET:POOL32C:64::LDR
3047 "ldr r<RT>, <OFFSET>(r<BASE>)"
3048 *micromips64:
3049 {
3050   check_u64 (SD_, instruction_0);
3051   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3052                            EXTEND12 (OFFSET), GPR[RT]);
3053 }
3054
3055 010101,5.INDEX,5.BASE,5.FD,00,011001000:POOL32F:64,f::LDXC1
3056 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3057 *micromips64:
3058 {
3059   check_fpu (SD_);
3060   check_u64 (SD_, instruction_0);
3061   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3062 }
3063
3064 011000,5.RT,5.BASE,0111,12.OFFSET:POOL32C:64::LLD
3065 "lld r<RT>, <OFFSET>(r<BASE>)"
3066 *micromips64:
3067 {
3068   check_u64 (SD_, instruction_0);
3069   do_lld (SD_, RT, OFFSET, BASE);
3070 }
3071
3072 011000,5.RT,5.BASE,1111,12.OFFSET:POOL32C:64::SCD
3073 "scd r<RT>, <OFFSET>(r<BASE>)"
3074 *micromips64:
3075 {
3076   check_u64 (SD_, instruction_0);
3077   do_scd (SD_, RT, OFFSET, BASE, 1);
3078 }
3079
3080 110110,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::SD
3081 "sd r<RT>, <OFFSET>(r<BASE>)"
3082 *micromips64:
3083 {
3084   check_u64 (SD_, instruction_0);
3085   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET),
3086             GPR[RT]);
3087 }
3088
3089 011000,5.RT,5.BASE,1100,12.OFFSET:POOL32C:64::SDL
3090 "sdl r<RT>, <OFFSET>(r<BASE>)"
3091 *micromips64:
3092 {
3093   check_u64 (SD_, instruction_0);
3094   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
3095                  GPR[RT]);
3096 }
3097
3098 011000,5.RT,5.BASE,1101,12.OFFSET:POOL32C:64::SDR
3099 "sdr r<RT>, <OFFSET>(r<BASE>)"
3100 *micromips64:
3101 {
3102   check_u64 (SD_, instruction_0);
3103   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
3104                   GPR[RT]);
3105 }
3106
3107 010101,5.INDEX,5.BASE,5.FD,00,100001000:POOL32F:64,f::SDXC1
3108 "sdxc1 f<FD>, r<INDEX>(r<BASE>)"
3109 *micromips64:
3110 {
3111   check_fpu (SD_);
3112   check_u64 (SD_, instruction_0);
3113   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX],
3114             COP_SD (1, FD));
3115 }