sim/mn10300/dv-mn103tim.c

   1 /*  This file is part of the program GDB, the GNU debugger.
   2
   3     Copyright (C) 1998-2024 Free Software Foundation, Inc.
   4     Contributed by Cygnus Solutions.
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 3 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18
  19     */
  20
  21 /* This must come before any other includes.  */
  22 #include "defs.h"
  23
  24 #include "sim-main.h"
  25 #include "hw-main.h"
  26 #include "sim-assert.h"
  27
  28 /* DEVICE
  29
  30
  31    mn103tim - mn103002 timers (8 and 16 bit)
  32
  33
  34    DESCRIPTION
  35
  36    Implements the mn103002 8 and 16 bit timers as described in the mn103002 user guide.
  37
  38
  39    PROPERTIES
  40
  41    reg = <8bit-timers-addr> <8bit-timers-size> <16bit-timers-addr> <16bit-timers-size>
  42
  43
  44    BUGS
  45
  46    */
  47
  48
  49 /* The timers' register address blocks */
  50
  51 struct mn103tim_block {
  52   unsigned_word base;
  53   unsigned_word bound;
  54 };
  55
  56 enum { TIMER8_BLOCK, TIMER16_BLOCK, NR_TIMER_BLOCKS };
  57
  58 enum timer_register_types {
  59   FIRST_MODE_REG = 0,
  60   TM0MD = FIRST_MODE_REG,
  61   TM1MD,
  62   TM2MD,
  63   TM3MD,
  64   TM4MD,
  65   TM5MD,
  66   TM6MD,
  67   LAST_MODE_REG = TM6MD,
  68   FIRST_BASE_REG,
  69   TM0BR = FIRST_BASE_REG,
  70   TM1BR,
  71   TM2BR,
  72   TM3BR,
  73   TM4BR,
  74   TM5BR,
  75   LAST_BASE_REG = TM5BR,
  76   FIRST_COUNTER,
  77   TM0BC = FIRST_COUNTER,
  78   TM1BC,
  79   TM2BC,
  80   TM3BC,
  81   TM4BC,
  82   TM5BC,
  83   TM6BC,
  84   LAST_COUNTER = TM6BC,
  85   TM6MDA,
  86   TM6MDB,
  87   TM6CA,
  88   TM6CB,
  89   LAST_TIMER_REG = TM6CB,
  90 };
  91
  92
  93 /* Don't include timer 6 because it's handled specially. */
  94 #define NR_8BIT_TIMERS 4
  95 #define NR_16BIT_TIMERS 2
  96 #define NR_REG_TIMERS 6 /* Exclude timer 6 - it's handled specially. */
  97 #define NR_TIMERS 7
  98
  99 typedef struct _mn10300_timer_regs {
 100   uint32_t base;
 101   uint8_t  mode;
 102 } mn10300_timer_regs;
 103
 104 typedef struct _mn10300_timer {
 105   uint32_t div_ratio, start;
 106   struct hw_event *event;
 107 } mn10300_timer;
 108
 109
 110 struct mn103tim {
 111   struct mn103tim_block block[NR_TIMER_BLOCKS];
 112   mn10300_timer_regs reg[NR_REG_TIMERS];
 113   mn10300_timer timer[NR_TIMERS];
 114
 115   /* treat timer 6 registers specially. */
 116   uint16_t   tm6md0, tm6md1, tm6bc, tm6ca, tm6cb;
 117   uint8_t  tm6mda, tm6mdb;  /* compare/capture mode regs for timer 6 */
 118 };
 119
 120 /* output port ID's */
 121
 122 /* for mn103002 */
 123 enum {
 124   TIMER0_UFLOW,
 125   TIMER1_UFLOW,
 126   TIMER2_UFLOW,
 127   TIMER3_UFLOW,
 128   TIMER4_UFLOW,
 129   TIMER5_UFLOW,
 130   TIMER6_UFLOW,
 131   TIMER6_CMPA,
 132   TIMER6_CMPB,
 133 };
 134
 135
 136 static const struct hw_port_descriptor mn103tim_ports[] = {
 137
 138   { "timer-0-underflow", TIMER0_UFLOW, 0, output_port, },
 139   { "timer-1-underflow", TIMER1_UFLOW, 0, output_port, },
 140   { "timer-2-underflow", TIMER2_UFLOW, 0, output_port, },
 141   { "timer-3-underflow", TIMER3_UFLOW, 0, output_port, },
 142   { "timer-4-underflow", TIMER4_UFLOW, 0, output_port, },
 143   { "timer-5-underflow", TIMER5_UFLOW, 0, output_port, },
 144
 145   { "timer-6-underflow", TIMER6_UFLOW, 0, output_port, },
 146   { "timer-6-compare-a", TIMER6_CMPA, 0, output_port, },
 147   { "timer-6-compare-b", TIMER6_CMPB, 0, output_port, },
 148
 149   { NULL, },
 150 };
 151
 152 #define bits2to5_mask 0x3c
 153 #define bits0to2_mask 0x07
 154 #define load_mask     0x40
 155 #define count_mask    0x80
 156 #define count_and_load_mask (load_mask | count_mask)
 157 #define clock_mask    0x03
 158 #define clk_ioclk    0x00
 159 #define clk_cascaded 0x03
 160
 161
 162 /* Finish off the partially created hw device.  Attach our local
 163    callbacks.  Wire up our port names etc */
 164
 165 static hw_io_read_buffer_method mn103tim_io_read_buffer;
 166 static hw_io_write_buffer_method mn103tim_io_write_buffer;
 167
 168 static void
 169 attach_mn103tim_regs (struct hw *me,
 170                       struct mn103tim *timers)
 171 {
 172   int i;
 173   if (hw_find_property (me, "reg") == NULL)
 174     hw_abort (me, "Missing \"reg\" property");
 175   for (i = 0; i < NR_TIMER_BLOCKS; i++)
 176     {
 177       unsigned_word attach_address;
 178       int attach_space;
 179       unsigned attach_size;
 180       reg_property_spec reg;
 181       if (!hw_find_reg_array_property (me, "reg", i, &reg))
 182         hw_abort (me, "\"reg\" property must contain three addr/size entries");
 183       hw_unit_address_to_attach_address (hw_parent (me),
 184                                          &reg.address,
 185                                          &attach_space,
 186                                          &attach_address,
 187                                          me);
 188       timers->block[i].base = attach_address;
 189       hw_unit_size_to_attach_size (hw_parent (me),
 190                                    &reg.size,
 191                                    &attach_size, me);
 192       timers->block[i].bound = attach_address + (attach_size - 1);
 193       hw_attach_address (hw_parent (me),
 194                          0,
 195                          attach_space, attach_address, attach_size,
 196                          me);
 197     }
 198 }
 199
 200 static void
 201 mn103tim_finish (struct hw *me)
 202 {
 203   struct mn103tim *timers;
 204   int i;
 205
 206   timers = HW_ZALLOC (me, struct mn103tim);
 207   set_hw_data (me, timers);
 208   set_hw_io_read_buffer (me, mn103tim_io_read_buffer);
 209   set_hw_io_write_buffer (me, mn103tim_io_write_buffer);
 210   set_hw_ports (me, mn103tim_ports);
 211
 212   /* Attach ourself to our parent bus */
 213   attach_mn103tim_regs (me, timers);
 214
 215   /* Initialize the timers */
 216   for ( i=0; i < NR_REG_TIMERS; ++i )
 217     {
 218       timers->reg[i].mode = 0x00;
 219       timers->reg[i].base = 0;
 220     }
 221   for ( i=0; i < NR_TIMERS; ++i )
 222     {
 223       timers->timer[i].event = NULL;
 224       timers->timer[i].div_ratio = 0;
 225       timers->timer[i].start = 0;
 226     }
 227   timers->tm6md0 = 0x00;
 228   timers->tm6md1 = 0x00;
 229   timers->tm6bc = 0x0000;
 230   timers->tm6ca = 0x0000;
 231   timers->tm6cb = 0x0000;
 232   timers->tm6mda = 0x00;
 233   timers->tm6mdb = 0x00;
 234 }
 235
 236
 237
 238 /* read and write */
 239
 240 static int
 241 decode_addr (struct hw *me,
 242              struct mn103tim *timers,
 243              unsigned_word address)
 244 {
 245   unsigned_word offset;
 246   offset = address - timers->block[0].base;
 247
 248   switch (offset)
 249     {
 250     case 0x00: return TM0MD;
 251     case 0x01: return TM1MD;
 252     case 0x02: return TM2MD;
 253     case 0x03: return TM3MD;
 254     case 0x10: return TM0BR;
 255     case 0x11: return TM1BR;
 256     case 0x12: return TM2BR;
 257     case 0x13: return TM3BR;
 258     case 0x20: return TM0BC;
 259     case 0x21: return TM1BC;
 260     case 0x22: return TM2BC;
 261     case 0x23: return TM3BC;
 262     case 0x80: return TM4MD;
 263     case 0x82: return TM5MD;
 264     case 0x84: /* fall through */
 265     case 0x85: return TM6MD;
 266     case 0x90: return TM4BR;
 267     case 0x92: return TM5BR;
 268     case 0xa0: return TM4BC;
 269     case 0xa2: return TM5BC;
 270     case 0xa4: return TM6BC;
 271     case 0xb4: return TM6MDA;
 272     case 0xb5: return TM6MDB;
 273     case 0xc4: return TM6CA;
 274     case 0xd4: return TM6CB;
 275     default:
 276       {
 277         hw_abort (me, "bad address");
 278         return -1;
 279       }
 280     }
 281 }
 282
 283 static void
 284 read_mode_reg (struct hw *me,
 285                struct mn103tim *timers,
 286                int timer_nr,
 287                void *dest,
 288                unsigned nr_bytes)
 289 {
 290   uint16_t val16;
 291   uint32_t val32;
 292
 293   switch ( nr_bytes )
 294     {
 295     case 1:
 296       /* Accessing 1 byte is ok for all mode registers. */
 297       if ( timer_nr == 6 )
 298         {
 299           *(uint8_t*)dest = timers->tm6md0;
 300         }
 301       else
 302         {
 303           *(uint8_t*)dest = timers->reg[timer_nr].mode;
 304         }
 305       break;
 306
 307     case 2:
 308       if ( timer_nr == 6 )
 309         {
 310           *(uint16_t *)dest = (timers->tm6md0 << 8) | timers->tm6md1;
 311         }
 312       else if ( timer_nr == 0 || timer_nr == 2 )
 313         {
 314           val16 = (timers->reg[timer_nr].mode << 8)
 315             | timers->reg[timer_nr+1].mode;
 316           *(uint16_t*)dest = val16;
 317         }
 318       else
 319         {
 320           hw_abort (me, "bad read size of 2 bytes to TM%dMD.", timer_nr);
 321         }
 322       break;
 323
 324     case 4:
 325       if ( timer_nr == 0 )
 326         {
 327           val32 = (timers->reg[0].mode << 24 )
 328             | (timers->reg[1].mode << 16)
 329             | (timers->reg[2].mode << 8)
 330             | timers->reg[3].mode;
 331           *(uint32_t*)dest = val32;
 332         }
 333       else
 334         {
 335           hw_abort (me, "bad read size of 4 bytes to TM%dMD.", timer_nr);
 336         }
 337       break;
 338
 339     default:
 340       hw_abort (me, "bad read size of %d bytes to TM%dMD.",
 341                 nr_bytes, timer_nr);
 342     }
 343 }
 344
 345
 346 static void
 347 read_base_reg (struct hw *me,
 348                struct mn103tim *timers,
 349                int timer_nr,
 350                void *dest,
 351                unsigned  nr_bytes)
 352 {
 353   uint16_t val16;
 354   uint32_t val32;
 355
 356   /* Check nr_bytes: accesses of 1, 2 and 4 bytes allowed depending on timer. */
 357   switch ( nr_bytes )
 358     {
 359     case 1:
 360       /* Reading 1 byte is ok for all registers. */
 361       if ( timer_nr < NR_8BIT_TIMERS )
 362         {
 363           *(uint8_t*)dest = timers->reg[timer_nr].base;
 364         }
 365       break;
 366
 367     case 2:
 368       if ( timer_nr == 1 || timer_nr == 3 )
 369         {
 370           hw_abort (me, "bad read size of 2 bytes to TM%dBR.", timer_nr);
 371         }
 372       else
 373         {
 374           if ( timer_nr < NR_8BIT_TIMERS )
 375             {
 376               val16 = (timers->reg[timer_nr].base<<8)
 377                 | timers->reg[timer_nr+1].base;
 378             }
 379           else
 380             {
 381               val16 = timers->reg[timer_nr].base;
 382             }
 383           *(uint16_t*)dest = val16;
 384         }
 385       break;
 386
 387     case 4:
 388       if ( timer_nr == 0 )
 389         {
 390           val32 = (timers->reg[0].base << 24) | (timers->reg[1].base << 16)
 391             | (timers->reg[2].base << 8) | timers->reg[3].base;
 392           *(uint32_t*)dest = val32;
 393         }
 394       else if ( timer_nr == 4 )
 395         {
 396           val32 = (timers->reg[4].base << 16) | timers->reg[5].base;
 397           *(uint32_t*)dest = val32;
 398         }
 399       else
 400         {
 401           hw_abort (me, "bad read size of 4 bytes to TM%dBR.", timer_nr);
 402         }
 403       break;
 404
 405     default:
 406       hw_abort (me, "bad read size must of %d bytes to TM%dBR.",
 407                 nr_bytes, timer_nr);
 408     }
 409 }
 410
 411
 412 static void
 413 read_counter (struct hw *me,
 414               struct mn103tim *timers,
 415               int timer_nr,
 416               void *dest,
 417               unsigned  nr_bytes)
 418 {
 419   uint32_t val;
 420
 421   if ( NULL == timers->timer[timer_nr].event )
 422     {
 423       /* Timer is not counting, use value in base register. */
 424       if ( timer_nr == 6 )
 425         {
 426           val = 0;  /* timer 6 is an up counter */
 427         }
 428       else
 429         {
 430           val = timers->reg[timer_nr].base;
 431         }
 432     }
 433   else
 434     {
 435       if ( timer_nr == 6 )  /* timer 6 is an up counter. */
 436         {
 437           val = hw_event_queue_time(me) - timers->timer[timer_nr].start;
 438         }
 439       else
 440         {
 441           /* ticks left = start time + div ratio - curr time */
 442           /* Cannot use base register because it can be written during counting and it
 443              doesn't affect counter until underflow occurs. */
 444
 445           val = timers->timer[timer_nr].start + timers->timer[timer_nr].div_ratio
 446             - hw_event_queue_time(me);
 447         }
 448     }
 449
 450   switch (nr_bytes) {
 451   case 1:
 452     *(uint8_t *)dest = val;
 453     break;
 454
 455   case 2:
 456     *(uint16_t *)dest = val;
 457     break;
 458
 459   case 4:
 460     *(uint32_t *)dest = val;
 461     break;
 462
 463   default:
 464     hw_abort(me, "bad read size for reading counter");
 465   }
 466
 467 }
 468
 469
 470 static void
 471 read_special_timer6_reg (struct hw *me,
 472                          struct mn103tim *timers,
 473                          int timer_nr,
 474                          void *dest,
 475                          unsigned  nr_bytes)
 476 {
 477   switch (nr_bytes) {
 478   case 1:
 479     {
 480       switch ( timer_nr ) {
 481       case TM6MDA:
 482         *(uint8_t *)dest = timers->tm6mda;
 483         break;
 484
 485       case TM6MDB:
 486         *(uint8_t *)dest = timers->tm6mdb;
 487         break;
 488
 489       case TM6CA:
 490         *(uint8_t *)dest = timers->tm6ca;
 491         break;
 492
 493       case TM6CB:
 494         *(uint8_t *)dest = timers->tm6cb;
 495         break;
 496
 497       default:
 498         break;
 499       }
 500       break;
 501     }
 502
 503   case 2:
 504     if ( timer_nr == TM6CA )
 505       {
 506         *(uint16_t *)dest = timers->tm6ca;
 507       }
 508     else if ( timer_nr == TM6CB )
 509       {
 510         *(uint16_t *)dest = timers->tm6cb;
 511       }
 512     else
 513       {
 514         hw_abort(me, "bad read size for timer 6 mode A/B register");
 515       }
 516     break;
 517
 518   default:
 519     hw_abort(me, "bad read size for timer 6 register");
 520   }
 521
 522 }
 523
 524
 525 static unsigned
 526 mn103tim_io_read_buffer (struct hw *me,
 527                          void *dest,
 528                          int space,
 529                          unsigned_word base,
 530                          unsigned nr_bytes)
 531 {
 532   struct mn103tim *timers = hw_data (me);
 533   enum timer_register_types timer_reg;
 534
 535   HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
 536
 537   timer_reg = decode_addr (me, timers, base);
 538
 539   /* It can be either a mode register, a base register, a binary counter, */
 540   /* or a special timer 6 register.  Check in that order. */
 541   if ( timer_reg >= FIRST_MODE_REG && timer_reg <= LAST_MODE_REG )
 542     {
 543       read_mode_reg(me, timers, timer_reg-FIRST_MODE_REG, dest, nr_bytes);
 544     }
 545   else if ( timer_reg <= LAST_BASE_REG )
 546     {
 547       read_base_reg(me, timers, timer_reg-FIRST_BASE_REG, dest, nr_bytes);
 548     }
 549   else if ( timer_reg <= LAST_COUNTER )
 550     {
 551       read_counter(me, timers, timer_reg-FIRST_COUNTER, dest, nr_bytes);
 552     }
 553   else if ( timer_reg <= LAST_TIMER_REG )
 554     {
 555       read_special_timer6_reg(me, timers, timer_reg, dest, nr_bytes);
 556     }
 557   else
 558     {
 559       hw_abort(me, "invalid timer register address.");
 560     }
 561
 562   return nr_bytes;
 563 }
 564
 565
 566 static void
 567 do_counter_event (struct hw *me,
 568                   void *data)
 569 {
 570   struct mn103tim *timers = hw_data(me);
 571   long timer_nr = (uintptr_t) data;
 572   int next_timer;
 573
 574   /* Check if counting is still enabled. */
 575   if ( (timers->reg[timer_nr].mode & count_mask) != 0 )
 576     {
 577       /* Generate an interrupt for the timer underflow (TIMERn_UFLOW). */
 578
 579       /* Port event occurs on port of last cascaded timer. */
 580       /* This works across timer range from 0 to NR_REG_TIMERS because */
 581       /* the first 16 bit timer (timer 4) is not allowed to be set as  */
 582       /* a cascading timer. */
 583       for ( next_timer = timer_nr+1; next_timer < NR_REG_TIMERS; ++next_timer )
 584         {
 585           if ( (timers->reg[next_timer].mode & clock_mask) != clk_cascaded )
 586             {
 587               break;
 588             }
 589         }
 590       hw_port_event (me, next_timer-1, 1);
 591
 592       /* Schedule next timeout.  */
 593       timers->timer[timer_nr].start = hw_event_queue_time(me);
 594       /* FIX: Check if div_ratio has changed and if it's now 0. */
 595       timers->timer[timer_nr].event
 596         = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio,
 597                                    do_counter_event, (void *)(uintptr_t)timer_nr);
 598     }
 599   else
 600     {
 601       timers->timer[timer_nr].event = NULL;
 602     }
 603
 604 }
 605
 606
 607 static void
 608 do_counter6_event (struct hw *me,
 609                   void *data)
 610 {
 611   struct mn103tim *timers = hw_data(me);
 612   long timer_nr = (uintptr_t) data;
 613
 614   /* Check if counting is still enabled. */
 615   if ( (timers->reg[timer_nr].mode & count_mask) != 0 )
 616     {
 617       /* Generate an interrupt for the timer underflow (TIMERn_UFLOW). */
 618       hw_port_event (me, timer_nr, 1);
 619
 620       /* Schedule next timeout.  */
 621       timers->timer[timer_nr].start = hw_event_queue_time(me);
 622       /* FIX: Check if div_ratio has changed and if it's now 0. */
 623       timers->timer[timer_nr].event
 624         = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio,
 625                                    do_counter6_event, (void *)(uintptr_t)timer_nr);
 626     }
 627   else
 628     {
 629       timers->timer[timer_nr].event = NULL;
 630     }
 631
 632 }
 633
 634 static void
 635 write_base_reg (struct hw *me,
 636                 struct mn103tim *timers,
 637                 int timer_nr,
 638                 const void *source,
 639                 unsigned  nr_bytes)
 640 {
 641   const uint8_t *buf8 = source;
 642   const uint16_t *buf16 = source;
 643
 644   /* If TMnCNE == 0 (counting is off),  writing to the base register
 645      (TMnBR) causes a simultaneous write to the counter reg (TMnBC).
 646      Else, the TMnBC is reloaded with the value from TMnBR when
 647      underflow occurs.  Since the counter register is not explicitly
 648      maintained, this functionality is handled in read_counter. */
 649
 650   /* Check nr_bytes: write of 1, 2 or 4 bytes allowed depending on timer. */
 651   switch ( nr_bytes )
 652     {
 653     case 1:
 654       /* Storing 1 byte is ok for all registers. */
 655       timers->reg[timer_nr].base = buf8[0];
 656       break;
 657
 658     case 2:
 659       if ( timer_nr == 1 || timer_nr == 3 )
 660         {
 661           hw_abort (me, "bad write size of 2 bytes to TM%dBR.", timer_nr);
 662         }
 663       else
 664         {
 665           if ( timer_nr < NR_8BIT_TIMERS )
 666             {
 667               timers->reg[timer_nr].base = buf8[0];
 668               timers->reg[timer_nr+1].base = buf8[1];
 669             }
 670           else
 671             {
 672               timers->reg[timer_nr].base = buf16[0];
 673             }
 674         }
 675       break;
 676
 677     case 4:
 678       if ( timer_nr == 0 )
 679         {
 680           timers->reg[0].base = buf8[0];
 681           timers->reg[1].base = buf8[1];
 682           timers->reg[2].base = buf8[2];
 683           timers->reg[3].base = buf8[3];
 684         }
 685       else if ( timer_nr == 4 )
 686         {
 687           timers->reg[4].base = buf16[0];
 688           timers->reg[5].base = buf16[1];
 689         }
 690       else
 691         {
 692           hw_abort (me, "bad write size of 4 bytes to TM%dBR.", timer_nr);
 693         }
 694       break;
 695
 696     default:
 697       hw_abort (me, "bad write size must of %d bytes to TM%dBR.",
 698                 nr_bytes, timer_nr);
 699     }
 700
 701 }
 702
 703 static void
 704 write_mode_reg (struct hw *me,
 705                 struct mn103tim *timers,
 706                 long timer_nr,
 707                 const void *source,
 708                 unsigned nr_bytes)
 709      /* for timers 0 to 5 */
 710 {
 711   unsigned i;
 712   uint8_t mode_val, next_mode_val;
 713   uint32_t div_ratio;
 714
 715   if ( nr_bytes != 1 )
 716     {
 717       hw_abort (me, "bad write size of %d bytes to TM%ldMD.", nr_bytes,
 718                 timer_nr);
 719     }
 720
 721   mode_val = *(uint8_t *)source;
 722   timers->reg[timer_nr].mode = mode_val;
 723
 724   if ( ( mode_val & count_and_load_mask ) == count_and_load_mask )
 725     {
 726       hw_abort(me, "Cannot load base reg and start counting simultaneously.");
 727     }
 728   if ( ( mode_val & bits2to5_mask ) != 0 )
 729     {
 730       hw_abort(me, "Cannot write to bits 2 to 5 of mode register");
 731     }
 732
 733   if ( mode_val & count_mask )
 734     {
 735       /* - de-schedule any previous event. */
 736       /* - add new event to queue to start counting. */
 737       /* - assert that counter == base reg? */
 738
 739       /* For cascaded timers, */
 740       if ( (mode_val & clock_mask) == clk_cascaded )
 741         {
 742           if ( timer_nr == 0 || timer_nr == 4 )
 743             {
 744               hw_abort(me, "Timer %ld cannot be cascaded.", timer_nr);
 745             }
 746         }
 747       else
 748         {
 749           div_ratio = timers->reg[timer_nr].base;
 750
 751           /* Check for cascading. */
 752           if ( timer_nr < NR_8BIT_TIMERS )
 753             {
 754               for ( i = timer_nr + 1; i <= 3; ++i )
 755                 {
 756                   next_mode_val = timers->reg[i].mode;
 757                   if ( ( next_mode_val & clock_mask ) == clk_cascaded )
 758                     {
 759                       /* Check that CNE is on. */
 760                       if ( ( next_mode_val & count_mask ) == 0 )
 761                         {
 762                           hw_abort (me, "cascaded timer not ready for counting");
 763                         }
 764                       ASSERT(timers->timer[i].event == NULL);
 765                       ASSERT(timers->timer[i].div_ratio == 0);
 766                       div_ratio = div_ratio
 767                         | (timers->reg[i].base << (8*(i-timer_nr)));
 768                     }
 769                   else
 770                     {
 771                       break;
 772                     }
 773                 }
 774             }
 775           else
 776             {
 777               /* Mode register for a 16 bit timer */
 778               next_mode_val = timers->reg[timer_nr+1].mode;
 779               if ( ( next_mode_val & clock_mask ) == clk_cascaded )
 780                 {
 781                   /* Check that CNE is on. */
 782                   if ( ( next_mode_val & count_mask ) == 0 )
 783                     {
 784                       hw_abort (me, "cascaded timer not ready for counting");
 785                     }
 786                   ASSERT(timers->timer[timer_nr+1].event == NULL);
 787                   ASSERT(timers->timer[timer_nr+1].div_ratio == 0);
 788                   div_ratio = div_ratio | (timers->reg[timer_nr+1].base << 16);
 789                 }
 790             }
 791
 792           timers->timer[timer_nr].div_ratio = div_ratio;
 793
 794           if ( NULL != timers->timer[timer_nr].event )
 795             {
 796               hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
 797               timers->timer[timer_nr].event = NULL;
 798             }
 799
 800           if ( div_ratio > 0 )
 801             {
 802               /* Set start time. */
 803               timers->timer[timer_nr].start = hw_event_queue_time(me);
 804               timers->timer[timer_nr].event
 805                 = hw_event_queue_schedule(me, div_ratio,
 806                                           do_counter_event,
 807                                           (void *)(uintptr_t)timer_nr);
 808             }
 809         }
 810     }
 811   else
 812     {
 813       /* Turn off counting */
 814       if ( NULL != timers->timer[timer_nr].event )
 815         {
 816           ASSERT((timers->reg[timer_nr].mode & clock_mask) != clk_cascaded);
 817           hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
 818           timers->timer[timer_nr].event = NULL;
 819         }
 820       else
 821         {
 822           if ( (timers->reg[timer_nr].mode & clock_mask) == clk_cascaded )
 823             {
 824               ASSERT(timers->timer[timer_nr].event == NULL);
 825             }
 826         }
 827
 828     }
 829
 830 }
 831
 832 static void
 833 write_tm6md (struct hw *me,
 834              struct mn103tim *timers,
 835              unsigned_word address,
 836              const void *source,
 837              unsigned nr_bytes)
 838 {
 839   uint8_t mode_val0 = 0x00, mode_val1 = 0x00;
 840   uint32_t div_ratio;
 841   long timer_nr = 6;
 842
 843   unsigned_word offset = address - timers->block[0].base;
 844
 845   if ((offset != 0x84 && nr_bytes > 1) || nr_bytes > 2 )
 846     {
 847       hw_abort (me, "Bad write size of %d bytes to TM6MD", nr_bytes);
 848     }
 849
 850   if ( offset == 0x84 )  /* address of TM6MD */
 851     {
 852       /*  Fill in first byte of mode */
 853       mode_val0 = *(uint8_t *)source;
 854       timers->tm6md0 = mode_val0;
 855
 856       if ( ( mode_val0 & 0x26 ) != 0 )
 857         {
 858           hw_abort(me, "Cannot write to bits 5, 3, and 2 of TM6MD");
 859         }
 860     }
 861
 862   if ( offset == 0x85 || nr_bytes == 2 )
 863     {
 864       /*  Fill in second byte of mode */
 865       if ( nr_bytes == 2 )
 866         {
 867           mode_val1 = *(uint8_t *)source+1;
 868         }
 869       else
 870         {
 871           mode_val1 = *(uint8_t *)source;
 872         }
 873
 874       timers->tm6md1 = mode_val1;
 875
 876       if ( ( mode_val1 & count_and_load_mask ) == count_and_load_mask )
 877         {
 878           hw_abort(me, "Cannot load base reg and start counting simultaneously.");
 879         }
 880       if ( ( mode_val1 & bits0to2_mask ) != 0 )
 881         {
 882           hw_abort(me, "Cannot write to bits 8 to 10 of TM6MD");
 883         }
 884     }
 885
 886   if ( mode_val1 & count_mask )
 887     {
 888       /* - de-schedule any previous event. */
 889       /* - add new event to queue to start counting. */
 890       /* - assert that counter == base reg? */
 891
 892       div_ratio = timers->tm6ca;  /* binary counter for timer 6 */
 893       timers->timer[timer_nr].div_ratio = div_ratio;
 894       if ( NULL != timers->timer[timer_nr].event )
 895         {
 896           hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
 897           timers->timer[timer_nr].event = NULL;
 898         }
 899
 900       if ( div_ratio > 0 )
 901         {
 902           /* Set start time. */
 903           timers->timer[timer_nr].start = hw_event_queue_time(me);
 904           timers->timer[timer_nr].event
 905             = hw_event_queue_schedule(me, div_ratio,
 906                                       do_counter6_event,
 907                                       (void *)(uintptr_t)timer_nr);
 908         }
 909     }
 910   else
 911     {
 912       /* Turn off counting */
 913       if ( NULL != timers->timer[timer_nr].event )
 914         {
 915           hw_event_queue_deschedule (me, timers->timer[timer_nr].event);
 916           timers->timer[timer_nr].event = NULL;
 917         }
 918     }
 919 }
 920
 921
 922
 923 static void
 924 write_special_timer6_reg (struct hw *me,
 925                           struct mn103tim *timers,
 926                           int timer_nr,
 927                           const void *source,
 928                           unsigned  nr_bytes)
 929 {
 930   switch (nr_bytes) {
 931   case 1:
 932     {
 933       switch ( timer_nr ) {
 934       case TM6MDA:
 935         timers->tm6mda = *(uint8_t *)source;
 936         break;
 937
 938       case TM6MDB:
 939         timers->tm6mdb = *(uint8_t *)source;
 940         break;
 941
 942       case TM6CA:
 943         timers->tm6ca = *(uint8_t *)source;
 944         break;
 945
 946       case TM6CB:
 947         timers->tm6cb = *(uint8_t *)source;
 948         break;
 949
 950       default:
 951         break;
 952       }
 953       break;
 954     }
 955
 956   case 2:
 957     if ( timer_nr == TM6CA )
 958       {
 959         timers->tm6ca = *(uint16_t *)source;
 960       }
 961     else if ( timer_nr == TM6CB )
 962       {
 963         timers->tm6cb = *(uint16_t *)source;
 964       }
 965     else
 966       {
 967         hw_abort(me, "bad read size for timer 6 mode A/B register");
 968       }
 969     break;
 970
 971   default:
 972     hw_abort(me, "bad read size for timer 6 register");
 973   }
 974
 975 }
 976
 977
 978 static unsigned
 979 mn103tim_io_write_buffer (struct hw *me,
 980                           const void *source,
 981                           int space,
 982                           unsigned_word base,
 983                           unsigned nr_bytes)
 984 {
 985   struct mn103tim *timers = hw_data (me);
 986   enum timer_register_types timer_reg;
 987
 988   HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,
 989              (int) nr_bytes, *(uint32_t *)source));
 990
 991   timer_reg = decode_addr (me, timers, base);
 992
 993   /* It can be either a mode register, a base register, a binary counter, */
 994   /* or a special timer 6 register.  Check in that order. */
 995   if ( timer_reg <= LAST_MODE_REG )
 996     {
 997       if ( timer_reg == 6 )
 998         {
 999           write_tm6md(me, timers, base, source, nr_bytes);
1000         }
1001       else
1002         {
1003           write_mode_reg(me, timers, timer_reg-FIRST_MODE_REG,
1004                          source, nr_bytes);
1005         }
1006     }
1007   else if ( timer_reg <= LAST_BASE_REG )
1008     {
1009       write_base_reg(me, timers, timer_reg-FIRST_BASE_REG, source, nr_bytes);
1010     }
1011   else if ( timer_reg <= LAST_COUNTER )
1012     {
1013       hw_abort(me, "cannot write to counter");
1014     }
1015   else if ( timer_reg <= LAST_TIMER_REG )
1016     {
1017       write_special_timer6_reg(me, timers, timer_reg, source, nr_bytes);
1018     }
1019   else
1020     {
1021       hw_abort(me, "invalid reg type");
1022     }
1023
1024   return nr_bytes;
1025 }
1026
1027
1028 const struct hw_descriptor dv_mn103tim_descriptor[] = {
1029   { "mn103tim", mn103tim_finish, },
1030   { NULL },
1031 };