sim/mn10300/mn10300-sim.h

   1 #ifndef MN10300_SIM_H
   2 #define MN10300_SIM_H
   3
   4 /* For compatibility, until all functions converted to passing
   5    SIM_DESC as an argument */
   6 extern SIM_DESC simulator;
   7
   8 typedef struct
   9 {
  10   uint32_t low, high;
  11 } dword;
  12 typedef uint32_t reg_t;
  13
  14 struct simops
  15 {
  16   long opcode;
  17   long mask;
  18   void (*func)();
  19   int length;
  20   int format;
  21   int numops;
  22   int operands[16];
  23 };
  24
  25 /* The current state of the processor; registers, memory, etc.  */
  26
  27 struct _state
  28 {
  29   reg_t regs[32];               /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
  30                                    lir, lar, mdrq, plus some room for processor
  31                                    specific regs.  */
  32   union
  33   {
  34     reg_t fs[32]; /* FS0-31 */
  35     dword fd[16]; /* FD0,2,...,30 */
  36   } fpregs;
  37
  38   /* All internal state modified by signal_exception() that may need to be
  39      rolled back for passing moment-of-exception image back to gdb. */
  40   reg_t exc_trigger_regs[32];
  41   reg_t exc_suspend_regs[32];
  42   int exc_suspended;
  43
  44 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
  45 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
  46 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
  47 };
  48
  49 extern struct _state State;
  50
  51 #define PC      (State.regs[REG_PC])
  52 #define SP      (State.regs[REG_SP])
  53
  54 #define PSW (State.regs[11])
  55 #define PSW_Z 0x1
  56 #define PSW_N 0x2
  57 #define PSW_C 0x4
  58 #define PSW_V 0x8
  59 #define PSW_IE LSBIT (11)
  60 #define PSW_LM LSMASK (10, 8)
  61
  62 #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
  63 #define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
  64
  65 #define REG_D0 0
  66 #define REG_A0 4
  67 #define REG_SP 8
  68 #define REG_PC 9
  69 #define REG_MDR 10
  70 #define REG_PSW 11
  71 #define REG_LIR 12
  72 #define REG_LAR 13
  73 #define REG_MDRQ 14
  74 #define REG_E0 15
  75 #define REG_SSP 23
  76 #define REG_MSP 24
  77 #define REG_USP 25
  78 #define REG_MCRH 26
  79 #define REG_MCRL 27
  80 #define REG_MCVF 28
  81
  82 #define REG_FPCR 29
  83
  84 #define FPCR (State.regs[REG_FPCR])
  85
  86 #define FCC_MASK LSMASK (21, 18)
  87 #define RM_MASK  LSMASK (17, 16) /* Must always be zero.  */
  88 #define EC_MASK  LSMASK (14, 10)
  89 #define EE_MASK  LSMASK ( 9,  5)
  90 #define EF_MASK  LSMASK ( 4,  0)
  91 #define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
  92
  93 #define FCC_L LSBIT (21)
  94 #define FCC_G LSBIT (20)
  95 #define FCC_E LSBIT (19)
  96 #define FCC_U LSBIT (18)
  97
  98 #define EC_V LSBIT (14)
  99 #define EC_Z LSBIT (13)
 100 #define EC_O LSBIT (12)
 101 #define EC_U LSBIT (11)
 102 #define EC_I LSBIT (10)
 103
 104 #define EE_V LSBIT (9)
 105 #define EE_Z LSBIT (8)
 106 #define EE_O LSBIT (7)
 107 #define EE_U LSBIT (6)
 108 #define EE_I LSBIT (5)
 109
 110 #define EF_V LSBIT (4)
 111 #define EF_Z LSBIT (3)
 112 #define EF_O LSBIT (2)
 113 #define EF_U LSBIT (1)
 114 #define EF_I LSBIT (0)
 115
 116 #define PSW_FE LSBIT(20)
 117 #define FPU_DISABLED !(PSW & PSW_FE)
 118
 119 #define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
 120 #define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
 121 #define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
 122
 123 #define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
 124 #define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
 125 #define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
 126 #define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
 127
 128 #define FETCH32(a,b,c,d) \
 129  ((a)+((b)<<8)+((c)<<16)+((d)<<24))
 130
 131 #define FETCH24(a,b,c) \
 132  ((a)+((b)<<8)+((c)<<16))
 133
 134 #define FETCH16(a,b) ((a)+((b)<<8))
 135
 136 #define load_byte(ADDR) \
 137 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 138
 139 #define load_half(ADDR) \
 140 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 141
 142 #define load_word(ADDR) \
 143 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 144
 145 #define load_dword(ADDR) \
 146 u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
 147                                    PC, read_map, (ADDR)))
 148
 149 static INLINE2 dword
 150 u642dw (uint64_t dw)
 151 {
 152   dword r;
 153
 154   r.low = (uint32_t)dw;
 155   r.high = (uint32_t)(dw >> 32);
 156   return r;
 157 }
 158
 159 #define store_byte(ADDR, DATA) \
 160 sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
 161                             PC, write_map, (ADDR), (DATA))
 162
 163
 164 #define store_half(ADDR, DATA) \
 165 sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
 166                             PC, write_map, (ADDR), (DATA))
 167
 168
 169 #define store_word(ADDR, DATA) \
 170 sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
 171                             PC, write_map, (ADDR), (DATA))
 172 #define store_dword(ADDR, DATA) \
 173 sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
 174                             PC, write_map, (ADDR), dw2u64 (DATA))
 175
 176 static INLINE2 uint64_t
 177 dw2u64 (dword data)
 178 {
 179   return data.low | (((uint64_t)data.high) << 32);
 180 }
 181
 182 /* Bring data in from the cold */
 183
 184 #define IMEM8(EA) \
 185 (sim_core_read_aligned_1(STATE_CPU (SD, 0), EA, exec_map, (EA)))
 186
 187 #define IMEM8_IMMED(EA, N) \
 188 (sim_core_read_aligned_1(STATE_CPU (SD, 0), EA, exec_map, (EA) + (N)))
 189
 190 /* Function declarations.  */
 191
 192 INLINE_SIM_MAIN (void) genericAdd (uint32_t source, uint32_t destReg);
 193 INLINE_SIM_MAIN (void) genericSub (uint32_t source, uint32_t destReg);
 194 INLINE_SIM_MAIN (void) genericCmp (uint32_t leftOpnd, uint32_t rightOpnd);
 195 INLINE_SIM_MAIN (void) genericOr (uint32_t source, uint32_t destReg);
 196 INLINE_SIM_MAIN (void) genericXor (uint32_t source, uint32_t destReg);
 197 INLINE_SIM_MAIN (void) genericBtst (uint32_t leftOpnd, uint32_t rightOpnd);
 198 INLINE_SIM_MAIN (void) do_syscall (SIM_DESC sd);
 199 void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig)
 200   ATTRIBUTE_NORETURN;
 201
 202 void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 203 void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 204 void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 205
 206 void fpu_disabled_exception     (SIM_DESC, sim_cpu *, address_word);
 207 void fpu_unimp_exception        (SIM_DESC, sim_cpu *, address_word);
 208 void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
 209
 210 extern const struct fp_prec_t
 211 {
 212   void (* reg2val) (const void *, sim_fpu *);
 213   int (*  round)   (sim_fpu *);
 214   void (* val2reg) (const sim_fpu *, void *);
 215 } fp_single_prec, fp_double_prec;
 216
 217 #define FP_SINGLE (&fp_single_prec)
 218 #define FP_DOUBLE (&fp_double_prec)
 219
 220 void fpu_rsqrt  (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
 221 void fpu_sqrt   (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
 222 void fpu_cmp    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
 223 void fpu_add    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 224 void fpu_sub    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 225 void fpu_mul    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 226 void fpu_div    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 227 void fpu_fmadd  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
 228 void fpu_fmsub  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
 229 void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
 230 void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
 231
 232 #endif