sim/pru/pru.h

   1 /* Copyright 2016-2024 Free Software Foundation, Inc.
   2    Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
   3
   4    This file is part of the PRU simulator.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef PRU_H
  20 #define PRU_H
  21
  22 #include <stdint.h>
  23
  24 #include "opcode/pru.h"
  25
  26 /* Needed for handling the dual PRU address space.  */
  27 #define IMEM_ADDR_MASK  ((1u << 23) - 1)
  28
  29 #define IMEM_ADDR_DEFAULT 0x20000000
  30
  31 /* Define memory sizes to allocate for simulated target.  Sizes are
  32    artificially large to accommodate execution of compiler test suite.
  33    Please synchronize with the linker script for prusim target.  */
  34 #define DMEM_DEFAULT_SIZE (64 * 1024 * 1024)
  35
  36 /* 16-bit word addressable space.  */
  37 #define IMEM_DEFAULT_SIZE (64 * 4 * 1024)
  38
  39 /* For AM335x SoCs.  */
  40 #define XFRID_SCRATCH_BANK_0      10
  41 #define XFRID_SCRATCH_BANK_1      11
  42 #define XFRID_SCRATCH_BANK_2      12
  43 #define XFRID_SCRATCH_BANK_PEER   14
  44 #define XFRID_MAX                 255
  45
  46 #define CPU     (*pru_cpu)
  47
  48 #define PC              (CPU.pc)
  49 #define PC_byteaddr     ((PC << 2) | PC_ADDR_SPACE_MARKER)
  50
  51 /* Various opcode fields.  */
  52 #define RS1 extract_regval (CPU.regs[GET_INSN_FIELD (RS1, inst)], \
  53                             GET_INSN_FIELD (RS1SEL, inst))
  54 #define RS2 extract_regval (CPU.regs[GET_INSN_FIELD (RS2, inst)], \
  55                             GET_INSN_FIELD (RS2SEL, inst))
  56
  57 #define RS2_w0 extract_regval (CPU.regs[GET_INSN_FIELD (RS2, inst)], \
  58                                RSEL_15_0)
  59
  60 #define XBBO_BASEREG (CPU.regs[GET_INSN_FIELD (RS1, inst)])
  61
  62 #define RS1SEL GET_INSN_FIELD (RS1SEL, inst)
  63 #define RS1_WIDTH regsel_width (RS1SEL)
  64 #define RDSEL GET_INSN_FIELD (RDSEL, inst)
  65 #define RD_WIDTH regsel_width (RDSEL)
  66 #define RD_REGN GET_INSN_FIELD (RD, inst)
  67 #define IO GET_INSN_FIELD (IO, inst)
  68 #define IMM8 GET_INSN_FIELD (IMM8, inst)
  69 #define IMM16 GET_INSN_FIELD (IMM16, inst)
  70 #define WAKEONSTATUS GET_INSN_FIELD (WAKEONSTATUS, inst)
  71 #define CB GET_INSN_FIELD (CB, inst)
  72 #define RDB GET_INSN_FIELD (RDB, inst)
  73 #define XFR_WBA GET_INSN_FIELD (XFR_WBA, inst)
  74 #define LOOP_JMPOFFS GET_INSN_FIELD (LOOP_JMPOFFS, inst)
  75 #define BROFF ((uint32_t) GET_BROFF_SIGNED (inst))
  76
  77 #define _BURSTLEN_CALCULATE(BITFIELD)                                       \
  78   ((BITFIELD) >= LSSBBO_BYTECOUNT_R0_BITS7_0 ?                              \
  79   (CPU.regs[0] >> ((BITFIELD) - LSSBBO_BYTECOUNT_R0_BITS7_0) * 8) & 0xff    \
  80   : (BITFIELD) + 1)
  81
  82 #define BURSTLEN _BURSTLEN_CALCULATE (GET_BURSTLEN (inst))
  83 #define XFR_LENGTH _BURSTLEN_CALCULATE (GET_INSN_FIELD (XFR_LENGTH, inst))
  84
  85 #define DO_XIN(wba,regn,rdb,l)    \
  86   pru_sim_xin (sd, cpu, (wba), (regn), (rdb), (l))
  87 #define DO_XOUT(wba,regn,rdb,l)   \
  88   pru_sim_xout (sd, cpu, (wba), (regn), (rdb), (l))
  89 #define DO_XCHG(wba,regn,rdb,l)   \
  90   pru_sim_xchg (sd, cpu, (wba), (regn), (rdb), (l))
  91
  92 #define RAISE_SIGILL(sd)  sim_engine_halt ((sd), NULL, NULL, PC_byteaddr, \
  93                                            sim_stopped, SIM_SIGILL)
  94 #define RAISE_SIGINT(sd)  sim_engine_halt ((sd), NULL, NULL, PC_byteaddr, \
  95                                            sim_stopped, SIM_SIGINT)
  96
  97 #define MAC_R25_MAC_MODE_MASK     (1u << 0)
  98 #define MAC_R25_ACC_CARRY_MASK    (1u << 1)
  99
 100 #define CARRY   CPU.carry
 101 #define CTABLE  CPU.ctable
 102
 103 #define PC_ADDR_SPACE_MARKER    CPU.pc_addr_space_marker
 104
 105 #define LOOPTOP           CPU.loop.looptop
 106 #define LOOPEND           CPU.loop.loopend
 107 #define LOOP_IN_PROGRESS  CPU.loop.loop_in_progress
 108 #define LOOPCNT           CPU.loop.loop_counter
 109
 110 /* 32 GP registers plus PC.  */
 111 #define NUM_REGS        33
 112
 113 /* The machine state.
 114    This state is maintained in host byte order.  The
 115    fetch/store register functions must translate between host
 116    byte order and the target processor byte order.
 117    Keeping this data in target byte order simplifies the register
 118    read/write functions.  Keeping this data in host order improves
 119    the performance of the simulator.  Simulation speed is deemed more
 120    important.  */
 121
 122 /* For clarity, please keep the same relative order in this enum as in the
 123    corresponding group of GP registers.
 124
 125    In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of
 126    the GP registers.  MAC registers are implicitly addressed when executing
 127    the XIN/XOUT instructions to access them.  Transfer to/from a MAC register
 128    can happen only from/to its corresponding GP peer register.  */
 129
 130 enum pru_macreg_id {
 131     /* MAC register       CPU GP register     Description.  */
 132     PRU_MACREG_MODE,      /* r25 */           /* Mode (MUL/MAC).  */
 133     PRU_MACREG_PROD_L,    /* r26 */           /* Lower 32 bits of product.  */
 134     PRU_MACREG_PROD_H,    /* r27 */           /* Higher 32 bits of product.  */
 135     PRU_MACREG_OP_0,      /* r28 */           /* First operand.  */
 136     PRU_MACREG_OP_1,      /* r29 */           /* Second operand.  */
 137     PRU_MACREG_ACC_L,     /* N/A */           /* Accumulator (not exposed)  */
 138     PRU_MACREG_ACC_H,     /* N/A */           /* Higher 32 bits of MAC
 139                                                  accumulator.  */
 140     PRU_MAC_NREGS
 141 };
 142
 143 struct pru_regset
 144 {
 145   uint32_t        regs[32];             /* Primary registers.  */
 146   uint16_t        pc;                   /* IMEM _word_ address.  */
 147   uint32_t        pc_addr_space_marker; /* IMEM virtual linker offset.  This
 148                                            is the artificial offset that
 149                                            we invent in order to "separate"
 150                                            the DMEM and IMEM memory spaces.  */
 151   unsigned int    carry : 1;
 152   uint32_t        ctable[32];           /* Constant offsets table for xBCO.  */
 153   uint32_t        macregs[PRU_MAC_NREGS];
 154   uint32_t        scratchpads[XFRID_MAX + 1][32];
 155   struct {
 156     uint16_t looptop;                   /* LOOP top (PC of loop instr).  */
 157     uint16_t loopend;                   /* LOOP end (PC of loop end label).  */
 158     int loop_in_progress;               /* Whether to check for PC==loopend.  */
 159     uint32_t loop_counter;              /* LOOP counter.  */
 160   } loop;
 161   int             cycles;
 162   int             insts;
 163 };
 164
 165 #define PRU_SIM_CPU(cpu) ((struct pru_regset *) CPU_ARCH_DATA (cpu))
 166
 167 #endif /* PRU_H */