sim/testsuite/sh/bclr.s

   1 # sh testcase for bclr
   2 # mach:  all
   3 # as(sh):       -defsym sim_cpu=0
   4 # as(shdsp):    -defsym sim_cpu=1 -dsp
   5
   6         .include "testutils.inc"
   7
   8         .align 2
   9 _x:     .long   0xffffffff
  10 _y:     .long   0x55555555
  11
  12         start
  13
  14 bclr_b_imm_disp12_reg:
  15         set_grs_a5a5
  16         mov.l   x, r1
  17
  18         bclr.b  #0, @(3, r1)
  19         assertmem _x, 0xfffffffe
  20         bclr.b  #1, @(3, r1)
  21         assertmem _x, 0xfffffffc
  22         bclr.b  #2, @(3, r1)
  23         assertmem _x, 0xfffffff8
  24         bclr.b  #3, @(3, r1)
  25         assertmem _x, 0xfffffff0
  26
  27         bclr.b  #4, @(3, r1)
  28         assertmem _x, 0xffffffe0
  29         bclr.b  #5, @(3, r1)
  30         assertmem _x, 0xffffffc0
  31         bclr.b  #6, @(3, r1)
  32         assertmem _x, 0xffffff80
  33         bclr.b  #7, @(3, r1)
  34         assertmem _x, 0xffffff00
  35
  36         bclr.b  #0, @(2, r1)
  37         assertmem _x, 0xfffffe00
  38         bclr.b  #1, @(2, r1)
  39         assertmem _x, 0xfffffc00
  40         bclr.b  #2, @(2, r1)
  41         assertmem _x, 0xfffff800
  42         bclr.b  #3, @(2, r1)
  43         assertmem _x, 0xfffff000
  44
  45         bra     .L2
  46         nop
  47
  48         .align 2
  49 x:      .long   _x
  50 y:      .long   _y
  51
  52 .L2:
  53         bclr.b  #4, @(2, r1)
  54         assertmem _x, 0xffffe000
  55         bclr.b  #5, @(2, r1)
  56         assertmem _x, 0xffffc000
  57         bclr.b  #6, @(2, r1)
  58         assertmem _x, 0xffff8000
  59         bclr.b  #7, @(2, r1)
  60         assertmem _x, 0xffff0000
  61
  62         bclr.b  #0, @(1, r1)
  63         assertmem _x, 0xfffe0000
  64         bclr.b  #1, @(1, r1)
  65         assertmem _x, 0xfffc0000
  66         bclr.b  #2, @(1, r1)
  67         assertmem _x, 0xfff80000
  68         bclr.b  #3, @(1, r1)
  69         assertmem _x, 0xfff00000
  70
  71         bclr.b  #4, @(1, r1)
  72         assertmem _x, 0xffe00000
  73         bclr.b  #5, @(1, r1)
  74         assertmem _x, 0xffc00000
  75         bclr.b  #6, @(1, r1)
  76         assertmem _x, 0xff800000
  77         bclr.b  #7, @(1, r1)
  78         assertmem _x, 0xff000000
  79
  80         bclr.b  #0, @(0, r1)
  81         assertmem _x, 0xfe000000
  82         bclr.b  #1, @(0, r1)
  83         assertmem _x, 0xfc000000
  84         bclr.b  #2, @(0, r1)
  85         assertmem _x, 0xf8000000
  86         bclr.b  #3, @(0, r1)
  87         assertmem _x, 0xf0000000
  88
  89         bclr.b  #4, @(0, r1)
  90         assertmem _x, 0xe0000000
  91         bclr.b  #5, @(0, r1)
  92         assertmem _x, 0xc0000000
  93         bclr.b  #6, @(0, r1)
  94         assertmem _x, 0x80000000
  95         bclr.b  #7, @(0, r1)
  96         assertmem _x, 0x00000000
  97
  98         assertreg _x, r1
  99
 100 bclr_imm_reg:
 101         set_greg 0xff, r1
 102         bclr    #0, r1
 103         assertreg 0xfe, r1
 104         bclr    #1, r1
 105         assertreg 0xfc, r1
 106         bclr    #2, r1
 107         assertreg 0xf8, r1
 108         bclr    #3, r1
 109         assertreg 0xf0, r1
 110
 111         bclr    #4, r1
 112         assertreg 0xe0, r1
 113         bclr    #5, r1
 114         assertreg 0xc0, r1
 115         bclr    #6, r1
 116         assertreg 0x80, r1
 117         bclr    #7, r1
 118         assertreg 0x00, r1
 119
 120         test_gr_a5a5 r0
 121         test_gr_a5a5 r2
 122         test_gr_a5a5 r3
 123         test_gr_a5a5 r4
 124         test_gr_a5a5 r5
 125         test_gr_a5a5 r6
 126         test_gr_a5a5 r7
 127         test_gr_a5a5 r8
 128         test_gr_a5a5 r9
 129         test_gr_a5a5 r10
 130         test_gr_a5a5 r11
 131         test_gr_a5a5 r12
 132         test_gr_a5a5 r13
 133         test_gr_a5a5 r14
 134
 135         pass
 136
 137         exit 0
 138
 139