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HEAD
arm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M Mainline
[binutils-gdb.git]
/
sim
/
testsuite
/
sh
/
bldnot.s
blob
eda87def9c23013dff5c5b01670480deb4b9e5f9
1
# sh testcase for bldnot
2
# mach: all
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# as(sh): -defsym sim_cpu=0
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# as(shdsp): -defsym sim_cpu=1 -dsp
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6
.include
"testutils.inc"
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8
.align 2
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_x
:
.long 0xa5a5a5a5
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_y
:
.long 0x55555555
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start
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bldnot_b_imm_disp12_reg
:
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set_grs_a5a5
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mov.
l
x
,
r1
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bldnot.
b
#0, @(0, r1)
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bt8k mfail
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bldnot.
b
#1, @(0, r1)
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bf8k mfail
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bldnot.
b
#2, @(0, r1)
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bt8k mfail
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bldnot.
b
#3, @(0, r1)
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bf8k mfail
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bldnot.
b
#4, @(0, r1)
28
bf8k mfail
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bldnot.
b
#5, @(0, r1)
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bt8k mfail
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bldnot.
b
#6, @(0, r1)
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bf8k mfail
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bldnot.
b
#7, @(0, r1)
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bt8k mfail
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bldnot.
b
#0, @(1, r1)
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bt8k mfail
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bldnot.
b
#1, @(1, r1)
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bf8k mfail
40
bldnot.
b
#2, @(1, r1)
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bt8k mfail
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bldnot.
b
#3, @(1, r1)
43
bf8k mfail
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bldnot.
b
#4, @(1, r1)
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bf8k mfail
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bldnot.
b
#5, @(1, r1)
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bt8k mfail
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bldnot.
b
#6, @(1, r1)
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bf8k mfail
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bldnot.
b
#7, @(1, r1)
52
bt8k mfail
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bldnot.
b
#0, @(2, r1)
55
bt8k mfail
56
bldnot.
b
#1, @(2, r1)
57
bf8k mfail
58
bldnot.
b
#2, @(2, r1)
59
bt8k mfail
60
bldnot.
b
#3, @(2, r1)
61
bf8k mfail
62
63
bldnot.
b
#4, @(2, r1)
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bf8k mfail
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bldnot.
b
#5, @(2, r1)
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bt8k mfail
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bldnot.
b
#6, @(2, r1)
68
bf8k mfail
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bldnot.
b
#7, @(2, r1)
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bt8k mfail
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bldnot.
b
#0, @(3, r1)
73
bt8k mfail
74
bldnot.
b
#1, @(3, r1)
75
bf8k mfail
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bldnot.
b
#2, @(3, r1)
77
bt8k mfail
78
bldnot.
b
#3, @(3, r1)
79
bf8k mfail
80
81
bldnot.
b
#4, @(3, r1)
82
bf8k mfail
83
bldnot.
b
#5, @(3, r1)
84
bt8k mfail
85
bldnot.
b
#6, @(3, r1)
86
bf8k mfail
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bldnot.
b
#7, @(3, r1)
88
bt8k mfail
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assertreg _x
,
r1
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set_greg
0xa5a5a5a5
,
r1
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test_grs_a5a5
94
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pass
96
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exit
0
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99
.align 2
100
x
:
.long _x
101
y
:
.long _y
102