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HEAD
arm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M Mainline
[binutils-gdb.git]
/
sim
/
testsuite
/
sh
/
fsqrt.s
blob
cb61bcf40856eb30b14346a9b5ce4f1f424198c8
1
# sh testcase for fsqrt
2
# mach: sh
3
# as(sh): -defsym sim_cpu=0
4
5
.include
"testutils.inc"
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start
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fsqrt_single
:
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set_grs_a5a5
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set_fprs_a5a5
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# sqrt(0.0) = 0.0.
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fldi0 fr0
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fsqrt
fr0
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fldi0 fr1
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fcmp
/
eq fr0
,
fr1
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bt
.L0
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fail
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.L0:
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# sqrt(1.0) = 1.0.
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fldi1 fr0
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fsqrt
fr0
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fldi1 fr1
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fcmp
/
eq fr0
,
fr1
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bt
.L1
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fail
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.L1:
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# sqrt(4.0) = 2.0
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fldi1 fr0
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# Double it.
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fadd
fr0
,
fr0
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# Double it again.
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fadd
fr0
,
fr0
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fsqrt
fr0
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fldi1 fr1
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# Double it.
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fadd
fr1
,
fr1
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fcmp
/
eq fr0
,
fr1
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bt
.L2
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fail
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.L2:
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test_grs_a5a5
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assert_fpreg_i
2
,
fr0
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assert_fpreg_i
2
,
fr1
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test_fpr_a5a5 fr2
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test_fpr_a5a5 fr3
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test_fpr_a5a5 fr4
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test_fpr_a5a5 fr5
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test_fpr_a5a5 fr6
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test_fpr_a5a5 fr7
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test_fpr_a5a5 fr8
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test_fpr_a5a5 fr9
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test_fpr_a5a5 fr10
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test_fpr_a5a5 fr11
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test_fpr_a5a5 fr12
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test_fpr_a5a5 fr13
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test_fpr_a5a5 fr14
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test_fpr_a5a5 fr15
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fsqrt_double
:
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double_prec
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set_grs_a5a5
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set_fprs_a5a5
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# sqrt(0.0) = 0.0.
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fldi0 fr0
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_s2d fr0
,
dr0
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fsqrt
dr0
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fldi0 fr2
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_s2d fr2
,
dr2
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fcmp
/
eq dr0
,
dr2
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bt
.L10
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fail
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.L10:
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# sqrt(1.0) = 1.0.
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fldi1 fr0
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_s2d fr0
,
dr0
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fsqrt
dr0
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fldi1 fr2
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_s2d fr2
,
dr2
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fcmp
/
eq dr0
,
dr2
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bt
.L11
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fail
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.L11:
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# sqrt(4.0) = 2.0.
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fldi1 fr0
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# Double it.
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single_prec
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fadd
fr0
,
fr0
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# Double it again.
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fadd
fr0
,
fr0
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double_prec
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_s2d fr0
,
dr0
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fsqrt
dr0
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fldi1 fr2
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# Double it.
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single_prec
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fadd
fr2
,
fr2
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double_prec
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_s2d fr2
,
dr2
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fcmp
/
eq dr0
,
dr2
100
bt
.L12
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fail
102
.L12:
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test_grs_a5a5
104
assert_dpreg_i
2
,
dr0
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assert_dpreg_i
2
,
dr2
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test_fpr_a5a5 fr4
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test_fpr_a5a5 fr5
108
test_fpr_a5a5 fr6
109
test_fpr_a5a5 fr7
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test_fpr_a5a5 fr8
111
test_fpr_a5a5 fr9
112
test_fpr_a5a5 fr10
113
test_fpr_a5a5 fr11
114
test_fpr_a5a5 fr12
115
test_fpr_a5a5 fr13
116
test_fpr_a5a5 fr14
117
test_fpr_a5a5 fr15
118
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pass
120
exit
0