sim/testsuite/sh/mov.s

   1 # sh testcase for all mov.[bwl] instructions
   2 # mach: sh
   3 # as(sh):       -defsym sim_cpu=0
   4
   5         .include "testutils.inc"
   6
   7         .align 2
   8 _lsrc:  .long   0x55555555
   9 _wsrc:  .long   0x55550000
  10 _bsrc:  .long   0x55000000
  11
  12         .align 2
  13 _ldst:  .long   0
  14 _wdst:  .long   0
  15 _bdst:  .long   0
  16
  17
  18         start
  19
  20 movb_disp12_reg:        # Test 8-bit @(disp12,gr) -> gr
  21         set_grs_a5a5
  22         mov.l   bsrc, r1
  23         add     #-111, r1
  24         add     #-111, r1
  25         add     #-111, r1
  26         add     #-111, r1
  27         mov.b   @(444,r1), r2
  28
  29         assertreg _bsrc-444, r1
  30         assertreg 0x55, r2
  31
  32 movb_reg_disp12:        # Test 8-bit gr -> @(disp12,gr)
  33         set_grs_a5a5
  34         mov.l   bdst, r1
  35         add     #-111, r1
  36         add     #-111, r1
  37         add     #-111, r1
  38         add     #-111, r1
  39         mov.b   r2, @(444,r1)
  40
  41         assertreg _bdst-444, r1
  42         assertmem _bdst, 0xa5000000
  43
  44 movw_disp12_reg:        # Test 16-bit @(disp12,gr) -> gr
  45         set_grs_a5a5
  46         mov.l   wsrc, r1
  47         add     #-111, r1
  48         add     #-111, r1
  49         add     #-111, r1
  50         add     #-111, r1
  51         mov.w   @(444,r1), r2
  52
  53         assertreg _wsrc-444, r1
  54         assertreg 0x5555, r2
  55
  56 movw_reg_disp12:        # Test 16-bit gr -> @(disp12,gr)
  57         set_grs_a5a5
  58         mov.l   wdst, r1
  59         add     #-111, r1
  60         add     #-111, r1
  61         add     #-111, r1
  62         add     #-111, r1
  63         mov.w   r2, @(444,r1)
  64
  65         assertreg _wdst-444, r1
  66         assertmem _wdst, 0xa5a50000
  67
  68 movl_disp12_reg:        # Test 32-bit @(disp12,gr) -> gr
  69         set_grs_a5a5
  70         mov.l   lsrc, r1
  71         add     #-111, r1
  72         add     #-111, r1
  73         add     #-111, r1
  74         add     #-111, r1
  75         mov.l   @(444,r1), r2
  76
  77         assertreg _lsrc-444, r1
  78         assertreg 0x55555555, r2
  79
  80 movl_reg_disp12:        # Test 32-bit gr -> @(disp12,gr)
  81         set_grs_a5a5
  82         mov.l   ldst, r1
  83         add     #-111, r1
  84         add     #-111, r1
  85         add     #-111, r1
  86         add     #-111, r1
  87         mov.l   r2, @(444,r1)
  88
  89         assertreg _ldst-444, r1
  90         assertmem _ldst, 0xa5a5a5a5
  91
  92         test_gr_a5a5 r0
  93         test_gr_a5a5 r2
  94         test_gr_a5a5 r3
  95         test_gr_a5a5 r4
  96         test_gr_a5a5 r5
  97         test_gr_a5a5 r6
  98         test_gr_a5a5 r7
  99         test_gr_a5a5 r8
 100         test_gr_a5a5 r9
 101         test_gr_a5a5 r10
 102         test_gr_a5a5 r11
 103         test_gr_a5a5 r12
 104         test_gr_a5a5 r13
 105         test_gr_a5a5 r14
 106
 107         pass
 108
 109         exit 0
 110
 111 lsrc:   .long _lsrc
 112 wsrc:   .long _wsrc
 113 bsrc:   .long _bsrc
 114
 115 ldst:   .long _ldst
 116 wdst:   .long _wdst
 117 bdst:   .long _bdst
 118