opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2018 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24
  25 #include "disassemble.h"
  26 #include "opcode/arm.h"
  27 #include "opintl.h"
  28 #include "safe-ctype.h"
  29 #include "libiberty.h"
  30 #include "floatformat.h"
  31
  32 /* FIXME: This shouldn't be done here.  */
  33 #include "coff/internal.h"
  34 #include "libcoff.h"
  35 #include "elf-bfd.h"
  36 #include "elf/internal.h"
  37 #include "elf/arm.h"
  38 #include "mach-o.h"
  39
  40 /* FIXME: Belongs in global header.  */
  41 #ifndef strneq
  42 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  43 #endif
  44
  45 /* Cached mapping symbol state.  */
  46 enum map_type
  47 {
  48   MAP_ARM,
  49   MAP_THUMB,
  50   MAP_DATA
  51 };
  52
  53 struct arm_private_data
  54 {
  55   /* The features to use when disassembling optional instructions.  */
  56   arm_feature_set features;
  57
  58   /* Whether any mapping symbols are present in the provided symbol
  59      table.  -1 if we do not know yet, otherwise 0 or 1.  */
  60   int has_mapping_symbols;
  61
  62   /* Track the last type (although this doesn't seem to be useful) */
  63   enum map_type last_type;
  64
  65   /* Tracking symbol table information */
  66   int last_mapping_sym;
  67   bfd_vma last_mapping_addr;
  68 };
  69
  70 struct opcode32
  71 {
  72   arm_feature_set arch;         /* Architecture defining this insn.  */
  73   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
  74   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  75   const char *  assembler;      /* How to disassemble this insn.  */
  76 };
  77
  78 struct opcode16
  79 {
  80   arm_feature_set arch;         /* Architecture defining this insn.  */
  81   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  82   const char *assembler;        /* How to disassemble this insn.  */
  83 };
  84
  85 /* print_insn_coprocessor recognizes the following format control codes:
  86
  87    %%                   %
  88
  89    %c                   print condition code (always bits 28-31 in ARM mode)
  90    %q                   print shifter argument
  91    %u                   print condition code (unconditional in ARM mode,
  92                           UNPREDICTABLE if not AL in Thumb)
  93    %A                   print address for ldc/stc/ldf/stf instruction
  94    %B                   print vstm/vldm register list
  95    %I                   print cirrus signed shift immediate: bits 0..3|4..6
  96    %F                   print the COUNT field of a LFM/SFM instruction.
  97    %P                   print floating point precision in arithmetic insn
  98    %Q                   print floating point precision in ldf/stf insn
  99    %R                   print floating point rounding mode
 100
 101    %<bitfield>c         print as a condition code (for vsel)
 102    %<bitfield>r         print as an ARM register
 103    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 104    %<bitfield>ru        as %<>r but each u register must be unique.
 105    %<bitfield>d         print the bitfield in decimal
 106    %<bitfield>k         print immediate for VFPv3 conversion instruction
 107    %<bitfield>x         print the bitfield in hex
 108    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 109    %<bitfield>f         print a floating point constant if >7 else a
 110                         floating point register
 111    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 112    %<bitfield>g         print as an iWMMXt 64-bit register
 113    %<bitfield>G         print as an iWMMXt general purpose or control register
 114    %<bitfield>D         print as a NEON D register
 115    %<bitfield>Q         print as a NEON Q register
 116    %<bitfield>V         print as a NEON D or Q register
 117    %<bitfield>E         print a quarter-float immediate value
 118
 119    %y<code>             print a single precision VFP reg.
 120                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 121    %z<code>             print a double precision VFP reg
 122                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 123
 124    %<bitfield>'c        print specified char iff bitfield is all ones
 125    %<bitfield>`c        print specified char iff bitfield is all zeroes
 126    %<bitfield>?ab...    select from array of values in big endian order
 127
 128    %L                   print as an iWMMXt N/M width field.
 129    %Z                   print the Immediate of a WSHUFH instruction.
 130    %l                   like 'A' except use byte offsets for 'B' & 'H'
 131                         versions.
 132    %i                   print 5-bit immediate in bits 8,3..0
 133                         (print "32" when 0)
 134    %r                   print register offset address for wldt/wstr instruction.  */
 135
 136 enum opcode_sentinel_enum
 137 {
 138   SENTINEL_IWMMXT_START = 1,
 139   SENTINEL_IWMMXT_END,
 140   SENTINEL_GENERIC_START
 141 } opcode_sentinels;
 142
 143 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 144 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 145
 146 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 147
 148 static const struct opcode32 coprocessor_opcodes[] =
 149 {
 150   /* XScale instructions.  */
 151   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 152     0x0e200010, 0x0fff0ff0,
 153     "mia%c\tacc0, %0-3r, %12-15r"},
 154   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 155     0x0e280010, 0x0fff0ff0,
 156     "miaph%c\tacc0, %0-3r, %12-15r"},
 157   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 158     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 159   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 160     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 161   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 162     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 163
 164   /* Intel Wireless MMX technology instructions.  */
 165   {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 166   {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 167     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 168   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 169     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 170   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 171     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 172   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 173     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 174   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 175     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 176   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 177     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 178   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 179     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 180   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 181     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 182   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 183     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 184   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 185     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 186   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 187     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 188   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 189     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 190   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 191     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 192   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 193     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 194   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 195     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 196   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 197     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 198   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 199     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 200   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 201     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 202   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 203     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 204   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 205     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 206   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 207     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 208   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 209     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 210   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 211     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 212   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 213     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 214   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 215     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 216   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 217     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 218   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 219     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 220   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 221     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 222   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 223     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 224   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 225     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 226   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 227     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 228   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 229     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 230   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 231     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 232   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 233     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 234   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 235     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 236   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 237     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 238   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 239     0x0e800120, 0x0f800ff0,
 240     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 241   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 242     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 243   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 244     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 245   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 246     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 247   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 248     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 249   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 250     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 251   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 252     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 253   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 254     0x0e8000a0, 0x0f800ff0,
 255     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 256   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 257     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 258   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 259     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 260   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 261     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 262   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 263     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 264   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 265     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 266   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 267     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 268   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 269     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 270   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 271     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 272   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 273     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 274   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 275     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 276   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 277     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 278   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 279     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 280   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 281     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 282   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 283     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 284   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 285     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 286   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 287     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 288   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 289     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 290   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 291     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 292   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 293     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 294   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 295     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 296   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 297     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 298   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 299     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 300   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 301     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 302   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 303     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 304   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 305     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 306   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 307     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 308   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 309     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 310   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 311     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 312   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 313     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 314   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 315     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 316   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 317     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 318   {ARM_FEATURE_CORE_LOW (0),
 319     SENTINEL_IWMMXT_END, 0, "" },
 320
 321   /* Floating point coprocessor (FPA) instructions.  */
 322   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 323     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 324   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 325     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 326   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 327     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 328   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 329     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 330   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 331     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 332   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 333     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 334   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 335     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 336   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 337     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 338   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 339     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 340   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 341     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 342   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 343     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 344   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 345     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 346   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 347     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 348   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 349     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 350   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 351     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 352   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 353     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 354   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 355     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 356   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 357     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 358   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 359     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 360   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 361     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 362   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 363     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 364   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 365     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 366   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 367     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 368   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 369     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 370   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 371     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 372   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 373     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 374   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 375     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 376   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 377     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 378   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 379     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 380   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 381     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 382   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 383     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 384   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 385     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 386   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 387     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 388   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 389     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 390   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 391     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 392   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 393     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 394   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 395     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 396   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 397     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 398   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 399     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 400   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 401     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 402   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 403     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 404   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 405     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 406   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 407     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 408
 409   /* ARMv8-M Mainline Security Extensions instructions.  */
 410   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 411     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 412   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 413     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 414
 415   /* Register load/store.  */
 416   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 417     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 418   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 419     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 420   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 421     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 422   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 423     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 424   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 425     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 426   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 427     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 428   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 429     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 430   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 431     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 432   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 433     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 434   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 435     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 436   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 437     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 438   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 439     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 440   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 441     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 442   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 443     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 444   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 445     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 446   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 447     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 448
 449   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 450     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 451   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 452     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 453   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 454     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 455   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 456     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 457
 458   /* Data transfer between ARM and NEON registers.  */
 459   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 460     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 461   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 462     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 464     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 465   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 466     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 468     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 469   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 470     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 472     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 474     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 476     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 477   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 478     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 480     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 482     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 484     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 486     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 487   /* Half-precision conversion instructions.  */
 488   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 489     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 490   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 491     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 492   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 493     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 494   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 495     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 496
 497   /* Floating point coprocessor (VFP) instructions.  */
 498   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 499     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 500   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 501     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 502   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 503     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 504   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 505     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 506   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 507     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 508   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 509     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 510   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 511     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 512   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 513     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 514   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 515     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 516   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 517     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 518   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 519     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 520   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 521     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 522   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 523     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 524   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 525     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 526   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 527     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 528   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 529     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 530   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 531     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 532   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 533     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 534   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 535     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 536   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 537     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 538   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 539     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 540   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 541     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 542   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 543     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 544   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 545     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 546   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 547     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 548   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 549     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 550   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 551     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 552   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 553     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 554   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 555     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 556   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 557     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 558   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 559     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 560   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 561     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 562   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 563     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 564   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 565     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 566   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 567     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 568   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 569     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 570   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 571     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 572   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 573     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 574   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 575     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 576   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 577     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 578   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 579     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 580   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 581     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 582   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 583     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 584   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 585     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 586   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 587     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 588   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 589     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 590   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 591     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 592   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 593     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 594   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 595     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 596   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 597     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 598   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 599     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 600   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 601     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 602   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 603     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 604   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 605     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 606   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 607     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 608   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 609     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 610   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 611     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 612   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 613     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 614   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 615     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 616   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 617     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 618   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 619     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 620   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 621     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 622   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 623     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 624   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 625     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 626   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 627     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 628   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 629     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 630   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 631     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 632   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 633     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 634   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 635     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 636
 637   /* Cirrus coprocessor instructions.  */
 638   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 639     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 640   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 641     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 642   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 643     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 644   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 645     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 646   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 647     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 648   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 649     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 650   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 651     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 652   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 653     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 654   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 655     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 656   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 657     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 658   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 659     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 660   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 661     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 662   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 663     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 664   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 665     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 666   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 667     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 668   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 669     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 670   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 671     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 672   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 673     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 674   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 675     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 676   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 677     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 678   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 679     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 680   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 681     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 682   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 683     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 684   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 685     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 686   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 687     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 688   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 689     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 690   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 691     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 692   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 693     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 694   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 695     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 696   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 697     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 698   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 699     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 700   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 701     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 702   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 703     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 704   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 705     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 706   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 707     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 708   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 709     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 710   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 711     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 712   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 713     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 714   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 715     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 716   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 717     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 718   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 719     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 720   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 721     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 722   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 723     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 724   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 725     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 726   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 727     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 728   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 729     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 730   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 731     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 732   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 733     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 734   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 735     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 736   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 737     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 738   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 739     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 740   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 741     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 742   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 743     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 744   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 745     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 746   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 747     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 748   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 749     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 750   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 751     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 752   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 753     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 754   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 755     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 756   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 757     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 758   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 759     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 760   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 761     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 762   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 763     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 764   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 765     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 766   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 767     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 768   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 769     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 770   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 771     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 772   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 773     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 774   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 775     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 776   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 777     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 778   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 779     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 780   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 781     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 782   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 783     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 784   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 785     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 786   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 787     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 788   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 789     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 790   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 791     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 792   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 793     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 794   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 795     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 796   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 797     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 798   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 799     0x0e000600, 0x0ff00f10,
 800     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 801   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 802     0x0e100600, 0x0ff00f10,
 803     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 804   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 805     0x0e200600, 0x0ff00f10,
 806     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 807   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 808     0x0e300600, 0x0ff00f10,
 809     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 810
 811   /* VFP Fused multiply add instructions.  */
 812   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 813     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 814   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 815     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 816   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 817     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 818   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 819     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 820   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 821     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 822   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 823     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 824   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 825     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 826   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 827     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 828
 829   /* FP v5.  */
 830   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 831     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 832   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 833     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 834   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 835     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 836   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 837     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 838   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 839     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
 840   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 841     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
 842   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 843     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 844   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 845     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 846   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 847     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 848   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 849     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 850   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 851     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 852   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 853     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 854
 855   /* Generic coprocessor instructions.  */
 856   {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 857   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 858     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 860     0x0c500000, 0x0ff00000,
 861     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 863     0x0e000000, 0x0f000010,
 864     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 865   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 866     0x0e10f010, 0x0f10f010,
 867     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 869     0x0e100010, 0x0f100010,
 870     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 872     0x0e000010, 0x0f100010,
 873     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 875     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 877     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 878
 879   /* V6 coprocessor instructions.  */
 880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 881     0xfc500000, 0xfff00000,
 882     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 884     0xfc400000, 0xfff00000,
 885     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 886
 887   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
 888   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 889     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 890   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 891     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 892   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 893     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 894   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 895     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 896   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 897     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 898   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 899     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 900   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 901     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
 902   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 903     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
 904   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 905     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
 906   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 907     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 908
 909   /* Dot Product instructions in the space of coprocessor 13.  */
 910   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 911     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
 912   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 913     0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
 914
 915   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
 916   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 917     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
 918   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 919     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
 920   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 921     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
 922   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 923     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
 924   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 925     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
 926   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 927     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
 928   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 929     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
 930   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 931     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
 932
 933   /* V5 coprocessor instructions.  */
 934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 935     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 937     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 939     0xfe000000, 0xff000010,
 940     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 941   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 942     0xfe000010, 0xff100010,
 943     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 945     0xfe100010, 0xff100010,
 946     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 947
 948   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
 949      cp_num: bit <11:8> == 0b1001.
 950      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
 951   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 952     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
 953   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 954     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
 955   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 956     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
 957   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 958     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
 959   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 960     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 961   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 962     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
 963   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 964     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
 965   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 966     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
 967   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 968     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
 969   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 970     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
 971   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 972     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
 973   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 974     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
 975   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 976     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
 977   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 978     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
 979   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 980     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
 981   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 982     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
 983   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 984     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
 985   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 986     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
 987   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 988     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
 989   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 990     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
 991   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 992     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
 993   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 994     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
 995   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 996     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
 997   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 998     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
 999   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1001   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1003   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1004     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1005   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1006     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1007   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1008     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1009   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1010     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1011   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1012     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1013   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1014     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1015   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1016     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1017   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1018     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1019   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1020     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1021
1022   /* ARMv8.3 javascript conversion instruction.  */
1023   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1024     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1025
1026   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1027 };
1028
1029 /* Neon opcode table:  This does not encode the top byte -- that is
1030    checked by the print_insn_neon routine, as it depends on whether we are
1031    doing thumb32 or arm32 disassembly.  */
1032
1033 /* print_insn_neon recognizes the following format control codes:
1034
1035    %%                   %
1036
1037    %c                   print condition code
1038    %u                   print condition code (unconditional in ARM mode,
1039                           UNPREDICTABLE if not AL in Thumb)
1040    %A                   print v{st,ld}[1234] operands
1041    %B                   print v{st,ld}[1234] any one operands
1042    %C                   print v{st,ld}[1234] single->all operands
1043    %D                   print scalar
1044    %E                   print vmov, vmvn, vorr, vbic encoded constant
1045    %F                   print vtbl,vtbx register list
1046
1047    %<bitfield>r         print as an ARM register
1048    %<bitfield>d         print the bitfield in decimal
1049    %<bitfield>e         print the 2^N - bitfield in decimal
1050    %<bitfield>D         print as a NEON D register
1051    %<bitfield>Q         print as a NEON Q register
1052    %<bitfield>R         print as a NEON D or Q register
1053    %<bitfield>Sn        print byte scaled width limited by n
1054    %<bitfield>Tn        print short scaled width limited by n
1055    %<bitfield>Un        print long scaled width limited by n
1056
1057    %<bitfield>'c        print specified char iff bitfield is all ones
1058    %<bitfield>`c        print specified char iff bitfield is all zeroes
1059    %<bitfield>?ab...    select from array of values in big endian order.  */
1060
1061 static const struct opcode32 neon_opcodes[] =
1062 {
1063   /* Extract.  */
1064   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1065     0xf2b00840, 0xffb00850,
1066     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1067   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1068     0xf2b00000, 0xffb00810,
1069     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1070
1071   /* Move data element to all lanes.  */
1072   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1074   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1076   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1078
1079   /* Table lookup.  */
1080   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1082   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1084
1085   /* Half-precision conversions.  */
1086   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1087     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1088   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1089     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1090
1091   /* NEON fused multiply add instructions.  */
1092   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1093     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1095     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1097     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1099     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100
1101   /* Two registers, miscellaneous.  */
1102   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1103     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1104   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1105     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1106   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1107     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1108   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1109     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1110   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1111     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1112   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1113     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1114   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1115     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1116   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1117     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1118   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1119     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1120   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1121     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1122   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1123     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1124   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1126   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1128   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1130   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1132   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1134   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1136   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1138   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1140   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1142   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1144   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145     0xf3b20300, 0xffb30fd0,
1146     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1147   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1149   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1150     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1151   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1153   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1154     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1155   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1157   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1159   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1161   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1163   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1165   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1167   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1169   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1171   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1173   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1175   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1177   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1179   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1181   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1183   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1185   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1187   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1189   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1191   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1193   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194     0xf3bb0600, 0xffbf0e10,
1195     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1196   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1197     0xf3b70600, 0xffbf0e10,
1198     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1199
1200   /* Three registers of the same length.  */
1201   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1202     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1203   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1204     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1205   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1206     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1207   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1208     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1209   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1210     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1211   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1212     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1213   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1214     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1215   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1216     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1217   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1218     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1220     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1222     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1242     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1244     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1246     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1248     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1252     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1254     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1256     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1262     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1266     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1270     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1274     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1278     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1281   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1282     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1285   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1286     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1290     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1293   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1294     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1297   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1298     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1301   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1302     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1306     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1309   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1310     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318     0xf2000b00, 0xff800f10,
1319     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1320   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321     0xf2000b10, 0xff800f10,
1322     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1323   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330     0xf3000b00, 0xff800f10,
1331     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1332   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333     0xf2000000, 0xfe800f10,
1334     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1335   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336     0xf2000010, 0xfe800f10,
1337     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1338   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339     0xf2000100, 0xfe800f10,
1340     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342     0xf2000200, 0xfe800f10,
1343     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1344   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345     0xf2000210, 0xfe800f10,
1346     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1347   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348     0xf2000300, 0xfe800f10,
1349     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1350   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351     0xf2000310, 0xfe800f10,
1352     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354     0xf2000400, 0xfe800f10,
1355     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1356   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357     0xf2000410, 0xfe800f10,
1358     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1359   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360     0xf2000500, 0xfe800f10,
1361     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1362   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363     0xf2000510, 0xfe800f10,
1364     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1365   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366     0xf2000600, 0xfe800f10,
1367     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1368   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369     0xf2000610, 0xfe800f10,
1370     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1371   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372     0xf2000700, 0xfe800f10,
1373     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1374   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375     0xf2000710, 0xfe800f10,
1376     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1377   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378     0xf2000910, 0xfe800f10,
1379     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1380   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381     0xf2000a00, 0xfe800f10,
1382     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1383   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384     0xf2000a10, 0xfe800f10,
1385     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1386   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1387     0xf3000b10, 0xff800f10,
1388     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1389   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1390     0xf3000c10, 0xff800f10,
1391     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1392
1393   /* One register and an immediate value.  */
1394   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1396   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1398   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1400   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1402   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1404   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1406   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1408   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1410   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1412   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1414   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1416   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1418   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1420
1421   /* Two registers and a shift amount.  */
1422   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1424   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1426   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1428   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1430   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1432   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433     0xf2880950, 0xfeb80fd0,
1434     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1435   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1437   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1439   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1441   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1443   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1445   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1447   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1449   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1451   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1453   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1455   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456     0xf2900950, 0xfeb00fd0,
1457     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1458   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1460   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1462   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1464   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1466   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1468   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1470   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1472   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1474   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1476   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1478   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1480   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1482   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1484   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1486   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1488   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1490   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1492   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1494   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1496   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1498   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1500   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501     0xf2a00950, 0xfea00fd0,
1502     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1503   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1505   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1509   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1511   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1513   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1515   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1517   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1519   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1521   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1523   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1525   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1527   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1529   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1531   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1533   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1535   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1537   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1539   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540     0xf2a00e10, 0xfea00e90,
1541     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1542   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1543     0xf2a00c10, 0xfea00e90,
1544     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1545
1546   /* Three registers of different lengths.  */
1547   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1548     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1549   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1551   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552     0xf2800400, 0xff800f50,
1553     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1554   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555     0xf2800600, 0xff800f50,
1556     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1557   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558     0xf2800900, 0xff800f50,
1559     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1560   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561     0xf2800b00, 0xff800f50,
1562     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1563   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564     0xf2800d00, 0xff800f50,
1565     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1566   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567     0xf3800400, 0xff800f50,
1568     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1569   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570     0xf3800600, 0xff800f50,
1571     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1572   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573     0xf2800000, 0xfe800f50,
1574     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1575   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576     0xf2800100, 0xfe800f50,
1577     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1578   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579     0xf2800200, 0xfe800f50,
1580     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1581   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582     0xf2800300, 0xfe800f50,
1583     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1584   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585     0xf2800500, 0xfe800f50,
1586     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1587   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588     0xf2800700, 0xfe800f50,
1589     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1590   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591     0xf2800800, 0xfe800f50,
1592     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1593   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594     0xf2800a00, 0xfe800f50,
1595     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1596   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597     0xf2800c00, 0xfe800f50,
1598     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1599
1600   /* Two registers and a scalar.  */
1601   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1603   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1605   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1606     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1607   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1609   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1611   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1613   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1614     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1615   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1617   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1619   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1621   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1622     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1623   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1625   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1627   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1629   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1631   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1633   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1634     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1635   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1637   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1639   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1640     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1641   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1643   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1645   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1646     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1647   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1649   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1651   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652     0xf2800240, 0xfe800f50,
1653     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1654   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655     0xf2800640, 0xfe800f50,
1656     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1657   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658     0xf2800a40, 0xfe800f50,
1659     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1660   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1661     0xf2800e40, 0xff800f50,
1662    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1663   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1664     0xf2800f40, 0xff800f50,
1665    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1666   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1667     0xf3800e40, 0xff800f50,
1668    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1669   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1670     0xf3800f40, 0xff800f50,
1671    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1672   },
1673
1674   /* Element and structure load/store.  */
1675   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1677   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1679   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1681   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1683   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1685   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1687   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1689   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1691   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1693   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1695   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1697   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1699   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1701   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1703   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1705   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1707   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1709   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1711   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1713
1714   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1715 };
1716
1717 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
1718    ordered: they must be searched linearly from the top to obtain a correct
1719    match.  */
1720
1721 /* print_insn_arm recognizes the following format control codes:
1722
1723    %%                   %
1724
1725    %a                   print address for ldr/str instruction
1726    %s                   print address for ldr/str halfword/signextend instruction
1727    %S                   like %s but allow UNPREDICTABLE addressing
1728    %b                   print branch destination
1729    %c                   print condition code (always bits 28-31)
1730    %m                   print register mask for ldm/stm instruction
1731    %o                   print operand2 (immediate or register + shift)
1732    %p                   print 'p' iff bits 12-15 are 15
1733    %t                   print 't' iff bit 21 set and bit 24 clear
1734    %B                   print arm BLX(1) destination
1735    %C                   print the PSR sub type.
1736    %U                   print barrier type.
1737    %P                   print address for pli instruction.
1738
1739    %<bitfield>r         print as an ARM register
1740    %<bitfield>T         print as an ARM register + 1
1741    %<bitfield>R         as %r but r15 is UNPREDICTABLE
1742    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1743    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1744    %<bitfield>d         print the bitfield in decimal
1745    %<bitfield>W         print the bitfield plus one in decimal
1746    %<bitfield>x         print the bitfield in hex
1747    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
1748
1749    %<bitfield>'c        print specified char iff bitfield is all ones
1750    %<bitfield>`c        print specified char iff bitfield is all zeroes
1751    %<bitfield>?ab...    select from array of values in big endian order
1752
1753    %e                   print arm SMI operand (bits 0..7,8..19).
1754    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
1755    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
1756    %R                   print the SPSR/CPSR or banked register of an MRS.  */
1757
1758 static const struct opcode32 arm_opcodes[] =
1759 {
1760   /* ARM instructions.  */
1761   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1762     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1764     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1765
1766   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1767     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1769     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1771     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1773     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1775     0x00800090, 0x0fa000f0,
1776     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1777   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1778     0x00a00090, 0x0fa000f0,
1779     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1780
1781   /* V8.2 RAS extension instructions.  */
1782   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
1783     0xe320f010, 0xffffffff, "esb"},
1784
1785   /* V8 instructions.  */
1786   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1787     0x0320f005, 0x0fffffff, "sevl"},
1788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1789     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1790   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1791     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1792   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1793     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1794   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1795     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1796   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1797     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1798   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1799     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1800   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1801     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1802   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1803     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1804   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1805     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1806   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1807     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1808   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1809     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1810   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1811     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1812   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1813     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1814   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1815     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1816   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1817     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1818   /* CRC32 instructions.  */
1819   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1820     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1821   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1822     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1823   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1824     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1825   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1826     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1827   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1828     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1829   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1830     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1831
1832   /* Privileged Access Never extension instructions.  */
1833   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1834     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1835
1836   /* Virtualization Extension instructions.  */
1837   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1838   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1839
1840   /* Integer Divide Extension instructions.  */
1841   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1842     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1843   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1844     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1845
1846   /* MP Extension instructions.  */
1847   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1848
1849   /* V7 instructions.  */
1850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1851   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1857    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1858     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1859
1860   /* ARM V6T2 instructions.  */
1861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1862     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1864     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1865   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1866     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1868     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1869
1870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1871     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1873     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1874
1875   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1876     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1877   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1878     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1880     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1882     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1883
1884   /* ARM Security extension instructions.  */
1885   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1886     0x01600070, 0x0ff000f0, "smc%c\t%e"},
1887
1888   /* ARM V6K instructions.  */
1889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1890     0xf57ff01f, 0xffffffff, "clrex"},
1891   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1892     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1893   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1894     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1896     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1898     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1900     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1902     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1903
1904   /* CSDB.  */
1905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1906
1907   /* ARM V6K NOP hints.  */
1908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1909     0x0320f001, 0x0fffffff, "yield%c"},
1910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1911     0x0320f002, 0x0fffffff, "wfe%c"},
1912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1913     0x0320f003, 0x0fffffff, "wfi%c"},
1914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1915     0x0320f004, 0x0fffffff, "sev%c"},
1916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1917     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1918
1919   /* ARM V6 instructions.  */
1920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1921     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1923     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1925     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1927     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1929     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1931     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1933     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1935     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1937     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1939     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1941     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1943     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1945     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1947     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1949     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1951     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1953     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1955     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1957     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1959     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1961     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1963     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1965     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1967     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1969     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1971     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1973     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1975     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1977     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1979     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1981     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1983     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1985     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1987     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1989     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1991     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1993     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1995     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1997     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1999     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2001     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2003     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2005     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2007     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2009     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2011     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2013     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2015     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2017     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2019     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2021     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2023     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2025     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2027     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2029     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2031     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2033     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2035     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2037     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2039     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2041     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2043     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2045     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2047     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2049     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2051     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2053     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2055     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2057     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2059     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2061     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2063     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2065     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2067     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2069     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2071     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2073     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2075     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2077     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2079     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2081     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2082   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2083     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2085     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2087     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2089     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2091     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2093     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2095     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2097     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2099     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2101     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2103     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2105     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2107     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2109     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2111     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2113     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2115     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2117     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2119     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2121     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2123     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2125     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2126   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2127     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2129     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2131     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2133     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2135     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2137     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2139     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2141     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2143     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2145     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2147     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2149     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2151     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2153     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2155     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2156   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2157     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2159     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2161     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2163     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2164
2165   /* V5J instruction.  */
2166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2167     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2168
2169   /* V5 Instructions.  */
2170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2171     0xe1200070, 0xfff000f0,
2172     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2174     0xfa000000, 0xfe000000, "blx\t%B"},
2175   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2176     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2177   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2178     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2179
2180   /* V5E "El Segundo" Instructions.  */
2181   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2182     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2183   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2184     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2185   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2186     0xf450f000, 0xfc70f000, "pld\t%a"},
2187   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2188     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2189   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2190     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2191   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2192     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2193   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2194     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2195
2196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2197     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2198   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2199     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2200
2201   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2202     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2203   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2204     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2205   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2206     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2207   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2208     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2209
2210   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2211     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2212   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2213     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2215     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2217     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2218
2219   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2220     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2221   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2222     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2223
2224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2225     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2226   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2227     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2228   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2229     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2230   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2231     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2232
2233   /* ARM Instructions.  */
2234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2235     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2236
2237   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2239   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2241   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2243   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2244     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2245   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2247   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2249
2250   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2252   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2256   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2258
2259   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2260     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2261   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2263   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2264     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2265   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2266     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2267
2268   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2270   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2272   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2274
2275   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2277   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2279   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2281
2282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2283     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2285     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2288
2289   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2290     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2291   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2293   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2295
2296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2297     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2298   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2299     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2300   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2301     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2302
2303   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2304     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2305   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2306     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2307   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2308     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2309
2310   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2312   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2313     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2314   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2316
2317   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2318     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2319   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2320     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2321   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2323
2324   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2325     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2326   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2327     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2328   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2329     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2330
2331   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2332     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2333   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2334     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2335   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2336     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2337
2338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2339     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2341     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2344
2345   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2346     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2347   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2349   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2351
2352   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2353     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2354   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2355     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2356   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2357     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2358
2359   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2361   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2362     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2363   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2364     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2365
2366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2367     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2368   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2369     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2370   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2371     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2372   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2373     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2374   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2375     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2376   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2377     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2379     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2380
2381   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2382     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2383   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2384     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2385   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2386     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2387
2388   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2389     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2390   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2391     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2392   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2393     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2394
2395   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2396     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2397   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2399
2400   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2402
2403   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2405   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2407
2408   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2410   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2412   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2413     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2414   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2415     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2416   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2417     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2418   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2419     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2420   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2421     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2432   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2435     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2437     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441     0x092d0000, 0x0fff0000, "push%c\t%m"},
2442   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2446
2447   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2448     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2449   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2450     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2451   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2452     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2453   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2454     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2455   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2456     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2457   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2458     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2459   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2460     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2461   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2462     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2463   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2464     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2465   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2466     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2467   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2468     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2469   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2470     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2471   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2472     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2473   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2474     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2475   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2476     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2477   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2478     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2479   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2480     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2481   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2482     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2483   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2484     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2485
2486   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2487     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2488   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2489     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2490
2491   /* The rest.  */
2492   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2493     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2495     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2496   {ARM_FEATURE_CORE_LOW (0),
2497     0x00000000, 0x00000000, 0}
2498 };
2499
2500 /* print_insn_thumb16 recognizes the following format control codes:
2501
2502    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2503    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2504    %<bitfield>I         print bitfield as a signed decimal
2505                                 (top bit of range being the sign bit)
2506    %N                   print Thumb register mask (with LR)
2507    %O                   print Thumb register mask (with PC)
2508    %M                   print Thumb register mask
2509    %b                   print CZB's 6-bit unsigned branch destination
2510    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2511    %c                   print the condition code
2512    %C                   print the condition code, or "s" if not conditional
2513    %x                   print warning if conditional an not at end of IT block"
2514    %X                   print "\t; unpredictable <IT:code>" if conditional
2515    %I                   print IT instruction suffix and operands
2516    %W                   print Thumb Writeback indicator for LDMIA
2517    %<bitfield>r         print bitfield as an ARM register
2518    %<bitfield>d         print bitfield as a decimal
2519    %<bitfield>H         print (bitfield * 2) as a decimal
2520    %<bitfield>W         print (bitfield * 4) as a decimal
2521    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2522    %<bitfield>B         print Thumb branch destination (signed displacement)
2523    %<bitfield>c         print bitfield as a condition code
2524    %<bitnum>'c          print specified char iff bit is one
2525    %<bitnum>?ab         print a if bit is one else print b.  */
2526
2527 static const struct opcode16 thumb_opcodes[] =
2528 {
2529   /* Thumb instructions.  */
2530
2531   /* ARMv8-M Security Extensions instructions.  */
2532   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2533   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
2534
2535   /* ARM V8 instructions.  */
2536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2537   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2538   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2539
2540   /* ARM V6K no-argument instructions.  */
2541   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2542   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2543   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2545   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2546   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2547
2548   /* ARM V6T2 instructions.  */
2549   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2550     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2551   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2552     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2553   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2554
2555   /* ARM V6.  */
2556   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2557   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2558   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2559   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2561   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2562   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2563   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2567
2568   /* ARM V5 ISA extends Thumb.  */
2569   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2570     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2571   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2573     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2574   /* ARM V4T ISA (Thumb v1).  */
2575   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2576     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2577   /* Format 4.  */
2578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2579   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2581   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2583   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2584   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2585   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2586   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2587   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2588   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2589   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2591   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2592   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2593   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2594   /* format 13 */
2595   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2597   /* format 5 */
2598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2599   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2601   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2602   /* format 14 */
2603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2604   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2605   /* format 2 */
2606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2607     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2609     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2610   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2611     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2612   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2613     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2614   /* format 8 */
2615   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2616     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2617   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2618     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2619   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2620     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2621   /* format 7 */
2622   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2623     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2624   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2625     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2626   /* format 1 */
2627   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2628   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2629     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2630   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2631   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2632   /* format 3 */
2633   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2634   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2635   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2636   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2637   /* format 6 */
2638   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2639   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2640     0x4800, 0xF800,
2641     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2642   /* format 9 */
2643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2644     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2645   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2646     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2647   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2648     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2649   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2650     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2651   /* format 10 */
2652   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2653     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2654   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2655     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2656   /* format 11 */
2657   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2658     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2659   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2660     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2661   /* format 12 */
2662   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2663     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2664   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2665     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2666   /* format 15 */
2667   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2668   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2669   /* format 17 */
2670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2671   /* format 16 */
2672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2673   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2674   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2675   /* format 18 */
2676   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2677
2678   /* The E800 .. FFFF range is unconditionally redirected to the
2679      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2680      are processed via that table.  Thus, we can never encounter a
2681      bare "second half of BL/BLX(1)" instruction here.  */
2682   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2683   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2684 };
2685
2686 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2687    We adopt the convention that hw1 is the high 16 bits of .value and
2688    .mask, hw2 the low 16 bits.
2689
2690    print_insn_thumb32 recognizes the following format control codes:
2691
2692        %%               %
2693
2694        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2695        %M               print a modified 12-bit immediate (same location)
2696        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2697        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2698        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
2699        %S               print a possibly-shifted Rm
2700
2701        %L               print address for a ldrd/strd instruction
2702        %a               print the address of a plain load/store
2703        %w               print the width and signedness of a core load/store
2704        %m               print register mask for ldm/stm
2705
2706        %E               print the lsb and width fields of a bfc/bfi instruction
2707        %F               print the lsb and width fields of a sbfx/ubfx instruction
2708        %b               print a conditional branch offset
2709        %B               print an unconditional branch offset
2710        %s               print the shift field of an SSAT instruction
2711        %R               print the rotation field of an SXT instruction
2712        %U               print barrier type.
2713        %P               print address for pli instruction.
2714        %c               print the condition code
2715        %x               print warning if conditional an not at end of IT block"
2716        %X               print "\t; unpredictable <IT:code>" if conditional
2717
2718        %<bitfield>d     print bitfield in decimal
2719        %<bitfield>D     print bitfield plus one in decimal
2720        %<bitfield>W     print bitfield*4 in decimal
2721        %<bitfield>r     print bitfield as an ARM register
2722        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
2723        %<bitfield>c     print bitfield as a condition code
2724
2725        %<bitfield>'c    print specified char iff bitfield is all ones
2726        %<bitfield>`c    print specified char iff bitfield is all zeroes
2727        %<bitfield>?ab... select from array of values in big endian order
2728
2729    With one exception at the bottom (done because BL and BLX(1) need
2730    to come dead last), this table was machine-sorted first in
2731    decreasing order of number of bits set in the mask, then in
2732    increasing numeric order of mask, then in increasing numeric order
2733    of opcode.  This order is not the clearest for a human reader, but
2734    is guaranteed never to catch a special-case bit pattern with a more
2735    general mask, which is important, because this instruction encoding
2736    makes heavy use of special-case bit patterns.  */
2737 static const struct opcode32 thumb32_opcodes[] =
2738 {
2739   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
2740   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
2741   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2742     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2743   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2744     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2745   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2746     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2747   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2748     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2749
2750   /* ARM V8.2 RAS extension instructions.  */
2751   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2752     0xf3af8010, 0xffffffff, "esb"},
2753
2754   /* V8 instructions.  */
2755   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2756     0xf3af8005, 0xffffffff, "sevl%c.w"},
2757   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2758     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2759   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2760     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2761   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2762     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2764     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2765   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2766     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2767   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2768     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2769   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2770     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2771   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2772     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2773   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2774     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2775   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2776     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2777   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2778     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2779   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2780     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2781   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2782     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2783   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2784     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2785   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2786     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2787
2788   /* CRC32 instructions.  */
2789   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2790     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
2791   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2792     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
2793   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2794     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
2795   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2796     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
2797   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2798     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
2799   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2800     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
2801
2802   /* V7 instructions.  */
2803   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2804   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2806   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2808   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2810   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2811     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2812   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2813     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2814
2815   /* Virtualization Extension instructions.  */
2816   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2817   /* We skip ERET as that is SUBS pc, lr, #0.  */
2818
2819   /* MP Extension instructions.  */
2820   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
2821
2822   /* Security extension instructions.  */
2823   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2824
2825   /* CSDB.  */
2826   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2827
2828   /* Instructions defined in the basic V6T2 set.  */
2829   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2831   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2833   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2834   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2837
2838   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2839     0xf3bf8f2f, 0xffffffff, "clrex%c"},
2840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2842   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2844   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2866   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2867     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2868   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2869     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2886   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2887     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2994   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2995     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
2998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3062   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3063     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069     0xf810f000, 0xff70f000, "pld%c\t%a"},
3070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3082   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3091     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095     0xfb100000, 0xfff000c0,
3096     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3098     0xfbc00080, 0xfff000c0,
3099     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3105     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3109     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3110   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3111     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3114   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3115     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3117     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3123     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3126   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3127     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3131     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3133     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3135     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3136   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3137     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3139     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3143     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3145     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3149     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3151     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3155     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3156   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3157     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3163     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3167     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3169     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3171     0xe9400000, 0xff500000,
3172     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3174     0xe9500000, 0xff500000,
3175     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177     0xe8600000, 0xff700000,
3178     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3179   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3180     0xe8700000, 0xff700000,
3181     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3183     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3185     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3186
3187   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
3188   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3189     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3191     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3193     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3195     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3196
3197   /* These have been 32-bit since the invention of Thumb.  */
3198   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3199      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3200   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3201      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3202
3203   /* Fallback.  */
3204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3205       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3206   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3207 };
3208
3209 static const char *const arm_conditional[] =
3210 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3211  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3212
3213 static const char *const arm_fp_const[] =
3214 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3215
3216 static const char *const arm_shift[] =
3217 {"lsl", "lsr", "asr", "ror"};
3218
3219 typedef struct
3220 {
3221   const char *name;
3222   const char *description;
3223   const char *reg_names[16];
3224 }
3225 arm_regname;
3226
3227 static const arm_regname regnames[] =
3228 {
3229   { "reg-names-raw", N_("Select raw register names"),
3230     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3231   { "reg-names-gcc", N_("Select register names used by GCC"),
3232     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3233   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3234     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
3235   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3236   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3237   { "reg-names-apcs", N_("Select register names used in the APCS"),
3238     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3239   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3240     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3241   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3242     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
3243 };
3244
3245 static const char *const iwmmxt_wwnames[] =
3246 {"b", "h", "w", "d"};
3247
3248 static const char *const iwmmxt_wwssnames[] =
3249 {"b", "bus", "bc", "bss",
3250  "h", "hus", "hc", "hss",
3251  "w", "wus", "wc", "wss",
3252  "d", "dus", "dc", "dss"
3253 };
3254
3255 static const char *const iwmmxt_regnames[] =
3256 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3257   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3258 };
3259
3260 static const char *const iwmmxt_cregnames[] =
3261 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3262   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3263 };
3264
3265 /* Default to GCC register name set.  */
3266 static unsigned int regname_selected = 1;
3267
3268 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
3269 #define arm_regnames      regnames[regname_selected].reg_names
3270
3271 static bfd_boolean force_thumb = FALSE;
3272
3273 /* Current IT instruction state.  This contains the same state as the IT
3274    bits in the CPSR.  */
3275 static unsigned int ifthen_state;
3276 /* IT state for the next instruction.  */
3277 static unsigned int ifthen_next_state;
3278 /* The address of the insn for which the IT state is valid.  */
3279 static bfd_vma ifthen_address;
3280 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3281 /* Indicates that the current Conditional state is unconditional or outside
3282    an IT block.  */
3283 #define COND_UNCOND 16
3284
3285 \f
3286 /* Functions.  */
3287
3288 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3289    Returns pointer to following character of the format string and
3290    fills in *VALUEP and *WIDTHP with the extracted value and number of
3291    bits extracted.  WIDTHP can be NULL.  */
3292
3293 static const char *
3294 arm_decode_bitfield (const char *ptr,
3295                      unsigned long insn,
3296                      unsigned long *valuep,
3297                      int *widthp)
3298 {
3299   unsigned long value = 0;
3300   int width = 0;
3301
3302   do
3303     {
3304       int start, end;
3305       int bits;
3306
3307       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3308         start = start * 10 + *ptr - '0';
3309       if (*ptr == '-')
3310         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3311           end = end * 10 + *ptr - '0';
3312       else
3313         end = start;
3314       bits = end - start;
3315       if (bits < 0)
3316         abort ();
3317       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3318       width += bits + 1;
3319     }
3320   while (*ptr++ == ',');
3321   *valuep = value;
3322   if (widthp)
3323     *widthp = width;
3324   return ptr - 1;
3325 }
3326
3327 static void
3328 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3329                   bfd_boolean print_shift)
3330 {
3331   func (stream, "%s", arm_regnames[given & 0xf]);
3332
3333   if ((given & 0xff0) != 0)
3334     {
3335       if ((given & 0x10) == 0)
3336         {
3337           int amount = (given & 0xf80) >> 7;
3338           int shift = (given & 0x60) >> 5;
3339
3340           if (amount == 0)
3341             {
3342               if (shift == 3)
3343                 {
3344                   func (stream, ", rrx");
3345                   return;
3346                 }
3347
3348               amount = 32;
3349             }
3350
3351           if (print_shift)
3352             func (stream, ", %s #%d", arm_shift[shift], amount);
3353           else
3354             func (stream, ", #%d", amount);
3355         }
3356       else if ((given & 0x80) == 0x80)
3357         func (stream, "\t; <illegal shifter operand>");
3358       else if (print_shift)
3359         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3360               arm_regnames[(given & 0xf00) >> 8]);
3361       else
3362         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3363     }
3364 }
3365
3366 #define W_BIT 21
3367 #define I_BIT 22
3368 #define U_BIT 23
3369 #define P_BIT 24
3370
3371 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
3372 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
3373 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
3374 #define PRE_BIT_SET         (given & (1 << P_BIT))
3375
3376 /* Print one coprocessor instruction on INFO->STREAM.
3377    Return TRUE if the instuction matched, FALSE if this is not a
3378    recognised coprocessor instruction.  */
3379
3380 static bfd_boolean
3381 print_insn_coprocessor (bfd_vma pc,
3382                         struct disassemble_info *info,
3383                         long given,
3384                         bfd_boolean thumb)
3385 {
3386   const struct opcode32 *insn;
3387   void *stream = info->stream;
3388   fprintf_ftype func = info->fprintf_func;
3389   unsigned long mask;
3390   unsigned long value = 0;
3391   int cond;
3392   int cp_num;
3393   struct arm_private_data *private_data = info->private_data;
3394   arm_feature_set allowed_arches = ARM_ARCH_NONE;
3395
3396   allowed_arches = private_data->features;
3397
3398   for (insn = coprocessor_opcodes; insn->assembler; insn++)
3399     {
3400       unsigned long u_reg = 16;
3401       bfd_boolean is_unpredictable = FALSE;
3402       signed long value_in_comment = 0;
3403       const char *c;
3404
3405       if (ARM_FEATURE_ZERO (insn->arch))
3406         switch (insn->value)
3407           {
3408           case SENTINEL_IWMMXT_START:
3409             if (info->mach != bfd_mach_arm_XScale
3410                 && info->mach != bfd_mach_arm_iWMMXt
3411                 && info->mach != bfd_mach_arm_iWMMXt2)
3412               do
3413                 insn++;
3414               while ((! ARM_FEATURE_ZERO (insn->arch))
3415                      && insn->value != SENTINEL_IWMMXT_END);
3416             continue;
3417
3418           case SENTINEL_IWMMXT_END:
3419             continue;
3420
3421           case SENTINEL_GENERIC_START:
3422             allowed_arches = private_data->features;
3423             continue;
3424
3425           default:
3426             abort ();
3427           }
3428
3429       mask = insn->mask;
3430       value = insn->value;
3431       cp_num = (given >> 8) & 0xf;
3432
3433       if (thumb)
3434         {
3435           /* The high 4 bits are 0xe for Arm conditional instructions, and
3436              0xe for arm unconditional instructions.  The rest of the
3437              encoding is the same.  */
3438           mask |= 0xf0000000;
3439           value |= 0xe0000000;
3440           if (ifthen_state)
3441             cond = IFTHEN_COND;
3442           else
3443             cond = COND_UNCOND;
3444         }
3445       else
3446         {
3447           /* Only match unconditional instuctions against unconditional
3448              patterns.  */
3449           if ((given & 0xf0000000) == 0xf0000000)
3450             {
3451               mask |= 0xf0000000;
3452               cond = COND_UNCOND;
3453             }
3454           else
3455             {
3456               cond = (given >> 28) & 0xf;
3457               if (cond == 0xe)
3458                 cond = COND_UNCOND;
3459             }
3460         }
3461
3462       if ((given & mask) != value)
3463         continue;
3464
3465       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3466         continue;
3467
3468       if (insn->value == 0xfe000010     /* mcr2  */
3469           || insn->value == 0xfe100010  /* mrc2  */
3470           || insn->value == 0xfc100000  /* ldc2  */
3471           || insn->value == 0xfc000000) /* stc2  */
3472         {
3473           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3474             is_unpredictable = TRUE;
3475         }
3476       else if (insn->value == 0x0e000000     /* cdp  */
3477                || insn->value == 0xfe000000  /* cdp2  */
3478                || insn->value == 0x0e000010  /* mcr  */
3479                || insn->value == 0x0e100010  /* mrc  */
3480                || insn->value == 0x0c100000  /* ldc  */
3481                || insn->value == 0x0c000000) /* stc  */
3482         {
3483           /* Floating-point instructions.  */
3484           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3485             continue;
3486         }
3487
3488       for (c = insn->assembler; *c; c++)
3489         {
3490           if (*c == '%')
3491             {
3492               switch (*++c)
3493                 {
3494                 case '%':
3495                   func (stream, "%%");
3496                   break;
3497
3498                 case 'A':
3499                   {
3500                     int rn = (given >> 16) & 0xf;
3501                     bfd_vma offset = given & 0xff;
3502
3503                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3504
3505                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3506                       {
3507                         /* Not unindexed.  The offset is scaled.  */
3508                         if (cp_num == 9)
3509                           /* vldr.16/vstr.16 will shift the address
3510                              left by 1 bit only.  */
3511                           offset = offset * 2;
3512                         else
3513                           offset = offset * 4;
3514
3515                         if (NEGATIVE_BIT_SET)
3516                           offset = - offset;
3517                         if (rn != 15)
3518                           value_in_comment = offset;
3519                       }
3520
3521                     if (PRE_BIT_SET)
3522                       {
3523                         if (offset)
3524                           func (stream, ", #%d]%s",
3525                                 (int) offset,
3526                                 WRITEBACK_BIT_SET ? "!" : "");
3527                         else if (NEGATIVE_BIT_SET)
3528                           func (stream, ", #-0]");
3529                         else
3530                           func (stream, "]");
3531                       }
3532                     else
3533                       {
3534                         func (stream, "]");
3535
3536                         if (WRITEBACK_BIT_SET)
3537                           {
3538                             if (offset)
3539                               func (stream, ", #%d", (int) offset);
3540                             else if (NEGATIVE_BIT_SET)
3541                               func (stream, ", #-0");
3542                           }
3543                         else
3544                           {
3545                             func (stream, ", {%s%d}",
3546                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3547                                   (int) offset);
3548                             value_in_comment = offset;
3549                           }
3550                       }
3551                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3552                       {
3553                         func (stream, "\t; ");
3554                         /* For unaligned PCs, apply off-by-alignment
3555                            correction.  */
3556                         info->print_address_func (offset + pc
3557                                                   + info->bytes_per_chunk * 2
3558                                                   - (pc & 3),
3559                                                   info);
3560                       }
3561                   }
3562                   break;
3563
3564                 case 'B':
3565                   {
3566                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3567                     int offset = (given >> 1) & 0x3f;
3568
3569                     if (offset == 1)
3570                       func (stream, "{d%d}", regno);
3571                     else if (regno + offset > 32)
3572                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3573                     else
3574                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3575                   }
3576                   break;
3577
3578                 case 'u':
3579                   if (cond != COND_UNCOND)
3580                     is_unpredictable = TRUE;
3581
3582                   /* Fall through.  */
3583                 case 'c':
3584                   if (cond != COND_UNCOND && cp_num == 9)
3585                     is_unpredictable = TRUE;
3586
3587                   func (stream, "%s", arm_conditional[cond]);
3588                   break;
3589
3590                 case 'I':
3591                   /* Print a Cirrus/DSP shift immediate.  */
3592                   /* Immediates are 7bit signed ints with bits 0..3 in
3593                      bits 0..3 of opcode and bits 4..6 in bits 5..7
3594                      of opcode.  */
3595                   {
3596                     int imm;
3597
3598                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
3599
3600                     /* Is ``imm'' a negative number?  */
3601                     if (imm & 0x40)
3602                       imm -= 0x80;
3603
3604                     func (stream, "%d", imm);
3605                   }
3606
3607                   break;
3608
3609                 case 'F':
3610                   switch (given & 0x00408000)
3611                     {
3612                     case 0:
3613                       func (stream, "4");
3614                       break;
3615                     case 0x8000:
3616                       func (stream, "1");
3617                       break;
3618                     case 0x00400000:
3619                       func (stream, "2");
3620                       break;
3621                     default:
3622                       func (stream, "3");
3623                     }
3624                   break;
3625
3626                 case 'P':
3627                   switch (given & 0x00080080)
3628                     {
3629                     case 0:
3630                       func (stream, "s");
3631                       break;
3632                     case 0x80:
3633                       func (stream, "d");
3634                       break;
3635                     case 0x00080000:
3636                       func (stream, "e");
3637                       break;
3638                     default:
3639                       func (stream, _("<illegal precision>"));
3640                       break;
3641                     }
3642                   break;
3643
3644                 case 'Q':
3645                   switch (given & 0x00408000)
3646                     {
3647                     case 0:
3648                       func (stream, "s");
3649                       break;
3650                     case 0x8000:
3651                       func (stream, "d");
3652                       break;
3653                     case 0x00400000:
3654                       func (stream, "e");
3655                       break;
3656                     default:
3657                       func (stream, "p");
3658                       break;
3659                     }
3660                   break;
3661
3662                 case 'R':
3663                   switch (given & 0x60)
3664                     {
3665                     case 0:
3666                       break;
3667                     case 0x20:
3668                       func (stream, "p");
3669                       break;
3670                     case 0x40:
3671                       func (stream, "m");
3672                       break;
3673                     default:
3674                       func (stream, "z");
3675                       break;
3676                     }
3677                   break;
3678
3679                 case '0': case '1': case '2': case '3': case '4':
3680                 case '5': case '6': case '7': case '8': case '9':
3681                   {
3682                     int width;
3683
3684                     c = arm_decode_bitfield (c, given, &value, &width);
3685
3686                     switch (*c)
3687                       {
3688                       case 'R':
3689                         if (value == 15)
3690                           is_unpredictable = TRUE;
3691                         /* Fall through.  */
3692                       case 'r':
3693                         if (c[1] == 'u')
3694                           {
3695                             /* Eat the 'u' character.  */
3696                             ++ c;
3697
3698                             if (u_reg == value)
3699                               is_unpredictable = TRUE;
3700                             u_reg = value;
3701                           }
3702                         func (stream, "%s", arm_regnames[value]);
3703                         break;
3704                       case 'V':
3705                         if (given & (1 << 6))
3706                           goto Q;
3707                         /* FALLTHROUGH */
3708                       case 'D':
3709                         func (stream, "d%ld", value);
3710                         break;
3711                       case 'Q':
3712                       Q:
3713                         if (value & 1)
3714                           func (stream, "<illegal reg q%ld.5>", value >> 1);
3715                         else
3716                           func (stream, "q%ld", value >> 1);
3717                         break;
3718                       case 'd':
3719                         func (stream, "%ld", value);
3720                         value_in_comment = value;
3721                         break;
3722                       case 'E':
3723                         {
3724                           /* Converts immediate 8 bit back to float value.  */
3725                           unsigned floatVal = (value & 0x80) << 24
3726                             | (value & 0x3F) << 19
3727                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3728
3729                           /* Quarter float have a maximum value of 31.0.
3730                              Get floating point value multiplied by 1e7.
3731                              The maximum value stays in limit of a 32-bit int.  */
3732                           unsigned decVal =
3733                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3734                             (16 + (value & 0xF));
3735
3736                           if (!(decVal % 1000000))
3737                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3738                                   floatVal, value & 0x80 ? '-' : ' ',
3739                                   decVal / 10000000,
3740                                   decVal % 10000000 / 1000000);
3741                           else if (!(decVal % 10000))
3742                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3743                                   floatVal, value & 0x80 ? '-' : ' ',
3744                                   decVal / 10000000,
3745                                   decVal % 10000000 / 10000);
3746                           else
3747                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3748                                   floatVal, value & 0x80 ? '-' : ' ',
3749                                   decVal / 10000000, decVal % 10000000);
3750                           break;
3751                         }
3752                       case 'k':
3753                         {
3754                           int from = (given & (1 << 7)) ? 32 : 16;
3755                           func (stream, "%ld", from - value);
3756                         }
3757                         break;
3758
3759                       case 'f':
3760                         if (value > 7)
3761                           func (stream, "#%s", arm_fp_const[value & 7]);
3762                         else
3763                           func (stream, "f%ld", value);
3764                         break;
3765
3766                       case 'w':
3767                         if (width == 2)
3768                           func (stream, "%s", iwmmxt_wwnames[value]);
3769                         else
3770                           func (stream, "%s", iwmmxt_wwssnames[value]);
3771                         break;
3772
3773                       case 'g':
3774                         func (stream, "%s", iwmmxt_regnames[value]);
3775                         break;
3776                       case 'G':
3777                         func (stream, "%s", iwmmxt_cregnames[value]);
3778                         break;
3779
3780                       case 'x':
3781                         func (stream, "0x%lx", (value & 0xffffffffUL));
3782                         break;
3783
3784                       case 'c':
3785                         switch (value)
3786                           {
3787                           case 0:
3788                             func (stream, "eq");
3789                             break;
3790
3791                           case 1:
3792                             func (stream, "vs");
3793                             break;
3794
3795                           case 2:
3796                             func (stream, "ge");
3797                             break;
3798
3799                           case 3:
3800                             func (stream, "gt");
3801                             break;
3802
3803                           default:
3804                             func (stream, "??");
3805                             break;
3806                           }
3807                         break;
3808
3809                       case '`':
3810                         c++;
3811                         if (value == 0)
3812                           func (stream, "%c", *c);
3813                         break;
3814                       case '\'':
3815                         c++;
3816                         if (value == ((1ul << width) - 1))
3817                           func (stream, "%c", *c);
3818                         break;
3819                       case '?':
3820                         func (stream, "%c", c[(1 << width) - (int) value]);
3821                         c += 1 << width;
3822                         break;
3823                       default:
3824                         abort ();
3825                       }
3826                     break;
3827
3828                   case 'y':
3829                   case 'z':
3830                     {
3831                       int single = *c++ == 'y';
3832                       int regno;
3833
3834                       switch (*c)
3835                         {
3836                         case '4': /* Sm pair */
3837                         case '0': /* Sm, Dm */
3838                           regno = given & 0x0000000f;
3839                           if (single)
3840                             {
3841                               regno <<= 1;
3842                               regno += (given >> 5) & 1;
3843                             }
3844                           else
3845                             regno += ((given >> 5) & 1) << 4;
3846                           break;
3847
3848                         case '1': /* Sd, Dd */
3849                           regno = (given >> 12) & 0x0000000f;
3850                           if (single)
3851                             {
3852                               regno <<= 1;
3853                               regno += (given >> 22) & 1;
3854                             }
3855                           else
3856                             regno += ((given >> 22) & 1) << 4;
3857                           break;
3858
3859                         case '2': /* Sn, Dn */
3860                           regno = (given >> 16) & 0x0000000f;
3861                           if (single)
3862                             {
3863                               regno <<= 1;
3864                               regno += (given >> 7) & 1;
3865                             }
3866                           else
3867                             regno += ((given >> 7) & 1) << 4;
3868                           break;
3869
3870                         case '3': /* List */
3871                           func (stream, "{");
3872                           regno = (given >> 12) & 0x0000000f;
3873                           if (single)
3874                             {
3875                               regno <<= 1;
3876                               regno += (given >> 22) & 1;
3877                             }
3878                           else
3879                             regno += ((given >> 22) & 1) << 4;
3880                           break;
3881
3882                         default:
3883                           abort ();
3884                         }
3885
3886                       func (stream, "%c%d", single ? 's' : 'd', regno);
3887
3888                       if (*c == '3')
3889                         {
3890                           int count = given & 0xff;
3891
3892                           if (single == 0)
3893                             count >>= 1;
3894
3895                           if (--count)
3896                             {
3897                               func (stream, "-%c%d",
3898                                     single ? 's' : 'd',
3899                                     regno + count);
3900                             }
3901
3902                           func (stream, "}");
3903                         }
3904                       else if (*c == '4')
3905                         func (stream, ", %c%d", single ? 's' : 'd',
3906                               regno + 1);
3907                     }
3908                     break;
3909
3910                   case 'L':
3911                     switch (given & 0x00400100)
3912                       {
3913                       case 0x00000000: func (stream, "b"); break;
3914                       case 0x00400000: func (stream, "h"); break;
3915                       case 0x00000100: func (stream, "w"); break;
3916                       case 0x00400100: func (stream, "d"); break;
3917                       default:
3918                         break;
3919                       }
3920                     break;
3921
3922                   case 'Z':
3923                     {
3924                       /* given (20, 23) | given (0, 3) */
3925                       value = ((given >> 16) & 0xf0) | (given & 0xf);
3926                       func (stream, "%d", (int) value);
3927                     }
3928                     break;
3929
3930                   case 'l':
3931                     /* This is like the 'A' operator, except that if
3932                        the width field "M" is zero, then the offset is
3933                        *not* multiplied by four.  */
3934                     {
3935                       int offset = given & 0xff;
3936                       int multiplier = (given & 0x00000100) ? 4 : 1;
3937
3938                       func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3939
3940                       if (multiplier > 1)
3941                         {
3942                           value_in_comment = offset * multiplier;
3943                           if (NEGATIVE_BIT_SET)
3944                             value_in_comment = - value_in_comment;
3945                         }
3946
3947                       if (offset)
3948                         {
3949                           if (PRE_BIT_SET)
3950                             func (stream, ", #%s%d]%s",
3951                                   NEGATIVE_BIT_SET ? "-" : "",
3952                                   offset * multiplier,
3953                                   WRITEBACK_BIT_SET ? "!" : "");
3954                           else
3955                             func (stream, "], #%s%d",
3956                                   NEGATIVE_BIT_SET ? "-" : "",
3957                                   offset * multiplier);
3958                         }
3959                       else
3960                         func (stream, "]");
3961                     }
3962                     break;
3963
3964                   case 'r':
3965                     {
3966                       int imm4 = (given >> 4) & 0xf;
3967                       int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3968                       int ubit = ! NEGATIVE_BIT_SET;
3969                       const char *rm = arm_regnames [given & 0xf];
3970                       const char *rn = arm_regnames [(given >> 16) & 0xf];
3971
3972                       switch (puw_bits)
3973                         {
3974                         case 1:
3975                         case 3:
3976                           func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3977                           if (imm4)
3978                             func (stream, ", lsl #%d", imm4);
3979                           break;
3980
3981                         case 4:
3982                         case 5:
3983                         case 6:
3984                         case 7:
3985                           func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3986                           if (imm4 > 0)
3987                             func (stream, ", lsl #%d", imm4);
3988                           func (stream, "]");
3989                           if (puw_bits == 5 || puw_bits == 7)
3990                             func (stream, "!");
3991                           break;
3992
3993                         default:
3994                           func (stream, "INVALID");
3995                         }
3996                     }
3997                     break;
3998
3999                   case 'i':
4000                     {
4001                       long imm5;
4002                       imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4003                       func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
4004                     }
4005                     break;
4006
4007                   default:
4008                     abort ();
4009                   }
4010                 }
4011             }
4012           else
4013             func (stream, "%c", *c);
4014         }
4015
4016       if (value_in_comment > 32 || value_in_comment < -16)
4017         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4018
4019       if (is_unpredictable)
4020         func (stream, UNPREDICTABLE_INSTRUCTION);
4021
4022       return TRUE;
4023     }
4024   return FALSE;
4025 }
4026
4027 /* Decodes and prints ARM addressing modes.  Returns the offset
4028    used in the address, if any, if it is worthwhile printing the
4029    offset as a hexadecimal value in a comment at the end of the
4030    line of disassembly.  */
4031
4032 static signed long
4033 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4034 {
4035   void *stream = info->stream;
4036   fprintf_ftype func = info->fprintf_func;
4037   bfd_vma offset = 0;
4038
4039   if (((given & 0x000f0000) == 0x000f0000)
4040       && ((given & 0x02000000) == 0))
4041     {
4042       offset = given & 0xfff;
4043
4044       func (stream, "[pc");
4045
4046       if (PRE_BIT_SET)
4047         {
4048           /* Pre-indexed.  Elide offset of positive zero when
4049              non-writeback.  */
4050           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4051             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4052
4053           if (NEGATIVE_BIT_SET)
4054             offset = -offset;
4055
4056           offset += pc + 8;
4057
4058           /* Cope with the possibility of write-back
4059              being used.  Probably a very dangerous thing
4060              for the programmer to do, but who are we to
4061              argue ?  */
4062           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
4063         }
4064       else  /* Post indexed.  */
4065         {
4066           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4067
4068           /* Ie ignore the offset.  */
4069           offset = pc + 8;
4070         }
4071
4072       func (stream, "\t; ");
4073       info->print_address_func (offset, info);
4074       offset = 0;
4075     }
4076   else
4077     {
4078       func (stream, "[%s",
4079             arm_regnames[(given >> 16) & 0xf]);
4080
4081       if (PRE_BIT_SET)
4082         {
4083           if ((given & 0x02000000) == 0)
4084             {
4085               /* Elide offset of positive zero when non-writeback.  */
4086               offset = given & 0xfff;
4087               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4088                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4089             }
4090           else
4091             {
4092               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
4093               arm_decode_shift (given, func, stream, TRUE);
4094             }
4095
4096           func (stream, "]%s",
4097                 WRITEBACK_BIT_SET ? "!" : "");
4098         }
4099       else
4100         {
4101           if ((given & 0x02000000) == 0)
4102             {
4103               /* Always show offset.  */
4104               offset = given & 0xfff;
4105               func (stream, "], #%s%d",
4106                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4107             }
4108           else
4109             {
4110               func (stream, "], %s",
4111                     NEGATIVE_BIT_SET ? "-" : "");
4112               arm_decode_shift (given, func, stream, TRUE);
4113             }
4114         }
4115       if (NEGATIVE_BIT_SET)
4116         offset = -offset;
4117     }
4118
4119   return (signed long) offset;
4120 }
4121
4122 /* Print one neon instruction on INFO->STREAM.
4123    Return TRUE if the instuction matched, FALSE if this is not a
4124    recognised neon instruction.  */
4125
4126 static bfd_boolean
4127 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4128 {
4129   const struct opcode32 *insn;
4130   void *stream = info->stream;
4131   fprintf_ftype func = info->fprintf_func;
4132
4133   if (thumb)
4134     {
4135       if ((given & 0xef000000) == 0xef000000)
4136         {
4137           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
4138           unsigned long bit28 = given & (1 << 28);
4139
4140           given &= 0x00ffffff;
4141           if (bit28)
4142             given |= 0xf3000000;
4143           else
4144             given |= 0xf2000000;
4145         }
4146       else if ((given & 0xff000000) == 0xf9000000)
4147         given ^= 0xf9000000 ^ 0xf4000000;
4148       else
4149         return FALSE;
4150     }
4151
4152   for (insn = neon_opcodes; insn->assembler; insn++)
4153     {
4154       if ((given & insn->mask) == insn->value)
4155         {
4156           signed long value_in_comment = 0;
4157           bfd_boolean is_unpredictable = FALSE;
4158           const char *c;
4159
4160           for (c = insn->assembler; *c; c++)
4161             {
4162               if (*c == '%')
4163                 {
4164                   switch (*++c)
4165                     {
4166                     case '%':
4167                       func (stream, "%%");
4168                       break;
4169
4170                     case 'u':
4171                       if (thumb && ifthen_state)
4172                         is_unpredictable = TRUE;
4173
4174                       /* Fall through.  */
4175                     case 'c':
4176                       if (thumb && ifthen_state)
4177                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
4178                       break;
4179
4180                     case 'A':
4181                       {
4182                         static const unsigned char enc[16] =
4183                         {
4184                           0x4, 0x14, /* st4 0,1 */
4185                           0x4, /* st1 2 */
4186                           0x4, /* st2 3 */
4187                           0x3, /* st3 4 */
4188                           0x13, /* st3 5 */
4189                           0x3, /* st1 6 */
4190                           0x1, /* st1 7 */
4191                           0x2, /* st2 8 */
4192                           0x12, /* st2 9 */
4193                           0x2, /* st1 10 */
4194                           0, 0, 0, 0, 0
4195                         };
4196                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4197                         int rn = ((given >> 16) & 0xf);
4198                         int rm = ((given >> 0) & 0xf);
4199                         int align = ((given >> 4) & 0x3);
4200                         int type = ((given >> 8) & 0xf);
4201                         int n = enc[type] & 0xf;
4202                         int stride = (enc[type] >> 4) + 1;
4203                         int ix;
4204
4205                         func (stream, "{");
4206                         if (stride > 1)
4207                           for (ix = 0; ix != n; ix++)
4208                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4209                         else if (n == 1)
4210                           func (stream, "d%d", rd);
4211                         else
4212                           func (stream, "d%d-d%d", rd, rd + n - 1);
4213                         func (stream, "}, [%s", arm_regnames[rn]);
4214                         if (align)
4215                           func (stream, " :%d", 32 << align);
4216                         func (stream, "]");
4217                         if (rm == 0xd)
4218                           func (stream, "!");
4219                         else if (rm != 0xf)
4220                           func (stream, ", %s", arm_regnames[rm]);
4221                       }
4222                       break;
4223
4224                     case 'B':
4225                       {
4226                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4227                         int rn = ((given >> 16) & 0xf);
4228                         int rm = ((given >> 0) & 0xf);
4229                         int idx_align = ((given >> 4) & 0xf);
4230                         int align = 0;
4231                         int size = ((given >> 10) & 0x3);
4232                         int idx = idx_align >> (size + 1);
4233                         int length = ((given >> 8) & 3) + 1;
4234                         int stride = 1;
4235                         int i;
4236
4237                         if (length > 1 && size > 0)
4238                           stride = (idx_align & (1 << size)) ? 2 : 1;
4239
4240                         switch (length)
4241                           {
4242                           case 1:
4243                             {
4244                               int amask = (1 << size) - 1;
4245                               if ((idx_align & (1 << size)) != 0)
4246                                 return FALSE;
4247                               if (size > 0)
4248                                 {
4249                                   if ((idx_align & amask) == amask)
4250                                     align = 8 << size;
4251                                   else if ((idx_align & amask) != 0)
4252                                     return FALSE;
4253                                 }
4254                               }
4255                             break;
4256
4257                           case 2:
4258                             if (size == 2 && (idx_align & 2) != 0)
4259                               return FALSE;
4260                             align = (idx_align & 1) ? 16 << size : 0;
4261                             break;
4262
4263                           case 3:
4264                             if ((size == 2 && (idx_align & 3) != 0)
4265                                 || (idx_align & 1) != 0)
4266                               return FALSE;
4267                             break;
4268
4269                           case 4:
4270                             if (size == 2)
4271                               {
4272                                 if ((idx_align & 3) == 3)
4273                                   return FALSE;
4274                                 align = (idx_align & 3) * 64;
4275                               }
4276                             else
4277                               align = (idx_align & 1) ? 32 << size : 0;
4278                             break;
4279
4280                           default:
4281                             abort ();
4282                           }
4283
4284                         func (stream, "{");
4285                         for (i = 0; i < length; i++)
4286                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4287                             rd + i * stride, idx);
4288                         func (stream, "}, [%s", arm_regnames[rn]);
4289                         if (align)
4290                           func (stream, " :%d", align);
4291                         func (stream, "]");
4292                         if (rm == 0xd)
4293                           func (stream, "!");
4294                         else if (rm != 0xf)
4295                           func (stream, ", %s", arm_regnames[rm]);
4296                       }
4297                       break;
4298
4299                     case 'C':
4300                       {
4301                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4302                         int rn = ((given >> 16) & 0xf);
4303                         int rm = ((given >> 0) & 0xf);
4304                         int align = ((given >> 4) & 0x1);
4305                         int size = ((given >> 6) & 0x3);
4306                         int type = ((given >> 8) & 0x3);
4307                         int n = type + 1;
4308                         int stride = ((given >> 5) & 0x1);
4309                         int ix;
4310
4311                         if (stride && (n == 1))
4312                           n++;
4313                         else
4314                           stride++;
4315
4316                         func (stream, "{");
4317                         if (stride > 1)
4318                           for (ix = 0; ix != n; ix++)
4319                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4320                         else if (n == 1)
4321                           func (stream, "d%d[]", rd);
4322                         else
4323                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4324                         func (stream, "}, [%s", arm_regnames[rn]);
4325                         if (align)
4326                           {
4327                             align = (8 * (type + 1)) << size;
4328                             if (type == 3)
4329                               align = (size > 1) ? align >> 1 : align;
4330                             if (type == 2 || (type == 0 && !size))
4331                               func (stream, " :<bad align %d>", align);
4332                             else
4333                               func (stream, " :%d", align);
4334                           }
4335                         func (stream, "]");
4336                         if (rm == 0xd)
4337                           func (stream, "!");
4338                         else if (rm != 0xf)
4339                           func (stream, ", %s", arm_regnames[rm]);
4340                       }
4341                       break;
4342
4343                     case 'D':
4344                       {
4345                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4346                         int size = (given >> 20) & 3;
4347                         int reg = raw_reg & ((4 << size) - 1);
4348                         int ix = raw_reg >> size >> 2;
4349
4350                         func (stream, "d%d[%d]", reg, ix);
4351                       }
4352                       break;
4353
4354                     case 'E':
4355                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
4356                       {
4357                         int bits = 0;
4358                         int cmode = (given >> 8) & 0xf;
4359                         int op = (given >> 5) & 0x1;
4360                         unsigned long value = 0, hival = 0;
4361                         unsigned shift;
4362                         int size = 0;
4363                         int isfloat = 0;
4364
4365                         bits |= ((given >> 24) & 1) << 7;
4366                         bits |= ((given >> 16) & 7) << 4;
4367                         bits |= ((given >> 0) & 15) << 0;
4368
4369                         if (cmode < 8)
4370                           {
4371                             shift = (cmode >> 1) & 3;
4372                             value = (unsigned long) bits << (8 * shift);
4373                             size = 32;
4374                           }
4375                         else if (cmode < 12)
4376                           {
4377                             shift = (cmode >> 1) & 1;
4378                             value = (unsigned long) bits << (8 * shift);
4379                             size = 16;
4380                           }
4381                         else if (cmode < 14)
4382                           {
4383                             shift = (cmode & 1) + 1;
4384                             value = (unsigned long) bits << (8 * shift);
4385                             value |= (1ul << (8 * shift)) - 1;
4386                             size = 32;
4387                           }
4388                         else if (cmode == 14)
4389                           {
4390                             if (op)
4391                               {
4392                                 /* Bit replication into bytes.  */
4393                                 int ix;
4394                                 unsigned long mask;
4395
4396                                 value = 0;
4397                                 hival = 0;
4398                                 for (ix = 7; ix >= 0; ix--)
4399                                   {
4400                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
4401                                     if (ix <= 3)
4402                                       value = (value << 8) | mask;
4403                                     else
4404                                       hival = (hival << 8) | mask;
4405                                   }
4406                                 size = 64;
4407                               }
4408                             else
4409                               {
4410                                 /* Byte replication.  */
4411                                 value = (unsigned long) bits;
4412                                 size = 8;
4413                               }
4414                           }
4415                         else if (!op)
4416                           {
4417                             /* Floating point encoding.  */
4418                             int tmp;
4419
4420                             value = (unsigned long)  (bits & 0x7f) << 19;
4421                             value |= (unsigned long) (bits & 0x80) << 24;
4422                             tmp = bits & 0x40 ? 0x3c : 0x40;
4423                             value |= (unsigned long) tmp << 24;
4424                             size = 32;
4425                             isfloat = 1;
4426                           }
4427                         else
4428                           {
4429                             func (stream, "<illegal constant %.8x:%x:%x>",
4430                                   bits, cmode, op);
4431                             size = 32;
4432                             break;
4433                           }
4434                         switch (size)
4435                           {
4436                           case 8:
4437                             func (stream, "#%ld\t; 0x%.2lx", value, value);
4438                             break;
4439
4440                           case 16:
4441                             func (stream, "#%ld\t; 0x%.4lx", value, value);
4442                             break;
4443
4444                           case 32:
4445                             if (isfloat)
4446                               {
4447                                 unsigned char valbytes[4];
4448                                 double fvalue;
4449
4450                                 /* Do this a byte at a time so we don't have to
4451                                    worry about the host's endianness.  */
4452                                 valbytes[0] = value & 0xff;
4453                                 valbytes[1] = (value >> 8) & 0xff;
4454                                 valbytes[2] = (value >> 16) & 0xff;
4455                                 valbytes[3] = (value >> 24) & 0xff;
4456
4457                                 floatformat_to_double
4458                                   (& floatformat_ieee_single_little, valbytes,
4459                                   & fvalue);
4460
4461                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4462                                       value);
4463                               }
4464                             else
4465                               func (stream, "#%ld\t; 0x%.8lx",
4466                                     (long) (((value & 0x80000000L) != 0)
4467                                             ? value | ~0xffffffffL : value),
4468                                     value);
4469                             break;
4470
4471                           case 64:
4472                             func (stream, "#0x%.8lx%.8lx", hival, value);
4473                             break;
4474
4475                           default:
4476                             abort ();
4477                           }
4478                       }
4479                       break;
4480
4481                     case 'F':
4482                       {
4483                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4484                         int num = (given >> 8) & 0x3;
4485
4486                         if (!num)
4487                           func (stream, "{d%d}", regno);
4488                         else if (num + regno >= 32)
4489                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4490                         else
4491                           func (stream, "{d%d-d%d}", regno, regno + num);
4492                       }
4493                       break;
4494
4495
4496                     case '0': case '1': case '2': case '3': case '4':
4497                     case '5': case '6': case '7': case '8': case '9':
4498                       {
4499                         int width;
4500                         unsigned long value;
4501
4502                         c = arm_decode_bitfield (c, given, &value, &width);
4503
4504                         switch (*c)
4505                           {
4506                           case 'r':
4507                             func (stream, "%s", arm_regnames[value]);
4508                             break;
4509                           case 'd':
4510                             func (stream, "%ld", value);
4511                             value_in_comment = value;
4512                             break;
4513                           case 'e':
4514                             func (stream, "%ld", (1ul << width) - value);
4515                             break;
4516
4517                           case 'S':
4518                           case 'T':
4519                           case 'U':
4520                             /* Various width encodings.  */
4521                             {
4522                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4523                               int limit;
4524                               unsigned low, high;
4525
4526                               c++;
4527                               if (*c >= '0' && *c <= '9')
4528                                 limit = *c - '0';
4529                               else if (*c >= 'a' && *c <= 'f')
4530                                 limit = *c - 'a' + 10;
4531                               else
4532                                 abort ();
4533                               low = limit >> 2;
4534                               high = limit & 3;
4535
4536                               if (value < low || value > high)
4537                                 func (stream, "<illegal width %d>", base << value);
4538                               else
4539                                 func (stream, "%d", base << value);
4540                             }
4541                             break;
4542                           case 'R':
4543                             if (given & (1 << 6))
4544                               goto Q;
4545                             /* FALLTHROUGH */
4546                           case 'D':
4547                             func (stream, "d%ld", value);
4548                             break;
4549                           case 'Q':
4550                           Q:
4551                             if (value & 1)
4552                               func (stream, "<illegal reg q%ld.5>", value >> 1);
4553                             else
4554                               func (stream, "q%ld", value >> 1);
4555                             break;
4556
4557                           case '`':
4558                             c++;
4559                             if (value == 0)
4560                               func (stream, "%c", *c);
4561                             break;
4562                           case '\'':
4563                             c++;
4564                             if (value == ((1ul << width) - 1))
4565                               func (stream, "%c", *c);
4566                             break;
4567                           case '?':
4568                             func (stream, "%c", c[(1 << width) - (int) value]);
4569                             c += 1 << width;
4570                             break;
4571                           default:
4572                             abort ();
4573                           }
4574                         break;
4575
4576                       default:
4577                         abort ();
4578                       }
4579                     }
4580                 }
4581               else
4582                 func (stream, "%c", *c);
4583             }
4584
4585           if (value_in_comment > 32 || value_in_comment < -16)
4586             func (stream, "\t; 0x%lx", value_in_comment);
4587
4588           if (is_unpredictable)
4589             func (stream, UNPREDICTABLE_INSTRUCTION);
4590
4591           return TRUE;
4592         }
4593     }
4594   return FALSE;
4595 }
4596
4597 /* Return the name of a v7A special register.  */
4598
4599 static const char *
4600 banked_regname (unsigned reg)
4601 {
4602   switch (reg)
4603     {
4604       case 15: return "CPSR";
4605       case 32: return "R8_usr";
4606       case 33: return "R9_usr";
4607       case 34: return "R10_usr";
4608       case 35: return "R11_usr";
4609       case 36: return "R12_usr";
4610       case 37: return "SP_usr";
4611       case 38: return "LR_usr";
4612       case 40: return "R8_fiq";
4613       case 41: return "R9_fiq";
4614       case 42: return "R10_fiq";
4615       case 43: return "R11_fiq";
4616       case 44: return "R12_fiq";
4617       case 45: return "SP_fiq";
4618       case 46: return "LR_fiq";
4619       case 48: return "LR_irq";
4620       case 49: return "SP_irq";
4621       case 50: return "LR_svc";
4622       case 51: return "SP_svc";
4623       case 52: return "LR_abt";
4624       case 53: return "SP_abt";
4625       case 54: return "LR_und";
4626       case 55: return "SP_und";
4627       case 60: return "LR_mon";
4628       case 61: return "SP_mon";
4629       case 62: return "ELR_hyp";
4630       case 63: return "SP_hyp";
4631       case 79: return "SPSR";
4632       case 110: return "SPSR_fiq";
4633       case 112: return "SPSR_irq";
4634       case 114: return "SPSR_svc";
4635       case 116: return "SPSR_abt";
4636       case 118: return "SPSR_und";
4637       case 124: return "SPSR_mon";
4638       case 126: return "SPSR_hyp";
4639       default: return NULL;
4640     }
4641 }
4642
4643 /* Return the name of the DMB/DSB option.  */
4644 static const char *
4645 data_barrier_option (unsigned option)
4646 {
4647   switch (option & 0xf)
4648     {
4649     case 0xf: return "sy";
4650     case 0xe: return "st";
4651     case 0xd: return "ld";
4652     case 0xb: return "ish";
4653     case 0xa: return "ishst";
4654     case 0x9: return "ishld";
4655     case 0x7: return "un";
4656     case 0x6: return "unst";
4657     case 0x5: return "nshld";
4658     case 0x3: return "osh";
4659     case 0x2: return "oshst";
4660     case 0x1: return "oshld";
4661     default:  return NULL;
4662     }
4663 }
4664
4665 /* Print one ARM instruction from PC on INFO->STREAM.  */
4666
4667 static void
4668 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4669 {
4670   const struct opcode32 *insn;
4671   void *stream = info->stream;
4672   fprintf_ftype func = info->fprintf_func;
4673   struct arm_private_data *private_data = info->private_data;
4674
4675   if (print_insn_coprocessor (pc, info, given, FALSE))
4676     return;
4677
4678   if (print_insn_neon (info, given, FALSE))
4679     return;
4680
4681   for (insn = arm_opcodes; insn->assembler; insn++)
4682     {
4683       if ((given & insn->mask) != insn->value)
4684         continue;
4685
4686       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4687         continue;
4688
4689       /* Special case: an instruction with all bits set in the condition field
4690          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4691          or by the catchall at the end of the table.  */
4692       if ((given & 0xF0000000) != 0xF0000000
4693           || (insn->mask & 0xF0000000) == 0xF0000000
4694           || (insn->mask == 0 && insn->value == 0))
4695         {
4696           unsigned long u_reg = 16;
4697           unsigned long U_reg = 16;
4698           bfd_boolean is_unpredictable = FALSE;
4699           signed long value_in_comment = 0;
4700           const char *c;
4701
4702           for (c = insn->assembler; *c; c++)
4703             {
4704               if (*c == '%')
4705                 {
4706                   bfd_boolean allow_unpredictable = FALSE;
4707
4708                   switch (*++c)
4709                     {
4710                     case '%':
4711                       func (stream, "%%");
4712                       break;
4713
4714                     case 'a':
4715                       value_in_comment = print_arm_address (pc, info, given);
4716                       break;
4717
4718                     case 'P':
4719                       /* Set P address bit and use normal address
4720                          printing routine.  */
4721                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4722                       break;
4723
4724                     case 'S':
4725                       allow_unpredictable = TRUE;
4726                       /* Fall through.  */
4727                     case 's':
4728                       if ((given & 0x004f0000) == 0x004f0000)
4729                         {
4730                           /* PC relative with immediate offset.  */
4731                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4732
4733                           if (PRE_BIT_SET)
4734                             {
4735                               /* Elide positive zero offset.  */
4736                               if (offset || NEGATIVE_BIT_SET)
4737                                 func (stream, "[pc, #%s%d]\t; ",
4738                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4739                               else
4740                                 func (stream, "[pc]\t; ");
4741                               if (NEGATIVE_BIT_SET)
4742                                 offset = -offset;
4743                               info->print_address_func (offset + pc + 8, info);
4744                             }
4745                           else
4746                             {
4747                               /* Always show the offset.  */
4748                               func (stream, "[pc], #%s%d",
4749                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4750                               if (! allow_unpredictable)
4751                                 is_unpredictable = TRUE;
4752                             }
4753                         }
4754                       else
4755                         {
4756                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4757
4758                           func (stream, "[%s",
4759                                 arm_regnames[(given >> 16) & 0xf]);
4760
4761                           if (PRE_BIT_SET)
4762                             {
4763                               if (IMMEDIATE_BIT_SET)
4764                                 {
4765                                   /* Elide offset for non-writeback
4766                                      positive zero.  */
4767                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4768                                       || offset)
4769                                     func (stream, ", #%s%d",
4770                                           NEGATIVE_BIT_SET ? "-" : "", offset);
4771
4772                                   if (NEGATIVE_BIT_SET)
4773                                     offset = -offset;
4774
4775                                   value_in_comment = offset;
4776                                 }
4777                               else
4778                                 {
4779                                   /* Register Offset or Register Pre-Indexed.  */
4780                                   func (stream, ", %s%s",
4781                                         NEGATIVE_BIT_SET ? "-" : "",
4782                                         arm_regnames[given & 0xf]);
4783
4784                                   /* Writing back to the register that is the source/
4785                                      destination of the load/store is unpredictable.  */
4786                                   if (! allow_unpredictable
4787                                       && WRITEBACK_BIT_SET
4788                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
4789                                     is_unpredictable = TRUE;
4790                                 }
4791
4792                               func (stream, "]%s",
4793                                     WRITEBACK_BIT_SET ? "!" : "");
4794                             }
4795                           else
4796                             {
4797                               if (IMMEDIATE_BIT_SET)
4798                                 {
4799                                   /* Immediate Post-indexed.  */
4800                                   /* PR 10924: Offset must be printed, even if it is zero.  */
4801                                   func (stream, "], #%s%d",
4802                                         NEGATIVE_BIT_SET ? "-" : "", offset);
4803                                   if (NEGATIVE_BIT_SET)
4804                                     offset = -offset;
4805                                   value_in_comment = offset;
4806                                 }
4807                               else
4808                                 {
4809                                   /* Register Post-indexed.  */
4810                                   func (stream, "], %s%s",
4811                                         NEGATIVE_BIT_SET ? "-" : "",
4812                                         arm_regnames[given & 0xf]);
4813
4814                                   /* Writing back to the register that is the source/
4815                                      destination of the load/store is unpredictable.  */
4816                                   if (! allow_unpredictable
4817                                       && (given & 0xf) == ((given >> 12) & 0xf))
4818                                     is_unpredictable = TRUE;
4819                                 }
4820
4821                               if (! allow_unpredictable)
4822                                 {
4823                                   /* Writeback is automatically implied by post- addressing.
4824                                      Setting the W bit is unnecessary and ARM specify it as
4825                                      being unpredictable.  */
4826                                   if (WRITEBACK_BIT_SET
4827                                       /* Specifying the PC register as the post-indexed
4828                                          registers is also unpredictable.  */
4829                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4830                                     is_unpredictable = TRUE;
4831                                 }
4832                             }
4833                         }
4834                       break;
4835
4836                     case 'b':
4837                       {
4838                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4839                         info->print_address_func (disp * 4 + pc + 8, info);
4840                       }
4841                       break;
4842
4843                     case 'c':
4844                       if (((given >> 28) & 0xf) != 0xe)
4845                         func (stream, "%s",
4846                               arm_conditional [(given >> 28) & 0xf]);
4847                       break;
4848
4849                     case 'm':
4850                       {
4851                         int started = 0;
4852                         int reg;
4853
4854                         func (stream, "{");
4855                         for (reg = 0; reg < 16; reg++)
4856                           if ((given & (1 << reg)) != 0)
4857                             {
4858                               if (started)
4859                                 func (stream, ", ");
4860                               started = 1;
4861                               func (stream, "%s", arm_regnames[reg]);
4862                             }
4863                         func (stream, "}");
4864                         if (! started)
4865                           is_unpredictable = TRUE;
4866                       }
4867                       break;
4868
4869                     case 'q':
4870                       arm_decode_shift (given, func, stream, FALSE);
4871                       break;
4872
4873                     case 'o':
4874                       if ((given & 0x02000000) != 0)
4875                         {
4876                           unsigned int rotate = (given & 0xf00) >> 7;
4877                           unsigned int immed = (given & 0xff);
4878                           unsigned int a, i;
4879
4880                           a = (((immed << (32 - rotate))
4881                                 | (immed >> rotate)) & 0xffffffff);
4882                           /* If there is another encoding with smaller rotate,
4883                              the rotate should be specified directly.  */
4884                           for (i = 0; i < 32; i += 2)
4885                             if ((a << i | a >> (32 - i)) <= 0xff)
4886                               break;
4887
4888                           if (i != rotate)
4889                             func (stream, "#%d, %d", immed, rotate);
4890                           else
4891                             func (stream, "#%d", a);
4892                           value_in_comment = a;
4893                         }
4894                       else
4895                         arm_decode_shift (given, func, stream, TRUE);
4896                       break;
4897
4898                     case 'p':
4899                       if ((given & 0x0000f000) == 0x0000f000)
4900                         {
4901                           arm_feature_set arm_ext_v6 =
4902                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4903
4904                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4905                              mechanism for setting PSR flag bits.  They are
4906                              obsolete in V6 onwards.  */
4907                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4908                                                      arm_ext_v6))
4909                             func (stream, "p");
4910                           else
4911                             is_unpredictable = TRUE;
4912                         }
4913                       break;
4914
4915                     case 't':
4916                       if ((given & 0x01200000) == 0x00200000)
4917                         func (stream, "t");
4918                       break;
4919
4920                     case 'A':
4921                       {
4922                         int offset = given & 0xff;
4923
4924                         value_in_comment = offset * 4;
4925                         if (NEGATIVE_BIT_SET)
4926                           value_in_comment = - value_in_comment;
4927
4928                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4929
4930                         if (PRE_BIT_SET)
4931                           {
4932                             if (offset)
4933                               func (stream, ", #%d]%s",
4934                                     (int) value_in_comment,
4935                                     WRITEBACK_BIT_SET ? "!" : "");
4936                             else
4937                               func (stream, "]");
4938                           }
4939                         else
4940                           {
4941                             func (stream, "]");
4942
4943                             if (WRITEBACK_BIT_SET)
4944                               {
4945                                 if (offset)
4946                                   func (stream, ", #%d", (int) value_in_comment);
4947                               }
4948                             else
4949                               {
4950                                 func (stream, ", {%d}", (int) offset);
4951                                 value_in_comment = offset;
4952                               }
4953                           }
4954                       }
4955                       break;
4956
4957                     case 'B':
4958                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
4959                       {
4960                         bfd_vma address;
4961                         bfd_vma offset = 0;
4962
4963                         if (! NEGATIVE_BIT_SET)
4964                           /* Is signed, hi bits should be ones.  */
4965                           offset = (-1) ^ 0x00ffffff;
4966
4967                         /* Offset is (SignExtend(offset field)<<2).  */
4968                         offset += given & 0x00ffffff;
4969                         offset <<= 2;
4970                         address = offset + pc + 8;
4971
4972                         if (given & 0x01000000)
4973                           /* H bit allows addressing to 2-byte boundaries.  */
4974                           address += 2;
4975
4976                         info->print_address_func (address, info);
4977                       }
4978                       break;
4979
4980                     case 'C':
4981                       if ((given & 0x02000200) == 0x200)
4982                         {
4983                           const char * name;
4984                           unsigned sysm = (given & 0x004f0000) >> 16;
4985
4986                           sysm |= (given & 0x300) >> 4;
4987                           name = banked_regname (sysm);
4988
4989                           if (name != NULL)
4990                             func (stream, "%s", name);
4991                           else
4992                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4993                         }
4994                       else
4995                         {
4996                           func (stream, "%cPSR_",
4997                                 (given & 0x00400000) ? 'S' : 'C');
4998                           if (given & 0x80000)
4999                             func (stream, "f");
5000                           if (given & 0x40000)
5001                             func (stream, "s");
5002                           if (given & 0x20000)
5003                             func (stream, "x");
5004                           if (given & 0x10000)
5005                             func (stream, "c");
5006                         }
5007                       break;
5008
5009                     case 'U':
5010                       if ((given & 0xf0) == 0x60)
5011                         {
5012                           switch (given & 0xf)
5013                             {
5014                             case 0xf: func (stream, "sy"); break;
5015                             default:
5016                               func (stream, "#%d", (int) given & 0xf);
5017                               break;
5018                             }
5019                         }
5020                       else
5021                         {
5022                           const char * opt = data_barrier_option (given & 0xf);
5023                           if (opt != NULL)
5024                             func (stream, "%s", opt);
5025                           else
5026                               func (stream, "#%d", (int) given & 0xf);
5027                         }
5028                       break;
5029
5030                     case '0': case '1': case '2': case '3': case '4':
5031                     case '5': case '6': case '7': case '8': case '9':
5032                       {
5033                         int width;
5034                         unsigned long value;
5035
5036                         c = arm_decode_bitfield (c, given, &value, &width);
5037
5038                         switch (*c)
5039                           {
5040                           case 'R':
5041                             if (value == 15)
5042                               is_unpredictable = TRUE;
5043                             /* Fall through.  */
5044                           case 'r':
5045                           case 'T':
5046                             /* We want register + 1 when decoding T.  */
5047                             if (*c == 'T')
5048                               ++value;
5049
5050                             if (c[1] == 'u')
5051                               {
5052                                 /* Eat the 'u' character.  */
5053                                 ++ c;
5054
5055                                 if (u_reg == value)
5056                                   is_unpredictable = TRUE;
5057                                 u_reg = value;
5058                               }
5059                             if (c[1] == 'U')
5060                               {
5061                                 /* Eat the 'U' character.  */
5062                                 ++ c;
5063
5064                                 if (U_reg == value)
5065                                   is_unpredictable = TRUE;
5066                                 U_reg = value;
5067                               }
5068                             func (stream, "%s", arm_regnames[value]);
5069                             break;
5070                           case 'd':
5071                             func (stream, "%ld", value);
5072                             value_in_comment = value;
5073                             break;
5074                           case 'b':
5075                             func (stream, "%ld", value * 8);
5076                             value_in_comment = value * 8;
5077                             break;
5078                           case 'W':
5079                             func (stream, "%ld", value + 1);
5080                             value_in_comment = value + 1;
5081                             break;
5082                           case 'x':
5083                             func (stream, "0x%08lx", value);
5084
5085                             /* Some SWI instructions have special
5086                                meanings.  */
5087                             if ((given & 0x0fffffff) == 0x0FF00000)
5088                               func (stream, "\t; IMB");
5089                             else if ((given & 0x0fffffff) == 0x0FF00001)
5090                               func (stream, "\t; IMBRange");
5091                             break;
5092                           case 'X':
5093                             func (stream, "%01lx", value & 0xf);
5094                             value_in_comment = value;
5095                             break;
5096                           case '`':
5097                             c++;
5098                             if (value == 0)
5099                               func (stream, "%c", *c);
5100                             break;
5101                           case '\'':
5102                             c++;
5103                             if (value == ((1ul << width) - 1))
5104                               func (stream, "%c", *c);
5105                             break;
5106                           case '?':
5107                             func (stream, "%c", c[(1 << width) - (int) value]);
5108                             c += 1 << width;
5109                             break;
5110                           default:
5111                             abort ();
5112                           }
5113                         break;
5114
5115                       case 'e':
5116                         {
5117                           int imm;
5118
5119                           imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5120                           func (stream, "%d", imm);
5121                           value_in_comment = imm;
5122                         }
5123                         break;
5124
5125                       case 'E':
5126                         /* LSB and WIDTH fields of BFI or BFC.  The machine-
5127                            language instruction encodes LSB and MSB.  */
5128                         {
5129                           long msb = (given & 0x001f0000) >> 16;
5130                           long lsb = (given & 0x00000f80) >> 7;
5131                           long w = msb - lsb + 1;
5132
5133                           if (w > 0)
5134                             func (stream, "#%lu, #%lu", lsb, w);
5135                           else
5136                             func (stream, "(invalid: %lu:%lu)", lsb, msb);
5137                         }
5138                         break;
5139
5140                       case 'R':
5141                         /* Get the PSR/banked register name.  */
5142                         {
5143                           const char * name;
5144                           unsigned sysm = (given & 0x004f0000) >> 16;
5145
5146                           sysm |= (given & 0x300) >> 4;
5147                           name = banked_regname (sysm);
5148
5149                           if (name != NULL)
5150                             func (stream, "%s", name);
5151                           else
5152                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5153                         }
5154                         break;
5155
5156                       case 'V':
5157                         /* 16-bit unsigned immediate from a MOVT or MOVW
5158                            instruction, encoded in bits 0:11 and 15:19.  */
5159                         {
5160                           long hi = (given & 0x000f0000) >> 4;
5161                           long lo = (given & 0x00000fff);
5162                           long imm16 = hi | lo;
5163
5164                           func (stream, "#%lu", imm16);
5165                           value_in_comment = imm16;
5166                         }
5167                         break;
5168
5169                       default:
5170                         abort ();
5171                       }
5172                     }
5173                 }
5174               else
5175                 func (stream, "%c", *c);
5176             }
5177
5178           if (value_in_comment > 32 || value_in_comment < -16)
5179             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5180
5181           if (is_unpredictable)
5182             func (stream, UNPREDICTABLE_INSTRUCTION);
5183
5184           return;
5185         }
5186     }
5187   abort ();
5188 }
5189
5190 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
5191
5192 static void
5193 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
5194 {
5195   const struct opcode16 *insn;
5196   void *stream = info->stream;
5197   fprintf_ftype func = info->fprintf_func;
5198
5199   for (insn = thumb_opcodes; insn->assembler; insn++)
5200     if ((given & insn->mask) == insn->value)
5201       {
5202         signed long value_in_comment = 0;
5203         const char *c = insn->assembler;
5204
5205         for (; *c; c++)
5206           {
5207             int domaskpc = 0;
5208             int domasklr = 0;
5209
5210             if (*c != '%')
5211               {
5212                 func (stream, "%c", *c);
5213                 continue;
5214               }
5215
5216             switch (*++c)
5217               {
5218               case '%':
5219                 func (stream, "%%");
5220                 break;
5221
5222               case 'c':
5223                 if (ifthen_state)
5224                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5225                 break;
5226
5227               case 'C':
5228                 if (ifthen_state)
5229                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5230                 else
5231                   func (stream, "s");
5232                 break;
5233
5234               case 'I':
5235                 {
5236                   unsigned int tmp;
5237
5238                   ifthen_next_state = given & 0xff;
5239                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5240                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5241                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5242                 }
5243                 break;
5244
5245               case 'x':
5246                 if (ifthen_next_state)
5247                   func (stream, "\t; unpredictable branch in IT block\n");
5248                 break;
5249
5250               case 'X':
5251                 if (ifthen_state)
5252                   func (stream, "\t; unpredictable <IT:%s>",
5253                         arm_conditional[IFTHEN_COND]);
5254                 break;
5255
5256               case 'S':
5257                 {
5258                   long reg;
5259
5260                   reg = (given >> 3) & 0x7;
5261                   if (given & (1 << 6))
5262                     reg += 8;
5263
5264                   func (stream, "%s", arm_regnames[reg]);
5265                 }
5266                 break;
5267
5268               case 'D':
5269                 {
5270                   long reg;
5271
5272                   reg = given & 0x7;
5273                   if (given & (1 << 7))
5274                     reg += 8;
5275
5276                   func (stream, "%s", arm_regnames[reg]);
5277                 }
5278                 break;
5279
5280               case 'N':
5281                 if (given & (1 << 8))
5282                   domasklr = 1;
5283                 /* Fall through.  */
5284               case 'O':
5285                 if (*c == 'O' && (given & (1 << 8)))
5286                   domaskpc = 1;
5287                 /* Fall through.  */
5288               case 'M':
5289                 {
5290                   int started = 0;
5291                   int reg;
5292
5293                   func (stream, "{");
5294
5295                   /* It would be nice if we could spot
5296                      ranges, and generate the rS-rE format: */
5297                   for (reg = 0; (reg < 8); reg++)
5298                     if ((given & (1 << reg)) != 0)
5299                       {
5300                         if (started)
5301                           func (stream, ", ");
5302                         started = 1;
5303                         func (stream, "%s", arm_regnames[reg]);
5304                       }
5305
5306                   if (domasklr)
5307                     {
5308                       if (started)
5309                         func (stream, ", ");
5310                       started = 1;
5311                       func (stream, "%s", arm_regnames[14] /* "lr" */);
5312                     }
5313
5314                   if (domaskpc)
5315                     {
5316                       if (started)
5317                         func (stream, ", ");
5318                       func (stream, "%s", arm_regnames[15] /* "pc" */);
5319                     }
5320
5321                   func (stream, "}");
5322                 }
5323                 break;
5324
5325               case 'W':
5326                 /* Print writeback indicator for a LDMIA.  We are doing a
5327                    writeback if the base register is not in the register
5328                    mask.  */
5329                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5330                   func (stream, "!");
5331                 break;
5332
5333               case 'b':
5334                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
5335                 {
5336                   bfd_vma address = (pc + 4
5337                                      + ((given & 0x00f8) >> 2)
5338                                      + ((given & 0x0200) >> 3));
5339                   info->print_address_func (address, info);
5340                 }
5341                 break;
5342
5343               case 's':
5344                 /* Right shift immediate -- bits 6..10; 1-31 print
5345                    as themselves, 0 prints as 32.  */
5346                 {
5347                   long imm = (given & 0x07c0) >> 6;
5348                   if (imm == 0)
5349                     imm = 32;
5350                   func (stream, "#%ld", imm);
5351                 }
5352                 break;
5353
5354               case '0': case '1': case '2': case '3': case '4':
5355               case '5': case '6': case '7': case '8': case '9':
5356                 {
5357                   int bitstart = *c++ - '0';
5358                   int bitend = 0;
5359
5360                   while (*c >= '0' && *c <= '9')
5361                     bitstart = (bitstart * 10) + *c++ - '0';
5362
5363                   switch (*c)
5364                     {
5365                     case '-':
5366                       {
5367                         bfd_vma reg;
5368
5369                         c++;
5370                         while (*c >= '0' && *c <= '9')
5371                           bitend = (bitend * 10) + *c++ - '0';
5372                         if (!bitend)
5373                           abort ();
5374                         reg = given >> bitstart;
5375                         reg &= (2 << (bitend - bitstart)) - 1;
5376
5377                         switch (*c)
5378                           {
5379                           case 'r':
5380                             func (stream, "%s", arm_regnames[reg]);
5381                             break;
5382
5383                           case 'd':
5384                             func (stream, "%ld", (long) reg);
5385                             value_in_comment = reg;
5386                             break;
5387
5388                           case 'H':
5389                             func (stream, "%ld", (long) (reg << 1));
5390                             value_in_comment = reg << 1;
5391                             break;
5392
5393                           case 'W':
5394                             func (stream, "%ld", (long) (reg << 2));
5395                             value_in_comment = reg << 2;
5396                             break;
5397
5398                           case 'a':
5399                             /* PC-relative address -- the bottom two
5400                                bits of the address are dropped
5401                                before the calculation.  */
5402                             info->print_address_func
5403                               (((pc + 4) & ~3) + (reg << 2), info);
5404                             value_in_comment = 0;
5405                             break;
5406
5407                           case 'x':
5408                             func (stream, "0x%04lx", (long) reg);
5409                             break;
5410
5411                           case 'B':
5412                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5413                             info->print_address_func (reg * 2 + pc + 4, info);
5414                             value_in_comment = 0;
5415                             break;
5416
5417                           case 'c':
5418                             func (stream, "%s", arm_conditional [reg]);
5419                             break;
5420
5421                           default:
5422                             abort ();
5423                           }
5424                       }
5425                       break;
5426
5427                     case '\'':
5428                       c++;
5429                       if ((given & (1 << bitstart)) != 0)
5430                         func (stream, "%c", *c);
5431                       break;
5432
5433                     case '?':
5434                       ++c;
5435                       if ((given & (1 << bitstart)) != 0)
5436                         func (stream, "%c", *c++);
5437                       else
5438                         func (stream, "%c", *++c);
5439                       break;
5440
5441                     default:
5442                       abort ();
5443                     }
5444                 }
5445                 break;
5446
5447               default:
5448                 abort ();
5449               }
5450           }
5451
5452         if (value_in_comment > 32 || value_in_comment < -16)
5453           func (stream, "\t; 0x%lx", value_in_comment);
5454         return;
5455       }
5456
5457   /* No match.  */
5458   abort ();
5459 }
5460
5461 /* Return the name of an V7M special register.  */
5462
5463 static const char *
5464 psr_name (int regno)
5465 {
5466   switch (regno)
5467     {
5468     case 0x0: return "APSR";
5469     case 0x1: return "IAPSR";
5470     case 0x2: return "EAPSR";
5471     case 0x3: return "PSR";
5472     case 0x5: return "IPSR";
5473     case 0x6: return "EPSR";
5474     case 0x7: return "IEPSR";
5475     case 0x8: return "MSP";
5476     case 0x9: return "PSP";
5477     case 0xa: return "MSPLIM";
5478     case 0xb: return "PSPLIM";
5479     case 0x10: return "PRIMASK";
5480     case 0x11: return "BASEPRI";
5481     case 0x12: return "BASEPRI_MAX";
5482     case 0x13: return "FAULTMASK";
5483     case 0x14: return "CONTROL";
5484     case 0x88: return "MSP_NS";
5485     case 0x89: return "PSP_NS";
5486     case 0x8a: return "MSPLIM_NS";
5487     case 0x8b: return "PSPLIM_NS";
5488     case 0x90: return "PRIMASK_NS";
5489     case 0x91: return "BASEPRI_NS";
5490     case 0x93: return "FAULTMASK_NS";
5491     case 0x94: return "CONTROL_NS";
5492     case 0x98: return "SP_NS";
5493     default: return "<unknown>";
5494     }
5495 }
5496
5497 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
5498
5499 static void
5500 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5501 {
5502   const struct opcode32 *insn;
5503   void *stream = info->stream;
5504   fprintf_ftype func = info->fprintf_func;
5505
5506   if (print_insn_coprocessor (pc, info, given, TRUE))
5507     return;
5508
5509   if (print_insn_neon (info, given, TRUE))
5510     return;
5511
5512   for (insn = thumb32_opcodes; insn->assembler; insn++)
5513     if ((given & insn->mask) == insn->value)
5514       {
5515         bfd_boolean is_unpredictable = FALSE;
5516         signed long value_in_comment = 0;
5517         const char *c = insn->assembler;
5518
5519         for (; *c; c++)
5520           {
5521             if (*c != '%')
5522               {
5523                 func (stream, "%c", *c);
5524                 continue;
5525               }
5526
5527             switch (*++c)
5528               {
5529               case '%':
5530                 func (stream, "%%");
5531                 break;
5532
5533               case 'c':
5534                 if (ifthen_state)
5535                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5536                 break;
5537
5538               case 'x':
5539                 if (ifthen_next_state)
5540                   func (stream, "\t; unpredictable branch in IT block\n");
5541                 break;
5542
5543               case 'X':
5544                 if (ifthen_state)
5545                   func (stream, "\t; unpredictable <IT:%s>",
5546                         arm_conditional[IFTHEN_COND]);
5547                 break;
5548
5549               case 'I':
5550                 {
5551                   unsigned int imm12 = 0;
5552
5553                   imm12 |= (given & 0x000000ffu);
5554                   imm12 |= (given & 0x00007000u) >> 4;
5555                   imm12 |= (given & 0x04000000u) >> 15;
5556                   func (stream, "#%u", imm12);
5557                   value_in_comment = imm12;
5558                 }
5559                 break;
5560
5561               case 'M':
5562                 {
5563                   unsigned int bits = 0, imm, imm8, mod;
5564
5565                   bits |= (given & 0x000000ffu);
5566                   bits |= (given & 0x00007000u) >> 4;
5567                   bits |= (given & 0x04000000u) >> 15;
5568                   imm8 = (bits & 0x0ff);
5569                   mod = (bits & 0xf00) >> 8;
5570                   switch (mod)
5571                     {
5572                     case 0: imm = imm8; break;
5573                     case 1: imm = ((imm8 << 16) | imm8); break;
5574                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5575                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5576                     default:
5577                       mod  = (bits & 0xf80) >> 7;
5578                       imm8 = (bits & 0x07f) | 0x80;
5579                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5580                     }
5581                   func (stream, "#%u", imm);
5582                   value_in_comment = imm;
5583                 }
5584                 break;
5585
5586               case 'J':
5587                 {
5588                   unsigned int imm = 0;
5589
5590                   imm |= (given & 0x000000ffu);
5591                   imm |= (given & 0x00007000u) >> 4;
5592                   imm |= (given & 0x04000000u) >> 15;
5593                   imm |= (given & 0x000f0000u) >> 4;
5594                   func (stream, "#%u", imm);
5595                   value_in_comment = imm;
5596                 }
5597                 break;
5598
5599               case 'K':
5600                 {
5601                   unsigned int imm = 0;
5602
5603                   imm |= (given & 0x000f0000u) >> 16;
5604                   imm |= (given & 0x00000ff0u) >> 0;
5605                   imm |= (given & 0x0000000fu) << 12;
5606                   func (stream, "#%u", imm);
5607                   value_in_comment = imm;
5608                 }
5609                 break;
5610
5611               case 'H':
5612                 {
5613                   unsigned int imm = 0;
5614
5615                   imm |= (given & 0x000f0000u) >> 4;
5616                   imm |= (given & 0x00000fffu) >> 0;
5617                   func (stream, "#%u", imm);
5618                   value_in_comment = imm;
5619                 }
5620                 break;
5621
5622               case 'V':
5623                 {
5624                   unsigned int imm = 0;
5625
5626                   imm |= (given & 0x00000fffu);
5627                   imm |= (given & 0x000f0000u) >> 4;
5628                   func (stream, "#%u", imm);
5629                   value_in_comment = imm;
5630                 }
5631                 break;
5632
5633               case 'S':
5634                 {
5635                   unsigned int reg = (given & 0x0000000fu);
5636                   unsigned int stp = (given & 0x00000030u) >> 4;
5637                   unsigned int imm = 0;
5638                   imm |= (given & 0x000000c0u) >> 6;
5639                   imm |= (given & 0x00007000u) >> 10;
5640
5641                   func (stream, "%s", arm_regnames[reg]);
5642                   switch (stp)
5643                     {
5644                     case 0:
5645                       if (imm > 0)
5646                         func (stream, ", lsl #%u", imm);
5647                       break;
5648
5649                     case 1:
5650                       if (imm == 0)
5651                         imm = 32;
5652                       func (stream, ", lsr #%u", imm);
5653                       break;
5654
5655                     case 2:
5656                       if (imm == 0)
5657                         imm = 32;
5658                       func (stream, ", asr #%u", imm);
5659                       break;
5660
5661                     case 3:
5662                       if (imm == 0)
5663                         func (stream, ", rrx");
5664                       else
5665                         func (stream, ", ror #%u", imm);
5666                     }
5667                 }
5668                 break;
5669
5670               case 'a':
5671                 {
5672                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5673                   unsigned int U   = ! NEGATIVE_BIT_SET;
5674                   unsigned int op  = (given & 0x00000f00) >> 8;
5675                   unsigned int i12 = (given & 0x00000fff);
5676                   unsigned int i8  = (given & 0x000000ff);
5677                   bfd_boolean writeback = FALSE, postind = FALSE;
5678                   bfd_vma offset = 0;
5679
5680                   func (stream, "[%s", arm_regnames[Rn]);
5681                   if (U) /* 12-bit positive immediate offset.  */
5682                     {
5683                       offset = i12;
5684                       if (Rn != 15)
5685                         value_in_comment = offset;
5686                     }
5687                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
5688                     offset = - (int) i12;
5689                   else if (op == 0x0) /* Shifted register offset.  */
5690                     {
5691                       unsigned int Rm = (i8 & 0x0f);
5692                       unsigned int sh = (i8 & 0x30) >> 4;
5693
5694                       func (stream, ", %s", arm_regnames[Rm]);
5695                       if (sh)
5696                         func (stream, ", lsl #%u", sh);
5697                       func (stream, "]");
5698                       break;
5699                     }
5700                   else switch (op)
5701                     {
5702                     case 0xE:  /* 8-bit positive immediate offset.  */
5703                       offset = i8;
5704                       break;
5705
5706                     case 0xC:  /* 8-bit negative immediate offset.  */
5707                       offset = -i8;
5708                       break;
5709
5710                     case 0xF:  /* 8-bit + preindex with wb.  */
5711                       offset = i8;
5712                       writeback = TRUE;
5713                       break;
5714
5715                     case 0xD:  /* 8-bit - preindex with wb.  */
5716                       offset = -i8;
5717                       writeback = TRUE;
5718                       break;
5719
5720                     case 0xB:  /* 8-bit + postindex.  */
5721                       offset = i8;
5722                       postind = TRUE;
5723                       break;
5724
5725                     case 0x9:  /* 8-bit - postindex.  */
5726                       offset = -i8;
5727                       postind = TRUE;
5728                       break;
5729
5730                     default:
5731                       func (stream, ", <undefined>]");
5732                       goto skip;
5733                     }
5734
5735                   if (postind)
5736                     func (stream, "], #%d", (int) offset);
5737                   else
5738                     {
5739                       if (offset)
5740                         func (stream, ", #%d", (int) offset);
5741                       func (stream, writeback ? "]!" : "]");
5742                     }
5743
5744                   if (Rn == 15)
5745                     {
5746                       func (stream, "\t; ");
5747                       info->print_address_func (((pc + 4) & ~3) + offset, info);
5748                     }
5749                 }
5750               skip:
5751                 break;
5752
5753               case 'A':
5754                 {
5755                   unsigned int U   = ! NEGATIVE_BIT_SET;
5756                   unsigned int W   = WRITEBACK_BIT_SET;
5757                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5758                   unsigned int off = (given & 0x000000ff);
5759
5760                   func (stream, "[%s", arm_regnames[Rn]);
5761
5762                   if (PRE_BIT_SET)
5763                     {
5764                       if (off || !U)
5765                         {
5766                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5767                           value_in_comment = off * 4 * (U ? 1 : -1);
5768                         }
5769                       func (stream, "]");
5770                       if (W)
5771                         func (stream, "!");
5772                     }
5773                   else
5774                     {
5775                       func (stream, "], ");
5776                       if (W)
5777                         {
5778                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
5779                           value_in_comment = off * 4 * (U ? 1 : -1);
5780                         }
5781                       else
5782                         {
5783                           func (stream, "{%u}", off);
5784                           value_in_comment = off;
5785                         }
5786                     }
5787                 }
5788                 break;
5789
5790               case 'w':
5791                 {
5792                   unsigned int Sbit = (given & 0x01000000) >> 24;
5793                   unsigned int type = (given & 0x00600000) >> 21;
5794
5795                   switch (type)
5796                     {
5797                     case 0: func (stream, Sbit ? "sb" : "b"); break;
5798                     case 1: func (stream, Sbit ? "sh" : "h"); break;
5799                     case 2:
5800                       if (Sbit)
5801                         func (stream, "??");
5802                       break;
5803                     case 3:
5804                       func (stream, "??");
5805                       break;
5806                     }
5807                 }
5808                 break;
5809
5810               case 'm':
5811                 {
5812                   int started = 0;
5813                   int reg;
5814
5815                   func (stream, "{");
5816                   for (reg = 0; reg < 16; reg++)
5817                     if ((given & (1 << reg)) != 0)
5818                       {
5819                         if (started)
5820                           func (stream, ", ");
5821                         started = 1;
5822                         func (stream, "%s", arm_regnames[reg]);
5823                       }
5824                   func (stream, "}");
5825                 }
5826                 break;
5827
5828               case 'E':
5829                 {
5830                   unsigned int msb = (given & 0x0000001f);
5831                   unsigned int lsb = 0;
5832
5833                   lsb |= (given & 0x000000c0u) >> 6;
5834                   lsb |= (given & 0x00007000u) >> 10;
5835                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5836                 }
5837                 break;
5838
5839               case 'F':
5840                 {
5841                   unsigned int width = (given & 0x0000001f) + 1;
5842                   unsigned int lsb = 0;
5843
5844                   lsb |= (given & 0x000000c0u) >> 6;
5845                   lsb |= (given & 0x00007000u) >> 10;
5846                   func (stream, "#%u, #%u", lsb, width);
5847                 }
5848                 break;
5849
5850               case 'b':
5851                 {
5852                   unsigned int S = (given & 0x04000000u) >> 26;
5853                   unsigned int J1 = (given & 0x00002000u) >> 13;
5854                   unsigned int J2 = (given & 0x00000800u) >> 11;
5855                   bfd_vma offset = 0;
5856
5857                   offset |= !S << 20;
5858                   offset |= J2 << 19;
5859                   offset |= J1 << 18;
5860                   offset |= (given & 0x003f0000) >> 4;
5861                   offset |= (given & 0x000007ff) << 1;
5862                   offset -= (1 << 20);
5863
5864                   info->print_address_func (pc + 4 + offset, info);
5865                 }
5866                 break;
5867
5868               case 'B':
5869                 {
5870                   unsigned int S = (given & 0x04000000u) >> 26;
5871                   unsigned int I1 = (given & 0x00002000u) >> 13;
5872                   unsigned int I2 = (given & 0x00000800u) >> 11;
5873                   bfd_vma offset = 0;
5874
5875                   offset |= !S << 24;
5876                   offset |= !(I1 ^ S) << 23;
5877                   offset |= !(I2 ^ S) << 22;
5878                   offset |= (given & 0x03ff0000u) >> 4;
5879                   offset |= (given & 0x000007ffu) << 1;
5880                   offset -= (1 << 24);
5881                   offset += pc + 4;
5882
5883                   /* BLX target addresses are always word aligned.  */
5884                   if ((given & 0x00001000u) == 0)
5885                       offset &= ~2u;
5886
5887                   info->print_address_func (offset, info);
5888                 }
5889                 break;
5890
5891               case 's':
5892                 {
5893                   unsigned int shift = 0;
5894
5895                   shift |= (given & 0x000000c0u) >> 6;
5896                   shift |= (given & 0x00007000u) >> 10;
5897                   if (WRITEBACK_BIT_SET)
5898                     func (stream, ", asr #%u", shift);
5899                   else if (shift)
5900                     func (stream, ", lsl #%u", shift);
5901                   /* else print nothing - lsl #0 */
5902                 }
5903                 break;
5904
5905               case 'R':
5906                 {
5907                   unsigned int rot = (given & 0x00000030) >> 4;
5908
5909                   if (rot)
5910                     func (stream, ", ror #%u", rot * 8);
5911                 }
5912                 break;
5913
5914               case 'U':
5915                 if ((given & 0xf0) == 0x60)
5916                   {
5917                     switch (given & 0xf)
5918                       {
5919                         case 0xf: func (stream, "sy"); break;
5920                         default:
5921                           func (stream, "#%d", (int) given & 0xf);
5922                               break;
5923                       }
5924                   }
5925                 else
5926                   {
5927                     const char * opt = data_barrier_option (given & 0xf);
5928                     if (opt != NULL)
5929                       func (stream, "%s", opt);
5930                     else
5931                       func (stream, "#%d", (int) given & 0xf);
5932                    }
5933                 break;
5934
5935               case 'C':
5936                 if ((given & 0xff) == 0)
5937                   {
5938                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5939                     if (given & 0x800)
5940                       func (stream, "f");
5941                     if (given & 0x400)
5942                       func (stream, "s");
5943                     if (given & 0x200)
5944                       func (stream, "x");
5945                     if (given & 0x100)
5946                       func (stream, "c");
5947                   }
5948                 else if ((given & 0x20) == 0x20)
5949                   {
5950                     char const* name;
5951                     unsigned sysm = (given & 0xf00) >> 8;
5952
5953                     sysm |= (given & 0x30);
5954                     sysm |= (given & 0x00100000) >> 14;
5955                     name = banked_regname (sysm);
5956
5957                     if (name != NULL)
5958                       func (stream, "%s", name);
5959                     else
5960                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5961                   }
5962                 else
5963                   {
5964                     func (stream, "%s", psr_name (given & 0xff));
5965                   }
5966                 break;
5967
5968               case 'D':
5969                 if (((given & 0xff) == 0)
5970                     || ((given & 0x20) == 0x20))
5971                   {
5972                     char const* name;
5973                     unsigned sm = (given & 0xf0000) >> 16;
5974
5975                     sm |= (given & 0x30);
5976                     sm |= (given & 0x00100000) >> 14;
5977                     name = banked_regname (sm);
5978
5979                     if (name != NULL)
5980                       func (stream, "%s", name);
5981                     else
5982                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5983                   }
5984                 else
5985                   func (stream, "%s", psr_name (given & 0xff));
5986                 break;
5987
5988               case '0': case '1': case '2': case '3': case '4':
5989               case '5': case '6': case '7': case '8': case '9':
5990                 {
5991                   int width;
5992                   unsigned long val;
5993
5994                   c = arm_decode_bitfield (c, given, &val, &width);
5995
5996                   switch (*c)
5997                     {
5998                     case 'd':
5999                       func (stream, "%lu", val);
6000                       value_in_comment = val;
6001                       break;
6002
6003                     case 'D':
6004                       func (stream, "%lu", val + 1);
6005                       value_in_comment = val + 1;
6006                       break;
6007
6008                     case 'W':
6009                       func (stream, "%lu", val * 4);
6010                       value_in_comment = val * 4;
6011                       break;
6012
6013                     case 'R':
6014                       if (val == 15)
6015                         is_unpredictable = TRUE;
6016                       /* Fall through.  */
6017                     case 'r':
6018                       func (stream, "%s", arm_regnames[val]);
6019                       break;
6020
6021                     case 'c':
6022                       func (stream, "%s", arm_conditional[val]);
6023                       break;
6024
6025                     case '\'':
6026                       c++;
6027                       if (val == ((1ul << width) - 1))
6028                         func (stream, "%c", *c);
6029                       break;
6030
6031                     case '`':
6032                       c++;
6033                       if (val == 0)
6034                         func (stream, "%c", *c);
6035                       break;
6036
6037                     case '?':
6038                       func (stream, "%c", c[(1 << width) - (int) val]);
6039                       c += 1 << width;
6040                       break;
6041
6042                     case 'x':
6043                       func (stream, "0x%lx", val & 0xffffffffUL);
6044                       break;
6045
6046                     default:
6047                       abort ();
6048                     }
6049                 }
6050                 break;
6051
6052               case 'L':
6053                 /* PR binutils/12534
6054                    If we have a PC relative offset in an LDRD or STRD
6055                    instructions then display the decoded address.  */
6056                 if (((given >> 16) & 0xf) == 0xf)
6057                   {
6058                     bfd_vma offset = (given & 0xff) * 4;
6059
6060                     if ((given & (1 << 23)) == 0)
6061                       offset = - offset;
6062                     func (stream, "\t; ");
6063                     info->print_address_func ((pc & ~3) + 4 + offset, info);
6064                   }
6065                 break;
6066
6067               default:
6068                 abort ();
6069               }
6070           }
6071
6072         if (value_in_comment > 32 || value_in_comment < -16)
6073           func (stream, "\t; 0x%lx", value_in_comment);
6074
6075         if (is_unpredictable)
6076           func (stream, UNPREDICTABLE_INSTRUCTION);
6077
6078         return;
6079       }
6080
6081   /* No match.  */
6082   abort ();
6083 }
6084
6085 /* Print data bytes on INFO->STREAM.  */
6086
6087 static void
6088 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6089                  struct disassemble_info *info,
6090                  long given)
6091 {
6092   switch (info->bytes_per_chunk)
6093     {
6094     case 1:
6095       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6096       break;
6097     case 2:
6098       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6099       break;
6100     case 4:
6101       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6102       break;
6103     default:
6104       abort ();
6105     }
6106 }
6107
6108 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6109    being displayed in symbol relative addresses.
6110
6111    Also disallow private symbol, with __tagsym$$ prefix,
6112    from ARM RVCT toolchain being displayed.  */
6113
6114 bfd_boolean
6115 arm_symbol_is_valid (asymbol * sym,
6116                      struct disassemble_info * info ATTRIBUTE_UNUSED)
6117 {
6118   const char * name;
6119
6120   if (sym == NULL)
6121     return FALSE;
6122
6123   name = bfd_asymbol_name (sym);
6124
6125   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
6126 }
6127
6128 /* Parse the string of disassembler options.  */
6129
6130 static void
6131 parse_arm_disassembler_options (const char *options)
6132 {
6133   const char *opt;
6134
6135   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
6136     {
6137       if (CONST_STRNEQ (opt, "reg-names-"))
6138         {
6139           unsigned int i;
6140           for (i = 0; i < NUM_ARM_OPTIONS; i++)
6141             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6142               {
6143                 regname_selected = i;
6144                 break;
6145               }
6146
6147           if (i >= NUM_ARM_OPTIONS)
6148             /* xgettext: c-format */
6149             opcodes_error_handler (_("unrecognised register name set: %s"),
6150                                    opt);
6151         }
6152       else if (CONST_STRNEQ (opt, "force-thumb"))
6153         force_thumb = 1;
6154       else if (CONST_STRNEQ (opt, "no-force-thumb"))
6155         force_thumb = 0;
6156       else
6157         /* xgettext: c-format */
6158         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
6159     }
6160
6161   return;
6162 }
6163
6164 static bfd_boolean
6165 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6166                          enum map_type *map_symbol);
6167
6168 /* Search back through the insn stream to determine if this instruction is
6169    conditionally executed.  */
6170
6171 static void
6172 find_ifthen_state (bfd_vma pc,
6173                    struct disassemble_info *info,
6174                    bfd_boolean little)
6175 {
6176   unsigned char b[2];
6177   unsigned int insn;
6178   int status;
6179   /* COUNT is twice the number of instructions seen.  It will be odd if we
6180      just crossed an instruction boundary.  */
6181   int count;
6182   int it_count;
6183   unsigned int seen_it;
6184   bfd_vma addr;
6185
6186   ifthen_address = pc;
6187   ifthen_state = 0;
6188
6189   addr = pc;
6190   count = 1;
6191   it_count = 0;
6192   seen_it = 0;
6193   /* Scan backwards looking for IT instructions, keeping track of where
6194      instruction boundaries are.  We don't know if something is actually an
6195      IT instruction until we find a definite instruction boundary.  */
6196   for (;;)
6197     {
6198       if (addr == 0 || info->symbol_at_address_func (addr, info))
6199         {
6200           /* A symbol must be on an instruction boundary, and will not
6201              be within an IT block.  */
6202           if (seen_it && (count & 1))
6203             break;
6204
6205           return;
6206         }
6207       addr -= 2;
6208       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
6209       if (status)
6210         return;
6211
6212       if (little)
6213         insn = (b[0]) | (b[1] << 8);
6214       else
6215         insn = (b[1]) | (b[0] << 8);
6216       if (seen_it)
6217         {
6218           if ((insn & 0xf800) < 0xe800)
6219             {
6220               /* Addr + 2 is an instruction boundary.  See if this matches
6221                  the expected boundary based on the position of the last
6222                  IT candidate.  */
6223               if (count & 1)
6224                 break;
6225               seen_it = 0;
6226             }
6227         }
6228       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6229         {
6230           enum map_type type = MAP_ARM;
6231           bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6232
6233           if (!found || (found && type == MAP_THUMB))
6234             {
6235               /* This could be an IT instruction.  */
6236               seen_it = insn;
6237               it_count = count >> 1;
6238             }
6239         }
6240       if ((insn & 0xf800) >= 0xe800)
6241         count++;
6242       else
6243         count = (count + 2) | 1;
6244       /* IT blocks contain at most 4 instructions.  */
6245       if (count >= 8 && !seen_it)
6246         return;
6247     }
6248   /* We found an IT instruction.  */
6249   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6250   if ((ifthen_state & 0xf) == 0)
6251     ifthen_state = 0;
6252 }
6253
6254 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6255    mapping symbol.  */
6256
6257 static int
6258 is_mapping_symbol (struct disassemble_info *info, int n,
6259                    enum map_type *map_type)
6260 {
6261   const char *name;
6262
6263   name = bfd_asymbol_name (info->symtab[n]);
6264   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6265       && (name[2] == 0 || name[2] == '.'))
6266     {
6267       *map_type = ((name[1] == 'a') ? MAP_ARM
6268                    : (name[1] == 't') ? MAP_THUMB
6269                    : MAP_DATA);
6270       return TRUE;
6271     }
6272
6273   return FALSE;
6274 }
6275
6276 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6277    Returns nonzero if *MAP_TYPE was set.  */
6278
6279 static int
6280 get_map_sym_type (struct disassemble_info *info,
6281                   int n,
6282                   enum map_type *map_type)
6283 {
6284   /* If the symbol is in a different section, ignore it.  */
6285   if (info->section != NULL && info->section != info->symtab[n]->section)
6286     return FALSE;
6287
6288   return is_mapping_symbol (info, n, map_type);
6289 }
6290
6291 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6292    Returns nonzero if *MAP_TYPE was set.  */
6293
6294 static int
6295 get_sym_code_type (struct disassemble_info *info,
6296                    int n,
6297                    enum map_type *map_type)
6298 {
6299   elf_symbol_type *es;
6300   unsigned int type;
6301
6302   /* If the symbol is in a different section, ignore it.  */
6303   if (info->section != NULL && info->section != info->symtab[n]->section)
6304     return FALSE;
6305
6306   es = *(elf_symbol_type **)(info->symtab + n);
6307   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6308
6309   /* If the symbol has function type then use that.  */
6310   if (type == STT_FUNC || type == STT_GNU_IFUNC)
6311     {
6312       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6313           == ST_BRANCH_TO_THUMB)
6314         *map_type = MAP_THUMB;
6315       else
6316         *map_type = MAP_ARM;
6317       return TRUE;
6318     }
6319
6320   return FALSE;
6321 }
6322
6323 /* Search the mapping symbol state for instruction at pc.  This is only
6324    applicable for elf target.
6325
6326    There is an assumption Here, info->private_data contains the correct AND
6327    up-to-date information about current scan process.  The information will be
6328    used to speed this search process.
6329
6330    Return TRUE if the mapping state can be determined, and map_symbol
6331    will be updated accordingly.  Otherwise, return FALSE.  */
6332
6333 static bfd_boolean
6334 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6335                          enum map_type *map_symbol)
6336 {
6337   bfd_vma addr;
6338   int n, start = 0;
6339   bfd_boolean found = FALSE;
6340   enum map_type type = MAP_ARM;
6341   struct arm_private_data *private_data;
6342
6343   if (info->private_data == NULL || info->symtab_size == 0
6344       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6345     return FALSE;
6346
6347   private_data = info->private_data;
6348   if (pc == 0)
6349     start = 0;
6350   else
6351     start = private_data->last_mapping_sym;
6352
6353   start = (start == -1)? 0 : start;
6354   addr = bfd_asymbol_value (info->symtab[start]);
6355
6356   if (pc >= addr)
6357     {
6358       if (get_map_sym_type (info, start, &type))
6359       found = TRUE;
6360     }
6361   else
6362     {
6363       for (n = start - 1; n >= 0; n--)
6364         {
6365           if (get_map_sym_type (info, n, &type))
6366             {
6367               found = TRUE;
6368               break;
6369             }
6370         }
6371     }
6372
6373   /* No mapping symbols were found.  A leading $d may be
6374      omitted for sections which start with data; but for
6375      compatibility with legacy and stripped binaries, only
6376      assume the leading $d if there is at least one mapping
6377      symbol in the file.  */
6378   if (!found && private_data->has_mapping_symbols == 1)
6379     {
6380       type = MAP_DATA;
6381       found = TRUE;
6382     }
6383
6384   *map_symbol = type;
6385   return found;
6386 }
6387
6388 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6389    of the supplied arm_feature_set structure with bitmasks indicating
6390    the support base architectures and coprocessor extensions.
6391
6392    FIXME: This could more efficiently implemented as a constant array,
6393    although it would also be less robust.  */
6394
6395 static void
6396 select_arm_features (unsigned long mach,
6397                      arm_feature_set * features)
6398 {
6399 #undef ARM_SET_FEATURES
6400 #define ARM_SET_FEATURES(FSET) \
6401   {                                                     \
6402     const arm_feature_set fset = FSET;                  \
6403     arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6404     ARM_MERGE_FEATURE_SETS (*features, tmp, fset);      \
6405   }
6406
6407   switch (mach)
6408     {
6409     case bfd_mach_arm_2:       ARM_SET_FEATURES (ARM_ARCH_V2); break;
6410     case bfd_mach_arm_2a:      ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6411     case bfd_mach_arm_3:       ARM_SET_FEATURES (ARM_ARCH_V3); break;
6412     case bfd_mach_arm_3M:      ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6413     case bfd_mach_arm_4:       ARM_SET_FEATURES (ARM_ARCH_V4); break;
6414     case bfd_mach_arm_4T:      ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6415     case bfd_mach_arm_5:       ARM_SET_FEATURES (ARM_ARCH_V5); break;
6416     case bfd_mach_arm_5T:      ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6417     case bfd_mach_arm_5TE:     ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6418     case bfd_mach_arm_XScale:  ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6419     case bfd_mach_arm_ep9312:
6420       ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6421                                          ARM_CEXT_MAVERICK | FPU_MAVERICK));
6422        break;
6423     case bfd_mach_arm_iWMMXt:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6424     case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6425       /* If the machine type is unknown allow all
6426          architecture types and all extensions.  */
6427     case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6428     default:
6429       abort ();
6430     }
6431
6432 #undef ARM_SET_FEATURES
6433 }
6434
6435
6436 /* NOTE: There are no checks in these routines that
6437    the relevant number of data bytes exist.  */
6438
6439 static int
6440 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6441 {
6442   unsigned char b[4];
6443   long          given;
6444   int           status;
6445   int           is_thumb = FALSE;
6446   int           is_data = FALSE;
6447   int           little_code;
6448   unsigned int  size = 4;
6449   void          (*printer) (bfd_vma, struct disassemble_info *, long);
6450   bfd_boolean   found = FALSE;
6451   struct arm_private_data *private_data;
6452
6453   if (info->disassembler_options)
6454     {
6455       parse_arm_disassembler_options (info->disassembler_options);
6456
6457       /* To avoid repeated parsing of these options, we remove them here.  */
6458       info->disassembler_options = NULL;
6459     }
6460
6461   /* PR 10288: Control which instructions will be disassembled.  */
6462   if (info->private_data == NULL)
6463     {
6464       static struct arm_private_data private;
6465
6466       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6467         /* If the user did not use the -m command line switch then default to
6468            disassembling all types of ARM instruction.
6469
6470            The info->mach value has to be ignored as this will be based on
6471            the default archictecture for the target and/or hints in the notes
6472            section, but it will never be greater than the current largest arm
6473            machine value (iWMMXt2), which is only equivalent to the V5TE
6474            architecture.  ARM architectures have advanced beyond the machine
6475            value encoding, and these newer architectures would be ignored if
6476            the machine value was used.
6477
6478            Ie the -m switch is used to restrict which instructions will be
6479            disassembled.  If it is necessary to use the -m switch to tell
6480            objdump that an ARM binary is being disassembled, eg because the
6481            input is a raw binary file, but it is also desired to disassemble
6482            all ARM instructions then use "-marm".  This will select the
6483            "unknown" arm architecture which is compatible with any ARM
6484            instruction.  */
6485           info->mach = bfd_mach_arm_unknown;
6486
6487       /* Compute the architecture bitmask from the machine number.
6488          Note: This assumes that the machine number will not change
6489          during disassembly....  */
6490       select_arm_features (info->mach, & private.features);
6491
6492       private.has_mapping_symbols = -1;
6493       private.last_mapping_sym = -1;
6494       private.last_mapping_addr = 0;
6495
6496       info->private_data = & private;
6497     }
6498
6499   private_data = info->private_data;
6500
6501   /* Decide if our code is going to be little-endian, despite what the
6502      function argument might say.  */
6503   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6504
6505   /* For ELF, consult the symbol table to determine what kind of code
6506      or data we have.  */
6507   if (info->symtab_size != 0
6508       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6509     {
6510       bfd_vma addr;
6511       int n, start;
6512       int last_sym = -1;
6513       enum map_type type = MAP_ARM;
6514
6515       /* Start scanning at the start of the function, or wherever
6516          we finished last time.  */
6517       /* PR 14006.  When the address is 0 we are either at the start of the
6518          very first function, or else the first function in a new, unlinked
6519          executable section (eg because of -ffunction-sections).  Either way
6520          start scanning from the beginning of the symbol table, not where we
6521          left off last time.  */
6522       if (pc == 0)
6523         start = 0;
6524       else
6525         {
6526           start = info->symtab_pos + 1;
6527           if (start < private_data->last_mapping_sym)
6528             start = private_data->last_mapping_sym;
6529         }
6530       found = FALSE;
6531
6532       /* First, look for mapping symbols.  */
6533       if (private_data->has_mapping_symbols != 0)
6534         {
6535           /* Scan up to the location being disassembled.  */
6536           for (n = start; n < info->symtab_size; n++)
6537             {
6538               addr = bfd_asymbol_value (info->symtab[n]);
6539               if (addr > pc)
6540                 break;
6541               if (get_map_sym_type (info, n, &type))
6542                 {
6543                   last_sym = n;
6544                   found = TRUE;
6545                 }
6546             }
6547
6548           if (!found)
6549             {
6550               /* No mapping symbol found at this address.  Look backwards
6551                  for a preceding one.  */
6552               for (n = start - 1; n >= 0; n--)
6553                 {
6554                   if (get_map_sym_type (info, n, &type))
6555                     {
6556                       last_sym = n;
6557                       found = TRUE;
6558                       break;
6559                     }
6560                 }
6561             }
6562
6563           if (found)
6564             private_data->has_mapping_symbols = 1;
6565
6566           /* No mapping symbols were found.  A leading $d may be
6567              omitted for sections which start with data; but for
6568              compatibility with legacy and stripped binaries, only
6569              assume the leading $d if there is at least one mapping
6570              symbol in the file.  */
6571           if (!found && private_data->has_mapping_symbols == -1)
6572             {
6573               /* Look for mapping symbols, in any section.  */
6574               for (n = 0; n < info->symtab_size; n++)
6575                 if (is_mapping_symbol (info, n, &type))
6576                   {
6577                     private_data->has_mapping_symbols = 1;
6578                     break;
6579                   }
6580               if (private_data->has_mapping_symbols == -1)
6581                 private_data->has_mapping_symbols = 0;
6582             }
6583
6584           if (!found && private_data->has_mapping_symbols == 1)
6585             {
6586               type = MAP_DATA;
6587               found = TRUE;
6588             }
6589         }
6590
6591       /* Next search for function symbols to separate ARM from Thumb
6592          in binaries without mapping symbols.  */
6593       if (!found)
6594         {
6595           /* Scan up to the location being disassembled.  */
6596           for (n = start; n < info->symtab_size; n++)
6597             {
6598               addr = bfd_asymbol_value (info->symtab[n]);
6599               if (addr > pc)
6600                 break;
6601               if (get_sym_code_type (info, n, &type))
6602                 {
6603                   last_sym = n;
6604                   found = TRUE;
6605                 }
6606             }
6607
6608           if (!found)
6609             {
6610               /* No mapping symbol found at this address.  Look backwards
6611                  for a preceding one.  */
6612               for (n = start - 1; n >= 0; n--)
6613                 {
6614                   if (get_sym_code_type (info, n, &type))
6615                     {
6616                       last_sym = n;
6617                       found = TRUE;
6618                       break;
6619                     }
6620                 }
6621             }
6622         }
6623
6624       private_data->last_mapping_sym = last_sym;
6625       private_data->last_type = type;
6626       is_thumb = (private_data->last_type == MAP_THUMB);
6627       is_data = (private_data->last_type == MAP_DATA);
6628
6629       /* Look a little bit ahead to see if we should print out
6630          two or four bytes of data.  If there's a symbol,
6631          mapping or otherwise, after two bytes then don't
6632          print more.  */
6633       if (is_data)
6634         {
6635           size = 4 - (pc & 3);
6636           for (n = last_sym + 1; n < info->symtab_size; n++)
6637             {
6638               addr = bfd_asymbol_value (info->symtab[n]);
6639               if (addr > pc
6640                   && (info->section == NULL
6641                       || info->section == info->symtab[n]->section))
6642                 {
6643                   if (addr - pc < size)
6644                     size = addr - pc;
6645                   break;
6646                 }
6647             }
6648           /* If the next symbol is after three bytes, we need to
6649              print only part of the data, so that we can use either
6650              .byte or .short.  */
6651           if (size == 3)
6652             size = (pc & 1) ? 1 : 2;
6653         }
6654     }
6655
6656   if (info->symbols != NULL)
6657     {
6658       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6659         {
6660           coff_symbol_type * cs;
6661
6662           cs = coffsymbol (*info->symbols);
6663           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
6664                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
6665                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
6666                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6667                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6668         }
6669       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6670                && !found)
6671         {
6672           /* If no mapping symbol has been found then fall back to the type
6673              of the function symbol.  */
6674           elf_symbol_type *  es;
6675           unsigned int       type;
6676
6677           es = *(elf_symbol_type **)(info->symbols);
6678           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6679
6680           is_thumb =
6681             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6682               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
6683         }
6684       else if (bfd_asymbol_flavour (*info->symbols)
6685                == bfd_target_mach_o_flavour)
6686         {
6687           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6688
6689           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6690         }
6691     }
6692
6693   if (force_thumb)
6694     is_thumb = TRUE;
6695
6696   if (is_data)
6697     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6698   else
6699     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6700
6701   info->bytes_per_line = 4;
6702
6703   /* PR 10263: Disassemble data if requested to do so by the user.  */
6704   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6705     {
6706       int i;
6707
6708       /* Size was already set above.  */
6709       info->bytes_per_chunk = size;
6710       printer = print_insn_data;
6711
6712       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6713       given = 0;
6714       if (little)
6715         for (i = size - 1; i >= 0; i--)
6716           given = b[i] | (given << 8);
6717       else
6718         for (i = 0; i < (int) size; i++)
6719           given = b[i] | (given << 8);
6720     }
6721   else if (!is_thumb)
6722     {
6723       /* In ARM mode endianness is a straightforward issue: the instruction
6724          is four bytes long and is either ordered 0123 or 3210.  */
6725       printer = print_insn_arm;
6726       info->bytes_per_chunk = 4;
6727       size = 4;
6728
6729       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6730       if (little_code)
6731         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6732       else
6733         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6734     }
6735   else
6736     {
6737       /* In Thumb mode we have the additional wrinkle of two
6738          instruction lengths.  Fortunately, the bits that determine
6739          the length of the current instruction are always to be found
6740          in the first two bytes.  */
6741       printer = print_insn_thumb16;
6742       info->bytes_per_chunk = 2;
6743       size = 2;
6744
6745       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6746       if (little_code)
6747         given = (b[0]) | (b[1] << 8);
6748       else
6749         given = (b[1]) | (b[0] << 8);
6750
6751       if (!status)
6752         {
6753           /* These bit patterns signal a four-byte Thumb
6754              instruction.  */
6755           if ((given & 0xF800) == 0xF800
6756               || (given & 0xF800) == 0xF000
6757               || (given & 0xF800) == 0xE800)
6758             {
6759               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6760               if (little_code)
6761                 given = (b[0]) | (b[1] << 8) | (given << 16);
6762               else
6763                 given = (b[1]) | (b[0] << 8) | (given << 16);
6764
6765               printer = print_insn_thumb32;
6766               size = 4;
6767             }
6768         }
6769
6770       if (ifthen_address != pc)
6771         find_ifthen_state (pc, info, little_code);
6772
6773       if (ifthen_state)
6774         {
6775           if ((ifthen_state & 0xf) == 0x8)
6776             ifthen_next_state = 0;
6777           else
6778             ifthen_next_state = (ifthen_state & 0xe0)
6779                                 | ((ifthen_state & 0xf) << 1);
6780         }
6781     }
6782
6783   if (status)
6784     {
6785       info->memory_error_func (status, pc, info);
6786       return -1;
6787     }
6788   if (info->flags & INSN_HAS_RELOC)
6789     /* If the instruction has a reloc associated with it, then
6790        the offset field in the instruction will actually be the
6791        addend for the reloc.  (We are using REL type relocs).
6792        In such cases, we can ignore the pc when computing
6793        addresses, since the addend is not currently pc-relative.  */
6794     pc = 0;
6795
6796   printer (pc, info, given);
6797
6798   if (is_thumb)
6799     {
6800       ifthen_state = ifthen_next_state;
6801       ifthen_address += size;
6802     }
6803   return size;
6804 }
6805
6806 int
6807 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6808 {
6809   /* Detect BE8-ness and record it in the disassembler info.  */
6810   if (info->flavour == bfd_target_elf_flavour
6811       && info->section != NULL
6812       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6813     info->endian_code = BFD_ENDIAN_LITTLE;
6814
6815   return print_insn (pc, info, FALSE);
6816 }
6817
6818 int
6819 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6820 {
6821   return print_insn (pc, info, TRUE);
6822 }
6823
6824 const disasm_options_t *
6825 disassembler_options_arm (void)
6826 {
6827   static disasm_options_t *opts = NULL;
6828
6829   if (opts == NULL)
6830     {
6831       unsigned int i;
6832       opts = XNEW (disasm_options_t);
6833       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6834       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6835       for (i = 0; i < NUM_ARM_OPTIONS; i++)
6836         {
6837           opts->name[i] = regnames[i].name;
6838           if (regnames[i].description != NULL)
6839             opts->description[i] = _(regnames[i].description);
6840           else
6841             opts->description[i] = NULL;
6842         }
6843       /* The array we return must be NULL terminated.  */
6844       opts->name[i] = NULL;
6845       opts->description[i] = NULL;
6846     }
6847
6848   return opts;
6849 }
6850
6851 void
6852 print_arm_disassembler_options (FILE *stream)
6853 {
6854   unsigned int i, max_len = 0;
6855   fprintf (stream, _("\n\
6856 The following ARM specific disassembler options are supported for use with\n\
6857 the -M switch:\n"));
6858
6859   for (i = 0; i < NUM_ARM_OPTIONS; i++)
6860     {
6861       unsigned int len = strlen (regnames[i].name);
6862       if (max_len < len)
6863         max_len = len;
6864     }
6865
6866   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6867     fprintf (stream, "  %s%*c %s\n",
6868              regnames[i].name,
6869              (int)(max_len - strlen (regnames[i].name)), ' ',
6870              _(regnames[i].description));
6871 }