| blob | f46673986ba781da4bd5a2617e8669006aa5b3f2 |
1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
3 Copyright (C) 1999-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
42 #ifdef HAVE_LIBUNWIND_IA64_H
46 /* Note: KERNEL_START is supposed to be an address which is not going
47 to ever contain any valid unwind info. For ia64 linux, the choice
48 of 0xc000000000000000 is fairly safe since that's uncached space.
50 We use KERNEL_START as follows: after obtaining the kernel's
51 unwind table via getunwind(), we project its unwind data into
52 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
53 when ia64_access_mem() sees a memory access to this
54 address-range, we redirect it to ktab instead.
56 None of this hackery is needed with a modern kernel/libcs
57 which uses the kernel virtual DSO to provide access to the
58 kernel's unwind info. In that case, ktab_size remains 0 and
59 hence the value of KERNEL_START doesn't matter. */
61 #define KERNEL_START 0xc000000000000000ULL
64 struct ia64_table_entry
65 {
69 };
74 #endif
76 /* An enumeration of the different IA-64 instruction types. */
79 {
87 undefined /* undefined or reserved */
90 /* We represent IA-64 PC addresses as the value of the instruction
91 pointer or'd with some bit combination in the low nibble which
92 represents the slot number in the bundle addressed by the
93 instruction pointer. The problem is that the Linux kernel
94 multiplies its slot numbers (for exceptions) by one while the
95 disassembler multiplies its slot numbers by 6. In addition, I've
96 heard it said that the simulator uses 1 as the multiplier.
98 I've fixed the disassembler so that the bytes_per_line field will
99 be the slot multiplier. If bytes_per_line comes in as zero, it
100 is set to six (which is how it was set up initially). -- objdump
101 displays pretty disassembly dumps with this value. For our purposes,
102 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
103 never want to also display the raw bytes the way objdump does. */
105 #define SLOT_MULTIPLIER 1
107 /* Length in bytes of an instruction bundle. */
109 #define BUNDLE_LEN 16
111 /* See the saved memory layout comment for ia64_memory_insert_breakpoint. */
113 #if BREAKPOINT_MAX < BUNDLE_LEN - 2
115 #endif
125 CORE_ADDR faddr);
127 #define NUM_IA64_RAW_REGS 462
129 /* Big enough to hold a FP register in bytes. */
130 #define IA64_FP_REGISTER_SIZE 16
134 /* NOTE: we treat the register stack registers r32-r127 as
135 pseudo-registers because they may not be accessible via the ptrace
136 register get/set interfaces. */
144 /* Array of register names; There should be ia64_num_regs strings in
145 the initializer. */
254 };
256 struct ia64_frame_cache
257 {
268 cfm value). */
269 CORE_ADDR after_prologue;
270 /* Address of first instruction after the last
271 prologue instruction; Note that there may
272 be instructions from the function's body
273 intermingled with the prologue. */
275 /* Size of the memory stack frame (may be zero),
276 or -1 if it has not been determined yet. */
278 for this frame. 0 if no register is being used
279 as the frame pointer. */
281 /* Saved registers. */
284 };
286 static int
288 {
290 }
293 {
296 };
299 {
302 };
305 {
307 &floatformat_ia64_ext_little
308 };
312 {
316 tdep->ia64_ext_type
318 floatformats_ia64_ext);
321 }
323 static int
326 {
344 }
348 {
350 }
354 {
357 else
359 }
361 static int
363 {
367 }
370 /* Extract ``len'' bits from an instruction bundle starting at
371 bit ``from''. */
373 static long long
375 {
392 {
395 }
398 {
402 }
405 }
407 /* Replace the specified bits in an instruction bundle. */
409 static void
411 {
419 {
428 }
429 else
430 {
439 {
443 }
446 {
452 }
453 }
454 }
456 /* Return the contents of slot N (for N = 0, 1, or 2) in
457 and instruction bundle. */
459 static long long
461 {
463 }
465 /* Store an instruction in an instruction bundle. */
467 static void
469 {
471 }
474 {
507 };
509 /* Fetch and (partially) decode an instruction at ADDR and return the
510 address of the next instruction to fetch. */
512 static CORE_ADDR
514 {
520 /* Warn about slot numbers greater than 2. We used to generate
521 an error here on the assumption that the user entered an invalid
522 address. But, sometimes GDB itself requests an invalid address.
523 This can (easily) happen when execution stops in a function for
524 which there are no symbols. The prologue scanner will attempt to
525 find the beginning of the function - if the nearest symbol
526 happens to not be aligned on a bundle boundary (16 bytes), the
527 resulting starting address will cause GDB to think that the slot
528 number is too large.
530 So we warn about it and set the slot number to zero. It is
531 not necessarily a fatal condition, particularly if debugging
532 at the assembly language level. */
534 {
538 }
553 else
557 }
559 /* There are 5 different break instructions (break.i, break.b,
560 break.m, break.f, and break.x), but they all have the same
561 encoding. (The five bit template in the low five bits of the
562 instruction bundle distinguishes one from another.)
564 The runtime architecture manual specifies that break instructions
565 used for debugging purposes must have the upper two bits of the 21
566 bit immediate set to a 0 and a 1 respectively. A breakpoint
567 instruction encodes the most significant bit of its 21 bit
568 immediate at bit 36 of the 41 bit instruction. The penultimate msb
569 is at bit 25 which leads to the pattern below.
571 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
572 it turns out that 0x80000 was used as the syscall break in the early
573 simulators. So I changed the pattern slightly to do "break.i 0x080001"
574 instead. But that didn't work either (I later found out that this
575 pattern was used by the simulator that I was using.) So I ended up
576 using the pattern seen below.
578 SHADOW_CONTENTS has byte-based addressing (PLACED_ADDRESS and SHADOW_LEN)
579 while we need bit-based addressing as the instructions length is 41 bits and
580 we must not modify/corrupt the adjacent slots in the same bundle.
581 Fortunately we may store larger memory incl. the adjacent bits with the
582 original memory content (not the possibly already stored breakpoints there).
583 We need to be careful in ia64_memory_remove_breakpoint to always restore
584 only the specific bits of this instruction ignoring any adjacent stored
585 bits.
587 We use the original addressing with the low nibble in the range <0..2> which
588 gets incorrectly interpreted by generic non-ia64 breakpoint_restore_shadows
589 as the direct byte offset of SHADOW_CONTENTS. We store whole BUNDLE_LEN
590 bytes just without these two possibly skipped bytes to not to exceed to the
591 next bundle.
593 If we would like to store the whole bundle to SHADOW_CONTENTS we would have
594 to store already the base address (`address & ~0x0f') into PLACED_ADDRESS.
595 In such case there is no other place where to store
596 SLOTNUM (`adress & 0x0f', value in the range <0..2>). We need to know
597 SLOTNUM in ia64_memory_remove_breakpoint.
599 There is one special case where we need to be extra careful:
600 L-X instructions, which are instructions that occupy 2 slots
601 (The L part is always in slot 1, and the X part is always in
602 slot 2). We must refuse to insert breakpoints for an address
603 that points at slot 2 of a bundle where an L-X instruction is
604 present, since there is logically no instruction at that address.
605 However, to make things more interesting, the opcode of L-X
606 instructions is located in slot 2. This means that, to insert
607 a breakpoint at an address that points to slot 1, we actually
608 need to write the breakpoint in slot 2! Slot 1 is actually
609 the extended operand, so writing the breakpoint there would not
610 have the desired effect. Another side-effect of this issue
611 is that we need to make sure that the shadow contents buffer
612 does save byte 15 of our instruction bundle (this is the tail
613 end of slot 2, which wouldn't be saved if we were to insert
614 the breakpoint in slot 1).
616 ia64 16-byte bundle layout:
617 | 5 bits | slot 0 with 41 bits | slot 1 with 41 bits | slot 2 with 41 bits |
619 The current addressing used by the code below:
620 original PC placed_address placed_size required covered
621 == bp_tgt->shadow_len reqd \subset covered
622 0xABCDE0 0xABCDE0 0x10 <0x0...0x5> <0x0..0xF>
623 0xABCDE1 0xABCDE1 0xF <0x5...0xA> <0x1..0xF>
624 0xABCDE2 0xABCDE2 0xE <0xA...0xF> <0x2..0xF>
626 L-X instructions are treated a little specially, as explained above:
627 0xABCDE1 0xABCDE1 0xF <0xA...0xF> <0x1..0xF>
629 `objdump -d' and some other tools show a bit unjustified offsets:
630 original PC byte where starts the instruction objdump offset
631 0xABCDE0 0xABCDE0 0xABCDE0
632 0xABCDE1 0xABCDE5 0xABCDE6
633 0xABCDE2 0xABCDEA 0xABCDEC
634 */
636 #define IA64_BREAKPOINT 0x00003333300LL
638 static int
641 {
654 /* Enable the automatic memory restoration from breakpoints while
655 we read our instruction bundle for the purpose of SHADOW_CONTENTS.
656 Otherwise, we could possibly store into the shadow parts of the adjacent
657 placed breakpoints. It is due to our SHADOW_CONTENTS overlapping the real
658 breakpoint instruction bits region. */
659 scoped_restore restore_memory_0
665 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
666 for addressing the SHADOW_CONTENTS placement. */
669 /* Always cover the last byte of the bundle in case we are inserting
670 a breakpoint on an L-X instruction. */
675 {
676 /* X unit types can only be used in slot 2, and are actually
677 part of a 2-slot L-X instruction. We cannot break at this
678 address, as this is the second half of an instruction that
679 lives in slot 1 of that bundle. */
682 }
684 {
685 /* L unit types can only be used in slot 1. But the associated
686 opcode for that instruction is in slot 2, so bump the slot number
687 accordingly. */
690 }
692 /* Store the whole bundle, except for the initial skipped bytes by the slot
693 number interpreted as bytes offset in PLACED_ADDRESS. */
697 /* Re-read the same bundle as above except that, this time, read it in order
698 to compute the new bundle inside which we will be inserting the
699 breakpoint. Therefore, disable the automatic memory restoration from
700 breakpoints while we read our instruction bundle. Otherwise, the general
701 restoration mechanism kicks in and we would possibly remove parts of the
702 adjacent placed breakpoints. It is due to our SHADOW_CONTENTS overlapping
703 the real breakpoint instruction bits region. */
704 scoped_restore restore_memory_1
710 /* Breakpoints already present in the code will get deteacted and not get
711 reinserted by bp_loc_is_permanent. Multiple breakpoints at the same
712 location cannot induce the internal error as they are optimized into
713 a single instance by update_global_location_list. */
725 }
727 static int
730 {
740 /* Disable the automatic memory restoration from breakpoints while
741 we read our instruction bundle. Otherwise, the general restoration
742 mechanism kicks in and we would possibly remove parts of the adjacent
743 placed breakpoints. It is due to our SHADOW_CONTENTS overlapping the real
744 breakpoint instruction bits region. */
745 scoped_restore restore_memory_1
751 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
752 for addressing the SHADOW_CONTENTS placement. */
757 {
758 /* X unit types can only be used in slot 2, and are actually
759 part of a 2-slot L-X instruction. We refuse to insert
760 breakpoints at this address, so there should be no reason
761 for us attempting to remove one there, except if the program's
762 code somehow got modified in memory. */
768 }
770 {
771 /* L unit types can only be used in slot 1. But the breakpoint
772 was actually saved using slot 2, so update the slot number
773 accordingly. */
776 }
782 {
787 }
789 /* Extract the original saved instruction from SLOTNUM normalizing its
790 bit-shift for INSTR_SAVED. */
796 /* In BUNDLE_MEM, be careful to modify only the bits belonging to SLOTNUM
797 and not any of the other ones that are stored in SHADOW_CONTENTS. */
802 }
804 /* Implement the breakpoint_kind_from_pc gdbarch method. */
806 static int
808 {
809 /* A place holder of gdbarch method breakpoint_kind_from_pc. */
811 }
813 /* As gdbarch_breakpoint_from_pc ranges have byte granularity and ia64
814 instruction slots ranges are bit-granular (41 bits) we have to provide an
815 extended range as described for ia64_memory_insert_breakpoint. We also take
816 care of preserving the `break' instruction 21-bit (or 62-bit) parameter to
817 make a match for permanent breakpoints. */
822 {
835 /* Enable the automatic memory restoration from breakpoints while
836 we read our instruction bundle to match bp_loc_is_permanent. */
837 {
838 scoped_restore restore_memory_0
841 }
843 /* The memory might be unreachable. This can happen, for instance,
844 when the user inserts a breakpoint at an invalid address. */
848 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
849 for addressing the SHADOW_CONTENTS placement. */
852 /* Cover always the last byte of the bundle for the L-X slot case. */
855 /* Check for L type instruction in slot 1, if present then bump up the slot
856 number to the slot 2. */
859 {
862 }
864 {
867 }
869 /* A break instruction has its all its opcode bits cleared except for
870 the parameter value. For L+X slot pair we are at the X slot (slot 2) so
871 we should not touch the L slot - the upper 41 bits of the parameter. */
877 }
879 static CORE_ADDR
881 {
890 }
892 void
894 {
896 ULONGEST psr_value;
906 }
908 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
910 /* Returns the address of the slot that's NSLOTS slots away from
911 the address ADDR. NSLOTS may be positive or negative. */
912 static CORE_ADDR
914 {
915 CORE_ADDR new_addr;
928 }
930 static enum register_status
933 {
938 {
939 #ifdef HAVE_LIBUNWIND_IA64_H
940 /* First try and use the libunwind special reg accessor,
941 otherwise fallback to standard logic. */
944 #endif
945 {
946 /* The fallback position is to assume that r32-r127 are
947 found sequentially in memory starting at $bof. This
948 isn't always true, but without libunwind, this is the
949 best we can do. */
950 ULONGEST cfm;
951 ULONGEST bsp;
952 CORE_ADDR reg;
962 /* The bsp points at the end of the register frame so we
963 subtract the size of frame from it to get start of
964 register frame. */
968 {
973 }
974 else
977 }
978 }
980 {
981 ULONGEST unatN_val;
982 ULONGEST unat;
990 }
992 {
994 ULONGEST bsp;
995 ULONGEST cfm;
1006 /* The bsp points at the end of the register frame so we
1007 subtract the size of frame from it to get start of register frame. */
1014 {
1015 /* Compute address of nat collection bits. */
1017 ULONGEST nat_collection;
1019 /* If our nat collection address is bigger than bsp, we have to get
1020 the nat collection from rnat. Otherwise, we fetch the nat
1021 collection from the computed address. */
1024 else
1028 }
1032 }
1034 {
1035 /* A virtual register frame start is provided for user convenience.
1036 It can be calculated as the bsp - sof (sizeof frame). */
1038 ULONGEST cfm;
1047 /* The bsp points at the end of the register frame so we
1048 subtract the size of frame from it to get beginning of frame. */
1052 }
1054 {
1055 ULONGEST pr;
1056 ULONGEST cfm;
1057 ULONGEST prN_val;
1067 {
1068 /* Fetch predicate register rename base from current frame
1069 marker for this frame. */
1072 /* Adjust the register number to account for register rotation. */
1073 regnum = VP16_REGNUM
1075 }
1079 }
1080 else
1084 }
1086 static void
1089 {
1093 {
1094 ULONGEST bsp;
1095 ULONGEST cfm;
1102 {
1105 }
1106 }
1108 {
1112 regnum),
1113 byte_order);
1120 }
1122 {
1123 ULONGEST natN_val;
1124 ULONGEST bsp;
1125 ULONGEST cfm;
1130 /* The bsp points at the end of the register frame so we
1131 subtract the size of frame from it to get start of register frame. */
1138 regnum),
1139 byte_order);
1142 {
1143 /* Compute address of nat collection bits. */
1145 CORE_ADDR nat_collection;
1148 /* If our nat collection address is bigger than bsp, we have to get
1149 the nat collection from rnat. Otherwise, we fetch the nat
1150 collection from the computed address. */
1152 {
1154 IA64_RNAT_REGNUM,
1158 else
1161 nat_collection);
1162 }
1163 else
1164 {
1169 else
1174 }
1175 }
1176 }
1178 {
1179 ULONGEST pr;
1180 ULONGEST cfm;
1181 ULONGEST prN_val;
1182 ULONGEST prN_mask;
1188 {
1189 /* Fetch predicate register rename base from current frame
1190 marker for this frame. */
1193 /* Adjust the register number to account for register rotation. */
1194 regnum = VP16_REGNUM
1196 }
1198 byte_order);
1205 }
1206 }
1208 /* The ia64 needs to convert between various ieee floating-point formats
1209 and the special ia64 floating point register format. */
1211 static int
1213 {
1217 }
1219 static int
1223 {
1227 /* Convert to TYPE. */
1236 }
1238 static void
1241 {
1246 }
1249 /* Limit the number of skipped non-prologue instructions since examining
1250 of the prologue is expensive. */
1253 /* Given PC representing the starting address of a function, and
1254 LIM_PC which is the (sloppy) limit to which to scan when looking
1255 for a prologue, attempt to further refine this limit by using
1256 the line data in the symbol table. If successful, a better guess
1257 on where the prologue ends is returned, otherwise the previous
1258 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
1259 which will be set to indicate whether the returned limit may be
1260 used with no further scanning in the event that the function is
1261 frameless. */
1263 /* FIXME: cagney/2004-02-14: This function and logic have largely been
1264 superseded by skip_prologue_using_sal. */
1266 static CORE_ADDR
1268 {
1271 CORE_ADDR end_pc;
1273 /* The prologue can not possibly go past the function end itself,
1274 so we can already adjust LIM_PC accordingly. */
1278 /* Start off not trusting the limit. */
1283 {
1287 /* Handle the case in which compiler's optimizer/scheduler
1288 has moved instructions into the prologue. We scan ahead
1289 in the function looking for address ranges whose corresponding
1290 line number is less than or equal to the first one that we
1291 found for the function. (It can be less than when the
1292 scheduler puts a body instruction before the first prologue
1293 instruction.) */
1296 i--)
1297 {
1305 {
1307 }
1309 }
1312 {
1316 }
1317 }
1319 }
1321 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1322 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1323 || (14 <= (_regnum_) && (_regnum_) <= 31))
1324 #define imm9(_instr_) \
1325 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1326 | (((_instr_) & 0x00008000000LL) >> 20) \
1327 | (((_instr_) & 0x00000001fc0LL) >> 6))
1329 /* Allocate and initialize a frame cache. */
1333 {
1339 /* Base address. */
1355 }
1357 static CORE_ADDR
1361 {
1362 CORE_ADDR next_pc;
1364 instruction_type it;
1380 CORE_ADDR addr;
1395 /* We want to check if we have a recognizable function start before we
1396 look ahead for a prologue. */
1399 {
1400 /* alloc - start of a regular function. */
1405 /* Verify that the current cfm matches what we think is the
1406 function start. If we have somehow jumped within a function,
1407 we do not want to interpret the prologue and calculate the
1408 addresses of various registers such as the return address.
1409 We will instead treat the frame as frameless. */
1418 }
1419 else
1420 {
1421 /* Look for a leaf routine. */
1425 {
1426 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1434 {
1435 /* mov r2, r12 - beginning of leaf routine. */
1438 }
1439 }
1441 /* If we don't recognize a regular function or leaf routine, we are
1442 done. */
1444 {
1448 }
1449 }
1451 /* Loop, looking for prologue instructions, keeping track of
1452 where preserved registers were spilled. */
1454 {
1460 {
1461 /* Exit loop upon hitting a non-nop branch instruction. */
1465 }
1468 {
1469 /* Exit loop upon hitting a predicated instruction if
1470 we already have the return register or if we are frameless. */
1474 }
1476 {
1477 /* Move from BR */
1483 {
1486 }
1487 }
1490 {
1491 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1500 {
1501 /* mov rN, r12 */
1504 }
1506 {
1507 /* adds r12, -mem_stack_frame_size, r12 */
1510 }
1513 {
1515 /* adds r2, spilloffset, rFramePointer
1516 or
1517 adds r2, spilloffset, r12
1519 Get ready for stf.spill or st8.spill instructions.
1520 The address to start spilling at is loaded into r2.
1521 FIXME: Why r2? That's what gcc currently uses; it
1522 could well be different for other compilers. */
1524 /* Hmm... whether or not this will work will depend on
1525 where the pc is. If it's still early in the prologue
1526 this'll be wrong. FIXME */
1529 sp_regnum);
1530 spill_addr = saved_sp
1535 }
1538 {
1539 /* mov rN, rM where rM is an input register. */
1542 }
1545 {
1546 /* mov r12, r2 */
1549 }
1550 }
1554 {
1555 /* stf.spill [rN] = fM, imm9
1556 or
1557 stf.spill [rN] = fM */
1565 {
1570 else
1573 }
1574 }
1577 {
1578 /* mov.m rN = arM
1579 or
1580 mov.i rN = arM */
1586 {
1587 /* We have something like "mov.m r3 = ar.unat". Remember the
1588 r3 (or whatever) and watch for a store of this register... */
1591 }
1592 }
1594 {
1595 /* mov rN = pr */
1599 {
1602 }
1603 }
1607 {
1608 /* st8 [rN] = rM
1609 or
1610 st8 [rN] = rM, imm9 */
1617 {
1618 /* We've found a spill of either the UNAT register or the PR
1619 register. (Well, not exactly; what we've actually found is
1620 a spill of the register that UNAT or PR was moved to).
1621 Record that fact and move on... */
1623 {
1624 /* Track UNAT register. */
1627 }
1628 else
1629 {
1630 /* Track PR register. */
1633 }
1635 /* st8 [rN] = rM, imm9 */
1637 else
1640 }
1642 {
1643 /* Allow up to one store of each input register. */
1646 }
1649 {
1650 /* Allow an indirect store of an input register. */
1653 }
1654 }
1656 {
1657 /* One of
1658 st1 [rN] = rM
1659 st2 [rN] = rM
1660 st4 [rN] = rM
1661 st8 [rN] = rM
1662 Note that the st8 case is handled in the clause above.
1664 Advance over stores of input registers. One store per input
1665 register is permitted. */
1670 {
1673 }
1676 {
1677 /* Allow an indirect store of an input register. */
1680 }
1681 }
1683 {
1684 /* Either
1685 stfs [rN] = fM
1686 or
1687 stfd [rN] = fM
1689 Advance over stores of floating point input registers. Again
1690 one store per register is permitted. */
1694 {
1697 }
1698 }
1702 {
1703 /* st8.spill [rN] = rM
1704 or
1705 st8.spill [rN] = rM, imm9 */
1710 {
1711 /* We've found a spill of one of the preserved general purpose
1712 regs. Record the spill address and advance the spill
1713 register if appropriate. */
1716 /* st8.spill [rN] = rM, imm9 */
1718 else
1721 }
1722 }
1725 }
1727 /* If not frameless and we aren't called by skip_prologue, then we need
1728 to calculate registers for the previous frame which will be needed
1729 later. */
1732 {
1736 /* Extract the size of the rotating portion of the stack
1737 frame and the register rename base from the current
1738 frame marker. */
1745 /* Find the bof (beginning of frame). */
1751 {
1753 {
1755 }
1762 }
1764 /* For the previous argument registers we require the previous bof.
1765 If we can't find the previous cfm, then we can do nothing. */
1768 {
1771 }
1773 {
1776 }
1780 {
1786 /* The previous bof only requires subtraction of the sol (size of
1787 locals) due to the overlap between output and input of
1788 subsequent frames. */
1794 {
1796 {
1798 }
1803 else
1805 }
1807 }
1808 }
1810 /* Try and trust the lim_pc value whenever possible. */
1820 }
1822 CORE_ADDR
1824 {
1831 /* Call examine_prologue with - as third argument since we don't
1832 have a next frame pointer to send. */
1834 }
1837 /* Normal frames. */
1841 {
1846 CORE_ADDR cfm;
1857 /* We always want the bsp to point to the end of frame.
1858 This way, we can always get the beginning of frame (bof)
1859 by subtracting frame size. */
1882 }
1884 static void
1887 {
1892 /* If outermost frame, mark with null frame id. */
1897 "regular frame id: code %s, stack %s, "
1903 }
1908 {
1923 {
1927 /* We want to calculate the previous bsp as the end of the previous
1928 register stack frame. This corresponds to what the hardware bsp
1929 register will be if we pop the frame back which is why we might
1930 have been called. We know the beginning of the current frame is
1931 cache->bsp - cache->sof. This value in the previous frame points
1932 to the start of the output registers. We can calculate the end of
1933 that frame by adding the size of output:
1934 (sof (size of frame) - sol (size of locals)). */
1939 prev_bsp =
1943 }
1946 {
1957 IA64_PFS_REGNUM);
1959 }
1962 {
1963 /* If the function in question uses an automatic register (r32-r127)
1964 for the frame pointer, it'll be found by ia64_find_saved_register()
1965 above. If the function lacks one of these frame pointers, we can
1966 still provide a value since we know the size of the frame. */
1968 }
1971 {
1973 ULONGEST prN;
1976 IA64_PR_REGNUM);
1978 {
1979 /* Fetch predicate register rename base from current frame
1980 marker for this frame. */
1983 /* Adjust the register number to account for register rotation. */
1985 }
1989 }
1992 {
1994 ULONGEST unatN;
1996 IA64_UNAT_REGNUM);
2000 }
2003 {
2005 /* Find address of general register corresponding to nat bit we're
2006 interested in. */
2007 CORE_ADDR gr_addr;
2012 {
2013 /* Compute address of nat collection bits. */
2015 CORE_ADDR bsp;
2016 CORE_ADDR nat_collection;
2019 /* If our nat collection address is bigger than bsp, we have to get
2020 the nat collection from rnat. Otherwise, we fetch the nat
2021 collection from the computed address. */
2025 {
2028 }
2029 else
2033 }
2036 }
2039 {
2044 {
2047 }
2049 {
2052 }
2055 }
2058 {
2059 /* We don't know how to get the complete previous PSR, but we need it
2060 for the slot information when we unwind the pc (pc is formed of IP
2061 register plus slot information from PSR). To get the previous
2062 slot information, we mask it off the return address. */
2072 {
2075 }
2077 {
2080 }
2085 }
2088 {
2095 }
2099 {
2109 {
2113 /* FIXME: brobecker/2008-05-01: Doesn't this seem redundant
2114 with the same code above? */
2118 IA64_CFM_REGNUM);
2122 IA64_BSP_REGNUM);
2129 }
2132 }
2135 {
2139 {
2140 /* Fetch floating point register rename base from current
2141 frame marker for this frame. */
2144 /* Adjust the floating point register number to account for
2145 register rotation. */
2146 regnum = IA64_FR32_REGNUM
2148 }
2150 /* If we have stored a memory address, access the register. */
2154 /* Otherwise, punt and get the current value of the register. */
2155 else
2157 }
2158 }
2161 {
2162 NORMAL_FRAME,
2163 default_frame_unwind_stop_reason,
2166 NULL,
2167 default_frame_sniffer
2168 };
2170 /* Signal trampolines. */
2172 static void
2175 {
2180 {
2185 IA64_IP_REGNUM);
2188 IA64_CFM_REGNUM);
2191 IA64_PSR_REGNUM);
2194 IA64_BSP_REGNUM);
2197 IA64_RNAT_REGNUM);
2200 IA64_CCV_REGNUM);
2203 IA64_UNAT_REGNUM);
2206 IA64_FPSR_REGNUM);
2209 IA64_PFS_REGNUM);
2212 IA64_LC_REGNUM);
2223 }
2224 }
2228 {
2240 /* Note that frame size is hard-coded below. We cannot calculate it
2241 via prologue examination. */
2255 }
2257 static void
2260 {
2270 "sigtramp frame id: code %s, stack %s, "
2276 }
2281 {
2291 {
2296 {
2300 }
2303 }
2307 {
2317 }
2320 {
2327 }
2328 }
2330 static int
2334 {
2337 {
2342 }
2345 }
2348 {
2349 SIGTRAMP_FRAME,
2350 default_frame_unwind_stop_reason,
2351 ia64_sigtramp_frame_this_id,
2352 ia64_sigtramp_frame_prev_register,
2353 NULL,
2354 ia64_sigtramp_frame_sniffer
2355 };
2357 \f
2359 static CORE_ADDR
2361 {
2365 }
2368 {
2370 ia64_frame_base_address,
2371 ia64_frame_base_address,
2372 ia64_frame_base_address
2373 };
2375 #ifdef HAVE_LIBUNWIND_IA64_H
2377 struct ia64_unwind_table_entry
2378 {
2379 unw_word_t start_offset;
2380 unw_word_t end_offset;
2381 unw_word_t info_offset;
2382 };
2386 {
2388 }
2390 /* Skip over a designated number of registers in the backing
2391 store, remembering every 64th position is for NAT. */
2394 {
2400 }
2402 /* Gdb ia64-libunwind-tdep callback function to convert from an ia64 gdb
2403 register number to a libunwind register number. */
2404 static int
2406 {
2431 else
2433 }
2435 /* Gdb ia64-libunwind-tdep callback function to convert from a libunwind
2436 register number to a ia64 gdb register number. */
2437 static int
2439 {
2462 else
2464 }
2466 /* Gdb ia64-libunwind-tdep callback function to reveal if register is
2467 a float register or not. */
2468 static int
2470 {
2472 }
2474 /* Libunwind callback accessor function for general registers. */
2475 static int
2478 {
2484 /* We never call any libunwind routines that need to write registers. */
2488 {
2490 /* Libunwind expects to see the pc value which means the slot number
2491 from the psr must be merged with the ip word address. */
2498 /* Libunwind expects to see the beginning of the current
2499 register frame so we must account for the fact that
2500 ptrace() will return a value for bsp that points *after*
2501 the current register frame. */
2509 /* Libunwind wants bspstore to be after the current register frame.
2510 This is what ptrace() and gdb treats as the regular bsp value. */
2515 /* For all other registers, just unwind the value directly. */
2518 }
2527 }
2529 /* Libunwind callback accessor function for floating-point registers. */
2530 static int
2533 {
2537 /* We never call any libunwind routines that need to write registers. */
2543 }
2545 /* Libunwind callback accessor function for top-level rse registers. */
2546 static int
2549 {
2555 /* We never call any libunwind routines that need to write registers. */
2559 {
2561 /* Libunwind expects to see the pc value which means the slot number
2562 from the psr must be merged with the ip word address. */
2569 /* Libunwind expects to see the beginning of the current
2570 register frame so we must account for the fact that
2571 ptrace() will return a value for bsp that points *after*
2572 the current register frame. */
2580 /* Libunwind wants bspstore to be after the current register frame.
2581 This is what ptrace() and gdb treats as the regular bsp value. */
2586 /* For all other registers, just unwind the value directly. */
2589 }
2599 }
2601 /* Libunwind callback accessor function for top-level fp registers. */
2602 static int
2605 {
2609 /* We never call any libunwind routines that need to write registers. */
2615 }
2617 /* Libunwind callback accessor function for accessing memory. */
2618 static int
2622 {
2624 {
2630 else
2633 }
2635 /* XXX do we need to normalize byte-order here? */
2638 else
2640 }
2642 /* Call low-level function to access the kernel unwind table. */
2645 {
2646 /* FIXME drow/2005-09-10: This code used to call
2647 ia64_linux_xfer_unwind_table directly to fetch the unwind table
2648 for the currently running ia64-linux kernel. That data should
2649 come from the core file and be accessed via the auxv vector; if
2650 we want to preserve fall back to the running kernel's table, then
2651 we should find a way to override the corefile layer's
2652 xfer_partial method. */
2655 NULL);
2656 }
2658 /* Get the kernel unwind table. */
2659 static int
2661 {
2665 {
2675 }
2697 }
2699 /* Find the unwind table entry for a specified address. */
2700 static int
2703 {
2707 CORE_ADDR load_base;
2719 {
2721 {
2734 }
2735 }
2740 /* Verify that the segment that contains the IP also contains
2741 the static unwind table. If not, we may be in the Linux kernel's
2742 DSO gate page in which case the unwind table is another segment.
2743 Otherwise, we are dealing with runtime-generated code, for which we
2744 have no info here. */
2748 {
2751 {
2754 {
2756 /* Get the segbase from the section containing the
2757 libunwind table. */
2759 }
2760 }
2763 }
2775 }
2777 /* Libunwind callback accessor function to acquire procedure unwind-info. */
2778 static int
2781 {
2783 unw_dyn_info_t di;
2788 {
2789 /* XXX This only works if the host and the target architecture are
2790 both ia64 and if the have (more or less) the same kernel
2791 version. */
2797 "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s,"
2805 }
2806 else
2807 {
2814 "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s,"
2822 }
2825 arg);
2827 /* We no longer need the dyn info storage so free it. */
2831 }
2833 /* Libunwind callback accessor function for cleanup. */
2834 static void
2837 {
2838 /* Nothing required for now. */
2839 }
2841 /* Libunwind callback accessor function to get head of the dynamic
2842 unwind-info registration list. */
2843 static int
2846 {
2849 unw_dyn_info_t di;
2856 {
2863 {
2865 /* We no longer need the dyn info storage so free it. */
2869 {
2872 "dynamic unwind table in objfile %s "
2878 }
2879 }
2880 }
2882 }
2885 /* Frame interface functions for libunwind. */
2887 static void
2890 {
2895 CORE_ADDR bsp;
2899 {
2902 }
2904 /* We must add the bsp as the special address for frame comparison
2905 purposes. */
2913 "libunwind frame id: code %s, stack %s, "
2919 }
2924 {
2935 /* Let libunwind do most of the work. */
2939 {
2940 ULONGEST prN_val;
2943 {
2945 ULONGEST cfm;
2947 /* Fetch predicate register rename base from current frame
2948 marker for this frame. */
2952 /* Adjust the register number to account for register rotation. */
2954 }
2958 }
2961 {
2962 ULONGEST unatN_val;
2967 }
2970 {
2974 /* We want to calculate the previous bsp as the end of the previous
2975 register stack frame. This corresponds to what the hardware bsp
2976 register will be if we pop the frame back which is why we might
2977 have been called. We know that libunwind will pass us back the
2978 beginning of the current frame so we should just add sof to it. */
2982 IA64_CFM_REGNUM);
2988 }
2989 else
2991 }
2993 static int
2997 {
3003 }
3006 {
3007 NORMAL_FRAME,
3008 default_frame_unwind_stop_reason,
3009 ia64_libunwind_frame_this_id,
3010 ia64_libunwind_frame_prev_register,
3011 NULL,
3012 ia64_libunwind_frame_sniffer,
3013 libunwind_frame_dealloc_cache
3014 };
3016 static void
3020 {
3024 CORE_ADDR bsp;
3029 {
3032 }
3034 /* We must add the bsp as the special address for frame comparison
3035 purposes. */
3039 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
3044 "libunwind sigtramp frame id: code %s, "
3050 }
3055 {
3059 CORE_ADDR prev_ip;
3061 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
3062 method of getting previous registers. */
3064 IA64_IP_REGNUM);
3069 {
3072 regnum);
3073 }
3074 else
3076 }
3078 static int
3082 {
3084 {
3088 }
3089 else
3091 }
3094 {
3095 SIGTRAMP_FRAME,
3096 default_frame_unwind_stop_reason,
3097 ia64_libunwind_sigtramp_frame_this_id,
3098 ia64_libunwind_sigtramp_frame_prev_register,
3099 NULL,
3100 ia64_libunwind_sigtramp_frame_sniffer
3101 };
3103 /* Set of libunwind callback acccessor functions. */
3104 unw_accessors_t ia64_unw_accessors =
3105 {
3106 ia64_find_proc_info_x,
3107 ia64_put_unwind_info,
3108 ia64_get_dyn_info_list,
3109 ia64_access_mem,
3110 ia64_access_reg,
3111 ia64_access_fpreg,
3112 /* resume */
3113 /* get_proc_name */
3114 };
3116 /* Set of special libunwind callback acccessor functions specific for accessing
3117 the rse registers. At the top of the stack, we want libunwind to figure out
3118 how to read r32 - r127. Though usually they are found sequentially in
3119 memory starting from $bof, this is not always true. */
3120 unw_accessors_t ia64_unw_rse_accessors =
3121 {
3122 ia64_find_proc_info_x,
3123 ia64_put_unwind_info,
3124 ia64_get_dyn_info_list,
3125 ia64_access_mem,
3126 ia64_access_rse_reg,
3127 ia64_access_rse_fpreg,
3128 /* resume */
3129 /* get_proc_name */
3130 };
3132 /* Set of ia64-libunwind-tdep gdb callbacks and data for generic
3133 ia64-libunwind-tdep code to use. */
3135 {
3136 ia64_gdb2uw_regnum,
3137 ia64_uw2gdb_regnum,
3138 ia64_is_fpreg,
3141 };
3145 static int
3147 {
3150 /* Don't use the struct convention for anything but structure,
3151 union, or array types. */
3157 /* HFAs are structures (or arrays) consisting entirely of floating
3158 point values of the same length. Up to 8 of these are returned
3159 in registers. Don't use the struct convention when this is the
3160 case. */
3166 /* Other structs of length 32 or less are returned in r8-r11.
3167 Don't use the struct convention for those either. */
3169 }
3171 /* Return non-zero if TYPE is a structure or union type. */
3173 static int
3175 {
3178 }
3180 static void
3183 {
3189 {
3196 {
3201 regnum++;
3202 }
3203 }
3205 {
3206 /* This is an integral value, and its size is less than 8 bytes.
3207 These values are LSB-aligned, so extract the relevant bytes,
3208 and copy them into VALBUF. */
3209 /* brobecker/2005-12-30: Actually, all integral values are LSB aligned,
3210 so I suppose we should also add handling here for integral values
3211 whose size is greater than 8. But I wasn't able to create such
3212 a type, neither in C nor in Ada, so not worrying about these yet. */
3214 ULONGEST val;
3218 }
3219 else
3220 {
3221 ULONGEST val;
3229 {
3230 ULONGEST regval;
3234 regnum++;
3235 }
3238 {
3241 }
3242 }
3243 }
3245 static void
3248 {
3254 {
3261 {
3266 regnum++;
3267 }
3268 }
3269 else
3270 {
3278 {
3279 ULONGEST val;
3283 regnum++;
3284 }
3287 {
3288 ULONGEST val;
3291 }
3292 }
3293 }
3295 static enum return_value_convention
3299 {
3303 {
3306 }
3309 {
3312 }
3316 else
3318 }
3320 static int
3322 {
3324 {
3328 else
3329 {
3332 }
3335 return
3337 etp);
3340 {
3348 }
3353 }
3354 }
3356 /* Determine if the given type is one of the floating point types or
3357 and HFA (which is a struct, array, or combination thereof whose
3358 bottom-most elements are all of the same floating point type). */
3362 {
3366 }
3369 /* Return 1 if the alignment of T is such that the next even slot
3370 should be used. Return 0, if the next available slot should
3371 be used. (See section 8.5.1 of the IA-64 Software Conventions
3372 and Runtime manual). */
3374 static int
3376 {
3378 {
3383 else
3386 return
3389 {
3397 }
3400 }
3401 }
3403 /* Attempt to find (and return) the global pointer for the given
3404 function.
3406 This is a rather nasty bit of code searchs for the .dynamic section
3407 in the objfile corresponding to the pc of the function we're trying
3408 to call. Once it finds the addresses at which the .dynamic section
3409 lives in the child process, it scans the Elf64_Dyn entries for a
3410 DT_PLTGOT tag. If it finds one of these, the corresponding
3411 d_un.d_ptr value is the global pointer. */
3413 static CORE_ADDR
3415 CORE_ADDR faddr)
3416 {
3422 {
3426 {
3429 }
3432 {
3439 {
3441 LONGEST tag;
3450 {
3451 CORE_ADDR global_pointer;
3457 byte_order);
3459 /* The payoff... */
3461 }
3467 }
3468 }
3469 }
3471 }
3473 /* Attempt to find (and return) the global pointer for the given
3474 function. We first try the find_global_pointer_from_solib routine
3475 from the gdbarch tdep vector, if provided. And if that does not
3476 work, then we try ia64_find_global_pointer_from_dynamic_section. */
3478 static CORE_ADDR
3480 {
3489 }
3491 /* Given a function's address, attempt to find (and return) the
3492 corresponding (canonical) function descriptor. Return 0 if
3493 not found. */
3494 static CORE_ADDR
3496 {
3500 /* Return early if faddr is already a function descriptor. */
3506 {
3509 {
3512 }
3515 {
3522 {
3524 LONGEST faddr2;
3536 }
3537 }
3538 }
3540 }
3542 /* Attempt to find a function descriptor corresponding to the
3543 given address. If none is found, construct one on the
3544 stack using the address at fdaptr. */
3546 static CORE_ADDR
3548 {
3551 CORE_ADDR fdesc;
3556 {
3557 ULONGEST global_pointer;
3573 }
3576 }
3578 /* Use the following routine when printing out function pointers
3579 so the user can see the function address rather than just the
3580 function descriptor. */
3581 static CORE_ADDR
3584 {
3591 /* check if ADDR points to a function descriptor. */
3595 /* Normally, functions live inside a section that is executable.
3596 So, if ADDR points to a non-executable section, then treat it
3597 as a function descriptor and return the target address iff
3598 the target address itself points to a section that is executable.
3599 Check first the memory of the whole length of 8 bytes is readable. */
3602 {
3608 }
3610 /* There are also descriptors embedded in vtables. */
3612 {
3620 }
3623 }
3625 static CORE_ADDR
3627 {
3629 }
3631 /* The default "allocate_new_rse_frame" ia64_infcall_ops routine for ia64. */
3633 static void
3635 {
3651 }
3653 /* The default "store_argument_in_slot" ia64_infcall_ops routine for
3654 ia64. */
3656 static void
3659 {
3661 }
3663 /* The default "set_function_addr" ia64_infcall_ops routine for ia64. */
3665 static void
3667 {
3668 /* Nothing needed. */
3669 }
3671 static CORE_ADDR
3675 function_call_return_method return_method,
3676 CORE_ADDR struct_addr)
3677 {
3686 ULONGEST bsp;
3692 /* Count the number of slots needed for the arguments. */
3694 {
3700 nslots++;
3703 nfuncargs++;
3706 }
3708 /* Divvy up the slots between the RSE and the memory stack. */
3712 /* Allocate a new RSE frame. */
3716 /* We will attempt to find function descriptors in the .opd segment,
3717 but if we can't we'll construct them ourselves. That being the
3718 case, we'll need to reserve space on the stack for them. */
3722 /* Adjust the stack pointer to it's new value. The calling conventions
3723 require us to have 16 bytes of scratch, plus whatever space is
3724 necessary for the memory slots and our function descriptors. */
3728 /* Place the arguments where they belong. The arguments will be
3729 either placed in the RSE backing store or on the memory stack.
3730 In addition, floating point arguments or HFAs are placed in
3731 floating point registers. */
3735 {
3742 /* Special handling for function parameters. */
3746 {
3756 else
3758 slotnum++;
3760 }
3762 /* Normal slots. */
3764 /* Skip odd slot if necessary... */
3766 slotnum++;
3770 {
3775 {
3776 /* Integral types are LSB-aligned, so we have to be careful
3777 to insert the argument on the correct side of the buffer.
3778 This is why we use store_unsigned_integer. */
3779 store_unsigned_integer
3782 byte_order));
3783 }
3784 else
3785 {
3786 /* This is either an 8bit integral type, or an aggregate.
3787 For 8bit integral type, there is no problem, we just
3788 copy the value over.
3790 For aggregates, the only potentially tricky portion
3791 is to write the last one if it is less than 8 bytes.
3792 In this case, the data is Byte0-aligned. Happy news,
3793 this means that we don't need to differentiate the
3794 handling of 8byte blocks and less-than-8bytes blocks. */
3797 }
3802 else
3807 slotnum++;
3808 }
3810 /* Handle floating point types (including HFAs). */
3813 {
3817 {
3823 floatreg++;
3826 }
3827 }
3828 }
3830 /* Store the struct return value in r8 if necessary. */
3840 /* The following is not necessary on HP-UX, because we're using
3841 a dummy code sequence pushed on the stack to make the call, and
3842 this sequence doesn't need b0 to be set in order for our dummy
3843 breakpoint to be hit. Nonetheless, this doesn't interfere, and
3844 it's needed for other OSes, so we do this unconditionaly. */
3852 }
3855 {
3856 ia64_allocate_new_rse_frame,
3857 ia64_store_argument_in_slot,
3858 ia64_set_function_addr
3859 };
3861 static struct frame_id
3863 {
3881 }
3883 static CORE_ADDR
3885 {
3897 }
3899 static int
3901 {
3904 }
3906 /* The default "size_of_register_frame" gdbarch_tdep routine for ia64. */
3908 static int
3910 {
3912 }
3916 {
3920 /* If there is already a candidate, use it. */
3930 /* According to the ia64 specs, instructions that store long double
3931 floats in memory use a long-double format different than that
3932 used in the floating registers. The memory format matches the
3933 x86 extended float format which is 80 bits. An OS may choose to
3934 use this format (e.g. GNU/Linux) or choose to use a different
3935 format for storing long doubles (e.g. HPUX). In the latter case,
3936 the setting of the format may be moved/overridden in an
3937 OS-specific tdep file. */
3971 ia64_memory_insert_breakpoint);
3973 ia64_memory_remove_breakpoint);
3979 /* Settings for calling functions in the inferior. */
3986 #ifdef HAVE_LIBUNWIND_IA64_H
3992 #else
3994 #endif
3998 /* Settings that should be unnecessary. */
4003 ia64_convert_from_func_ptr_addr);
4005 /* The virtual table contains 16-byte descriptors, not pointers to
4006 descriptors. */
4009 /* Hook in ABI-specific overrides, if they have been registered. */
4013 }
4015 void
4017 {
4019 }