3 #ld
: -shared --plt
-align=0 tlsdll
.so
5 #target
: powerpc64
*-*-*
9 Disassembly of section \
.text
:
11 .* <.*\
.plt_call\
..*>:
12 .*: (04 10 .. ..|
.. .. 10 04) pld r12
,.*
13 .*: (e5
80 .. ..|
.. .. 80 e5
)
14 .*: (7d 89 03 a6|a6
03 89 7d) mtctr r12
15 .*: (4e
80 04 20|
20 04 80 4e
) bctr
16 .*: (f8
41 00 18|
18 00 41 f8
) std r2
,24\
(r1\
)
17 .*: (e9
82 .. ..|
.. .. 82 e9
) ld r12
,.*\
(r2\
)
18 .*: (7d 89 03 a6|a6
03 89 7d) mtctr r12
19 .*: (4e
80 04 20|
20 04 80 4e
) bctr
21 .* <.*\
.plt_call\
.__tls_get_addr_opt
.*>:
22 .*: (e8
03 00 00|
00 00 03 e8
) ld r0
,0\
(r3\
)
23 .*: (e9
83 00 08|
08 00 83 e9
) ld r12
,8\
(r3\
)
24 .*: (2c
20 00 00|
00 00 20 2c
) cmpdi r0
,0
25 .*: (7c
60 1b 78|
78 1b 60 7c
) mr r0
,r3
26 .*: (7c
6c
6a
14|
14 6a
6c
7c
) add r3
,r12
,r13
27 .*: (4d 82 00 20|
20 00 82 4d) beqlr
28 .*: (7c
03 03 78|
78 03 03 7c
) mr r3
,r0
29 .*: (60 00 00 00|
00 00 00 60) nop
30 .*: (04 10 .. ..|
.. .. 10 04) pld r12
,.*
31 .*: (e5
80 .. ..|
.. .. 80 e5
)
32 .*: (7d 89 03 a6|a6
03 89 7d) mtctr r12
33 .*: (4e
80 04 20|
20 04 80 4e
) bctr
34 .*: (e8
03 00 00|
00 00 03 e8
) ld r0
,0\
(r3\
)
35 .*: (e9
83 00 08|
08 00 83 e9
) ld r12
,8\
(r3\
)
36 .*: (2c
20 00 00|
00 00 20 2c
) cmpdi r0
,0
37 .*: (7c
60 1b 78|
78 1b 60 7c
) mr r0
,r3
38 .*: (7c
6c
6a
14|
14 6a
6c
7c
) add r3
,r12
,r13
39 .*: (4d 82 00 20|
20 00 82 4d) beqlr
40 .*: (7c
03 03 78|
78 03 03 7c
) mr r3
,r0
41 .*: (7c
08 02 a6|a6
02 08 7c
) mflr r0
42 .*: (f8
01 00 08|
08 00 01 f8
) std r0
,8\
(r1\
)
43 .*: (f8
41 00 18|
18 00 41 f8
) std r2
,24\
(r1\
)
44 .*: (e9
82 .. ..|
.. .. 82 e9
) ld r12
,.*\
(r2\
)
45 .*: (7d 89 03 a6|a6
03 89 7d) mtctr r12
46 .*: (4e
80 04 21|
21 04 80 4e
) bctrl
47 .*: (e8
41 00 18|
18 00 41 e8
) ld r2
,24\
(r1\
)
48 .*: (e8
01 00 08|
08 00 01 e8
) ld r0
,8\
(r1\
)
49 .*: (7c
08 03 a6|a6
03 08 7c
) mtlr r0
50 .*: (4e
80 00 20|
20 00 80 4e
) blr
54 .*: (06 10 .. ..|
.. .. 10 06) pla r3
,.*
55 .*: (38 60 .. ..|
.. .. 60 38)
56 .*: (4b ff
.. ..|
.. .. ff
4b) bl
.* <.*\
.plt_call\
.__tls_get_addr_opt
[^\
+]*>
57 .*: (60 00 00 00|
00 00 00 60) nop
58 .*: (38 62 .. ..|
.. .. 62 38) addi r3
,r2
,.*
59 .*: (4b ff
.. ..|
.. .. ff
4b) bl
.* <.*\
.plt_call\
.__tls_get_addr_opt
.*\
+0x30>
60 .*: (60 00 00 00|
00 00 00 60) nop
61 .*: (4b ff
.. ..|
.. .. ff
4b) bl
.* <.*\
.plt_call\
..*:[^\
+]*>
62 .*: (4b ff
.. ..|
.. .. ff
4b) bl
.* <.*.plt_call\
..*:.*\
+0x10>
63 .*: (e8
41 00 18|
18 00 41 e8
) ld r2
,24\
(r1\
)
66 .*: (06 10 00 00|
00 00 10 06) pla r3
,8.*
67 .*: (38 60 00 08|
08 00 60 38)
68 .*: (4e
80 00 20|
20 00 80 4e
) blr
69 .*: (60 00 00 00|
00 00 00 60) nop
70 .*: (00 00 00 00|
90 02 01 00) .*
71 .*: (00 01 02 90|
00 00 00 00) .*
73 .* <__glink_PLTresolve
>:
74 .*: (7c
08 02 a6|a6
02 08 7c
) mflr r0
75 .*: (42 9f 00 05|
05 00 9f 42) bcl
20,4\
*cr7\
+so
,.* <__glink_PLTresolve\
+0x8>
76 .*: (7d 68 02 a6|a6
02 68 7d) mflr r11
77 .*: (7c
08 03 a6|a6
03 08 7c
) mtlr r0
78 .*: (e8
0b ff f0|f0 ff
0b e8
) ld r0
,-16\
(r11\
)
79 .*: (7d 8b 60 50|
50 60 8b 7d) subf r12
,r11
,r12
80 .*: (7d 60 5a
14|
14 5a
60 7d) add r11
,r0
,r11
81 .*: (38 0c ff d4|d4 ff
0c
38) addi r0
,r12
,-44
82 .*: (e9
8b 00 00|
00 00 8b e9
) ld r12
,0\
(r11\
)
83 .*: (78 00 f0
82|
82 f0
00 78) srdi r0
,r0
,2
84 .*: (7d 89 03 a6|a6
03 89 7d) mtctr r12
85 .*: (e9
6b 00 08|
08 00 6b e9
) ld r11
,8\
(r11\
)
86 .*: (4e
80 04 20|
20 04 80 4e
) bctr
88 .* <__tls_get_addr_opt
@plt>:
89 .*: (4b ff
.. ..|
.. .. ff
4b) b
.* <__glink_PLTresolve
>
