opcodes/lm32-desc.h

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* CPU data header for lm32.
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5
   6 Copyright (C) 1996-2020 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   9
  10    This file is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3, or (at your option)
  13    any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with this program; if not, write to the Free Software Foundation, Inc.,
  22    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #ifndef LM32_CPU_H
  27 #define LM32_CPU_H
  28
  29 #ifdef __cplusplus
  30 extern "C" {
  31 #endif
  32
  33 #define CGEN_ARCH lm32
  34
  35 /* Given symbol S, return lm32_cgen_<S>.  */
  36 #define CGEN_SYM(s) lm32##_cgen_##s
  37
  38
  39 /* Selected cpu families.  */
  40 #define HAVE_CPU_LM32BF
  41
  42 #define CGEN_INSN_LSB0_P 1
  43
  44 /* Minimum size of any insn (in bytes).  */
  45 #define CGEN_MIN_INSN_SIZE 4
  46
  47 /* Maximum size of any insn (in bytes).  */
  48 #define CGEN_MAX_INSN_SIZE 4
  49
  50 #define CGEN_INT_INSN_P 1
  51
  52 /* Maximum number of syntax elements in an instruction.  */
  53 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
  54
  55 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  56    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  57    we can't hash on everything up to the space.  */
  58 #define CGEN_MNEMONIC_OPERANDS
  59
  60 /* Maximum number of fields in an instruction.  */
  61 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 5
  62
  63 /* Enums.  */
  64
  65 /* Enum declaration for opcodes.  */
  66 typedef enum opcodes {
  67   OP_ADD = 45, OP_ADDI = 13, OP_AND = 40, OP_ANDI = 8
  68  , OP_ANDHI = 24, OP_B = 48, OP_BI = 56, OP_BE = 17
  69  , OP_BG = 18, OP_BGE = 19, OP_BGEU = 20, OP_BGU = 21
  70  , OP_BNE = 23, OP_CALL = 54, OP_CALLI = 62, OP_CMPE = 57
  71  , OP_CMPEI = 25, OP_CMPG = 58, OP_CMPGI = 26, OP_CMPGE = 59
  72  , OP_CMPGEI = 27, OP_CMPGEU = 60, OP_CMPGEUI = 28, OP_CMPGU = 61
  73  , OP_CMPGUI = 29, OP_CMPNE = 63, OP_CMPNEI = 31, OP_DIVU = 35
  74  , OP_LB = 4, OP_LBU = 16, OP_LH = 7, OP_LHU = 11
  75  , OP_LW = 10, OP_MODU = 49, OP_MUL = 34, OP_MULI = 2
  76  , OP_NOR = 33, OP_NORI = 1, OP_OR = 46, OP_ORI = 14
  77  , OP_ORHI = 30, OP_RAISE = 43, OP_RCSR = 36, OP_SB = 12
  78  , OP_SEXTB = 44, OP_SEXTH = 55, OP_SH = 3, OP_SL = 47
  79  , OP_SLI = 15, OP_SR = 37, OP_SRI = 5, OP_SRU = 32
  80  , OP_SRUI = 0, OP_SUB = 50, OP_SW = 22, OP_USER = 51
  81  , OP_WCSR = 52, OP_XNOR = 41, OP_XNORI = 9, OP_XOR = 38
  82  , OP_XORI = 6
  83 } OPCODES;
  84
  85 /* Attributes.  */
  86
  87 /* Enum declaration for machine type selection.  */
  88 typedef enum mach_attr {
  89   MACH_BASE, MACH_LM32, MACH_MAX
  90 } MACH_ATTR;
  91
  92 /* Enum declaration for instruction set selection.  */
  93 typedef enum isa_attr {
  94   ISA_LM32, ISA_MAX
  95 } ISA_ATTR;
  96
  97 /* Number of architecture variants.  */
  98 #define MAX_ISAS  1
  99 #define MAX_MACHS ((int) MACH_MAX)
 100
 101 /* Ifield support.  */
 102
 103 /* Ifield attribute indices.  */
 104
 105 /* Enum declaration for cgen_ifld attrs.  */
 106 typedef enum cgen_ifld_attr {
 107   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 108  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 109  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 110 } CGEN_IFLD_ATTR;
 111
 112 /* Number of non-boolean elements in cgen_ifld_attr.  */
 113 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 114
 115 /* cgen_ifld attribute accessor macros.  */
 116 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
 117 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
 118 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
 119 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
 120 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
 121 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
 122 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
 123
 124 /* Enum declaration for lm32 ifield types.  */
 125 typedef enum ifield_type {
 126   LM32_F_NIL, LM32_F_ANYOF, LM32_F_OPCODE, LM32_F_R0
 127  , LM32_F_R1, LM32_F_R2, LM32_F_RESV0, LM32_F_SHIFT
 128  , LM32_F_IMM, LM32_F_UIMM, LM32_F_CSR, LM32_F_USER
 129  , LM32_F_EXCEPTION, LM32_F_BRANCH, LM32_F_CALL, LM32_F_MAX
 130 } IFIELD_TYPE;
 131
 132 #define MAX_IFLD ((int) LM32_F_MAX)
 133
 134 /* Hardware attribute indices.  */
 135
 136 /* Enum declaration for cgen_hw attrs.  */
 137 typedef enum cgen_hw_attr {
 138   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 139  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 140 } CGEN_HW_ATTR;
 141
 142 /* Number of non-boolean elements in cgen_hw_attr.  */
 143 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 144
 145 /* cgen_hw attribute accessor macros.  */
 146 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
 147 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
 148 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
 149 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
 150 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
 151
 152 /* Enum declaration for lm32 hardware types.  */
 153 typedef enum cgen_hw_type {
 154   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 155  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CSR
 156  , HW_MAX
 157 } CGEN_HW_TYPE;
 158
 159 #define MAX_HW ((int) HW_MAX)
 160
 161 /* Operand attribute indices.  */
 162
 163 /* Enum declaration for cgen_operand attrs.  */
 164 typedef enum cgen_operand_attr {
 165   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 166  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 167  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 168 } CGEN_OPERAND_ATTR;
 169
 170 /* Number of non-boolean elements in cgen_operand_attr.  */
 171 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 172
 173 /* cgen_operand attribute accessor macros.  */
 174 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 175 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
 176 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
 177 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
 178 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
 179 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
 180 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
 181 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
 182 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
 183
 184 /* Enum declaration for lm32 operand types.  */
 185 typedef enum cgen_operand_type {
 186   LM32_OPERAND_PC, LM32_OPERAND_R0, LM32_OPERAND_R1, LM32_OPERAND_R2
 187  , LM32_OPERAND_SHIFT, LM32_OPERAND_IMM, LM32_OPERAND_UIMM, LM32_OPERAND_BRANCH
 188  , LM32_OPERAND_CALL, LM32_OPERAND_CSR, LM32_OPERAND_USER, LM32_OPERAND_EXCEPTION
 189  , LM32_OPERAND_HI16, LM32_OPERAND_LO16, LM32_OPERAND_GP16, LM32_OPERAND_GOT16
 190  , LM32_OPERAND_GOTOFFHI16, LM32_OPERAND_GOTOFFLO16, LM32_OPERAND_MAX
 191 } CGEN_OPERAND_TYPE;
 192
 193 /* Number of operands types.  */
 194 #define MAX_OPERANDS 18
 195
 196 /* Maximum number of operands referenced by any insn.  */
 197 #define MAX_OPERAND_INSTANCES 5
 198
 199 /* Insn attribute indices.  */
 200
 201 /* Enum declaration for cgen_insn attrs.  */
 202 typedef enum cgen_insn_attr {
 203   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 204  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 205  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
 206  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 207 } CGEN_INSN_ATTR;
 208
 209 /* Number of non-boolean elements in cgen_insn_attr.  */
 210 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 211
 212 /* cgen_insn attribute accessor macros.  */
 213 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
 214 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
 215 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
 216 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
 217 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
 218 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
 219 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
 220 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
 221 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
 222 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
 223 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
 224
 225 /* cgen.h uses things we just defined.  */
 226 #include "opcode/cgen.h"
 227
 228 extern const struct cgen_ifld lm32_cgen_ifld_table[];
 229
 230 /* Attributes.  */
 231 extern const CGEN_ATTR_TABLE lm32_cgen_hardware_attr_table[];
 232 extern const CGEN_ATTR_TABLE lm32_cgen_ifield_attr_table[];
 233 extern const CGEN_ATTR_TABLE lm32_cgen_operand_attr_table[];
 234 extern const CGEN_ATTR_TABLE lm32_cgen_insn_attr_table[];
 235
 236 /* Hardware decls.  */
 237
 238 extern CGEN_KEYWORD lm32_cgen_opval_h_gr;
 239 extern CGEN_KEYWORD lm32_cgen_opval_h_csr;
 240
 241 extern const CGEN_HW_ENTRY lm32_cgen_hw_table[];
 242
 243
 244
 245    #ifdef __cplusplus
 246    }
 247    #endif
 248
 249 #endif /* LM32_CPU_H */