opcodes/mt-desc.h

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* CPU data header for mt.
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5
   6 Copyright (C) 1996-2020 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   9
  10    This file is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3, or (at your option)
  13    any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with this program; if not, write to the Free Software Foundation, Inc.,
  22    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #ifndef MT_CPU_H
  27 #define MT_CPU_H
  28
  29 #ifdef __cplusplus
  30 extern "C" {
  31 #endif
  32
  33 #define CGEN_ARCH mt
  34
  35 /* Given symbol S, return mt_cgen_<S>.  */
  36 #define CGEN_SYM(s) mt##_cgen_##s
  37
  38
  39 /* Selected cpu families.  */
  40 #define HAVE_CPU_MS1BF
  41 #define HAVE_CPU_MS1_003BF
  42 #define HAVE_CPU_MS2BF
  43
  44 #define CGEN_INSN_LSB0_P 1
  45
  46 /* Minimum size of any insn (in bytes).  */
  47 #define CGEN_MIN_INSN_SIZE 4
  48
  49 /* Maximum size of any insn (in bytes).  */
  50 #define CGEN_MAX_INSN_SIZE 4
  51
  52 #define CGEN_INT_INSN_P 1
  53
  54 /* Maximum number of syntax elements in an instruction.  */
  55 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 40
  56
  57 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  58    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  59    we can't hash on everything up to the space.  */
  60 #define CGEN_MNEMONIC_OPERANDS
  61
  62 /* Maximum number of fields in an instruction.  */
  63 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 14
  64
  65 /* Enums.  */
  66
  67 /* Enum declaration for msys enums.  */
  68 typedef enum insn_msys {
  69   MSYS_NO, MSYS_YES
  70 } INSN_MSYS;
  71
  72 /* Enum declaration for opc enums.  */
  73 typedef enum insn_opc {
  74   OPC_ADD = 0, OPC_ADDU = 1, OPC_SUB = 2, OPC_SUBU = 3
  75  , OPC_MUL = 4, OPC_AND = 8, OPC_OR = 9, OPC_XOR = 10
  76  , OPC_NAND = 11, OPC_NOR = 12, OPC_XNOR = 13, OPC_LDUI = 14
  77  , OPC_LSL = 16, OPC_LSR = 17, OPC_ASR = 18, OPC_BRLT = 24
  78  , OPC_BRLE = 25, OPC_BREQ = 26, OPC_JMP = 27, OPC_JAL = 28
  79  , OPC_BRNEQ = 29, OPC_DBNZ = 30, OPC_LOOP = 31, OPC_LDW = 32
  80  , OPC_STW = 33, OPC_EI = 48, OPC_DI = 49, OPC_SI = 50
  81  , OPC_RETI = 51, OPC_BREAK = 52, OPC_IFLUSH = 53
  82 } INSN_OPC;
  83
  84 /* Enum declaration for msopc enums.  */
  85 typedef enum insn_msopc {
  86   MSOPC_LDCTXT, MSOPC_LDFB, MSOPC_STFB, MSOPC_FBCB
  87  , MSOPC_MFBCB, MSOPC_FBCCI, MSOPC_FBRCI, MSOPC_FBCRI
  88  , MSOPC_FBRRI, MSOPC_MFBCCI, MSOPC_MFBRCI, MSOPC_MFBCRI
  89  , MSOPC_MFBRRI, MSOPC_FBCBDR, MSOPC_RCFBCB, MSOPC_MRCFBCB
  90  , MSOPC_CBCAST, MSOPC_DUPCBCAST, MSOPC_WFBI, MSOPC_WFB
  91  , MSOPC_RCRISC, MSOPC_FBCBINC, MSOPC_RCXMODE, MSOPC_INTLVR
  92  , MSOPC_WFBINC, MSOPC_MWFBINC, MSOPC_WFBINCR, MSOPC_MWFBINCR
  93  , MSOPC_FBCBINCS, MSOPC_MFBCBINCS, MSOPC_FBCBINCRS, MSOPC_MFBCBINCRS
  94 } INSN_MSOPC;
  95
  96 /* Enum declaration for imm enums.  */
  97 typedef enum insn_imm {
  98   IMM_NO, IMM_YES
  99 } INSN_IMM;
 100
 101 /* Enum declaration for .  */
 102 typedef enum msys_syms {
 103   H_NIL_DUP = 1, H_NIL_XX = 0
 104 } MSYS_SYMS;
 105
 106 /* Attributes.  */
 107
 108 /* Enum declaration for machine type selection.  */
 109 typedef enum mach_attr {
 110   MACH_BASE, MACH_MS1, MACH_MS1_003, MACH_MS2
 111  , MACH_MAX
 112 } MACH_ATTR;
 113
 114 /* Enum declaration for instruction set selection.  */
 115 typedef enum isa_attr {
 116   ISA_MT, ISA_MAX
 117 } ISA_ATTR;
 118
 119 /* Number of architecture variants.  */
 120 #define MAX_ISAS  1
 121 #define MAX_MACHS ((int) MACH_MAX)
 122
 123 /* Ifield support.  */
 124
 125 /* Ifield attribute indices.  */
 126
 127 /* Enum declaration for cgen_ifld attrs.  */
 128 typedef enum cgen_ifld_attr {
 129   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 130  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 131  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 132 } CGEN_IFLD_ATTR;
 133
 134 /* Number of non-boolean elements in cgen_ifld_attr.  */
 135 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 136
 137 /* cgen_ifld attribute accessor macros.  */
 138 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
 139 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
 140 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
 141 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
 142 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
 143 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
 144 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
 145
 146 /* Enum declaration for mt ifield types.  */
 147 typedef enum ifield_type {
 148   MT_F_NIL, MT_F_ANYOF, MT_F_MSYS, MT_F_OPC
 149  , MT_F_IMM, MT_F_UU24, MT_F_SR1, MT_F_SR2
 150  , MT_F_DR, MT_F_DRRR, MT_F_IMM16U, MT_F_IMM16S
 151  , MT_F_IMM16A, MT_F_UU4A, MT_F_UU4B, MT_F_UU12
 152  , MT_F_UU8, MT_F_UU16, MT_F_UU1, MT_F_MSOPC
 153  , MT_F_UU_26_25, MT_F_MASK, MT_F_BANKADDR, MT_F_RDA
 154  , MT_F_UU_2_25, MT_F_RBBC, MT_F_PERM, MT_F_MODE
 155  , MT_F_UU_1_24, MT_F_WR, MT_F_FBINCR, MT_F_UU_2_23
 156  , MT_F_XMODE, MT_F_A23, MT_F_MASK1, MT_F_CR
 157  , MT_F_TYPE, MT_F_INCAMT, MT_F_CBS, MT_F_UU_1_19
 158  , MT_F_BALL, MT_F_COLNUM, MT_F_BRC, MT_F_INCR
 159  , MT_F_FBDISP, MT_F_UU_4_15, MT_F_LENGTH, MT_F_UU_1_15
 160  , MT_F_RC, MT_F_RCNUM, MT_F_ROWNUM, MT_F_CBX
 161  , MT_F_ID, MT_F_SIZE, MT_F_ROWNUM1, MT_F_UU_3_11
 162  , MT_F_RC1, MT_F_CCB, MT_F_CBRB, MT_F_CDB
 163  , MT_F_ROWNUM2, MT_F_CELL, MT_F_UU_3_9, MT_F_CONTNUM
 164  , MT_F_UU_1_6, MT_F_DUP, MT_F_RC2, MT_F_CTXDISP
 165  , MT_F_IMM16L, MT_F_LOOPO, MT_F_CB1SEL, MT_F_CB2SEL
 166  , MT_F_CB1INCR, MT_F_CB2INCR, MT_F_RC3, MT_F_MSYSFRSR2
 167  , MT_F_BRC2, MT_F_BALL2, MT_F_MAX
 168 } IFIELD_TYPE;
 169
 170 #define MAX_IFLD ((int) MT_F_MAX)
 171
 172 /* Hardware attribute indices.  */
 173
 174 /* Enum declaration for cgen_hw attrs.  */
 175 typedef enum cgen_hw_attr {
 176   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 177  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 178 } CGEN_HW_ATTR;
 179
 180 /* Number of non-boolean elements in cgen_hw_attr.  */
 181 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 182
 183 /* cgen_hw attribute accessor macros.  */
 184 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
 185 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
 186 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
 187 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
 188 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
 189
 190 /* Enum declaration for mt hardware types.  */
 191 typedef enum cgen_hw_type {
 192   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 193  , HW_H_IADDR, HW_H_SPR, HW_H_PC, HW_MAX
 194 } CGEN_HW_TYPE;
 195
 196 #define MAX_HW ((int) HW_MAX)
 197
 198 /* Operand attribute indices.  */
 199
 200 /* Enum declaration for cgen_operand attrs.  */
 201 typedef enum cgen_operand_attr {
 202   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 203  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 204  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 205 } CGEN_OPERAND_ATTR;
 206
 207 /* Number of non-boolean elements in cgen_operand_attr.  */
 208 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 209
 210 /* cgen_operand attribute accessor macros.  */
 211 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 212 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
 213 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
 214 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
 215 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
 216 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
 217 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
 218 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
 219 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
 220
 221 /* Enum declaration for mt operand types.  */
 222 typedef enum cgen_operand_type {
 223   MT_OPERAND_PC, MT_OPERAND_FRSR1, MT_OPERAND_FRSR2, MT_OPERAND_FRDR
 224  , MT_OPERAND_FRDRRR, MT_OPERAND_IMM16, MT_OPERAND_IMM16Z, MT_OPERAND_IMM16O
 225  , MT_OPERAND_RC, MT_OPERAND_RCNUM, MT_OPERAND_CONTNUM, MT_OPERAND_RBBC
 226  , MT_OPERAND_COLNUM, MT_OPERAND_ROWNUM, MT_OPERAND_ROWNUM1, MT_OPERAND_ROWNUM2
 227  , MT_OPERAND_RC1, MT_OPERAND_RC2, MT_OPERAND_CBRB, MT_OPERAND_CELL
 228  , MT_OPERAND_DUP, MT_OPERAND_CTXDISP, MT_OPERAND_FBDISP, MT_OPERAND_TYPE
 229  , MT_OPERAND_MASK, MT_OPERAND_BANKADDR, MT_OPERAND_INCAMT, MT_OPERAND_XMODE
 230  , MT_OPERAND_MASK1, MT_OPERAND_BALL, MT_OPERAND_BRC, MT_OPERAND_RDA
 231  , MT_OPERAND_WR, MT_OPERAND_BALL2, MT_OPERAND_BRC2, MT_OPERAND_PERM
 232  , MT_OPERAND_A23, MT_OPERAND_CR, MT_OPERAND_CBS, MT_OPERAND_INCR
 233  , MT_OPERAND_LENGTH, MT_OPERAND_CBX, MT_OPERAND_CCB, MT_OPERAND_CDB
 234  , MT_OPERAND_MODE, MT_OPERAND_ID, MT_OPERAND_SIZE, MT_OPERAND_FBINCR
 235  , MT_OPERAND_LOOPSIZE, MT_OPERAND_IMM16L, MT_OPERAND_RC3, MT_OPERAND_CB1SEL
 236  , MT_OPERAND_CB2SEL, MT_OPERAND_CB1INCR, MT_OPERAND_CB2INCR, MT_OPERAND_MAX
 237 } CGEN_OPERAND_TYPE;
 238
 239 /* Number of operands types.  */
 240 #define MAX_OPERANDS 55
 241
 242 /* Maximum number of operands referenced by any insn.  */
 243 #define MAX_OPERAND_INSTANCES 8
 244
 245 /* Insn attribute indices.  */
 246
 247 /* Enum declaration for cgen_insn attrs.  */
 248 typedef enum cgen_insn_attr {
 249   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 250  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 251  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY, CGEN_INSN_MEMORY_ACCESS
 252  , CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN, CGEN_INSN_JAL_HAZARD
 253  , CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1, CGEN_INSN_USES_FRSR2
 254  , CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
 255  , CGEN_INSN_END_NBOOLS
 256 } CGEN_INSN_ATTR;
 257
 258 /* Number of non-boolean elements in cgen_insn_attr.  */
 259 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 260
 261 /* cgen_insn attribute accessor macros.  */
 262 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
 263 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
 264 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
 265 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
 266 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
 267 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
 268 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
 269 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
 270 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
 271 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
 272 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
 273 #define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_LOAD_DELAY)) != 0)
 274 #define CGEN_ATTR_CGEN_INSN_MEMORY_ACCESS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_MEMORY_ACCESS)) != 0)
 275 #define CGEN_ATTR_CGEN_INSN_AL_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_AL_INSN)) != 0)
 276 #define CGEN_ATTR_CGEN_INSN_IO_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IO_INSN)) != 0)
 277 #define CGEN_ATTR_CGEN_INSN_BR_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_BR_INSN)) != 0)
 278 #define CGEN_ATTR_CGEN_INSN_JAL_HAZARD_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_JAL_HAZARD)) != 0)
 279 #define CGEN_ATTR_CGEN_INSN_USES_FRDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_FRDR)) != 0)
 280 #define CGEN_ATTR_CGEN_INSN_USES_FRDRRR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_FRDRRR)) != 0)
 281 #define CGEN_ATTR_CGEN_INSN_USES_FRSR1_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_FRSR1)) != 0)
 282 #define CGEN_ATTR_CGEN_INSN_USES_FRSR2_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_USES_FRSR2)) != 0)
 283 #define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIPA)) != 0)
 284
 285 /* cgen.h uses things we just defined.  */
 286 #include "opcode/cgen.h"
 287
 288 extern const struct cgen_ifld mt_cgen_ifld_table[];
 289
 290 /* Attributes.  */
 291 extern const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[];
 292 extern const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[];
 293 extern const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[];
 294 extern const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[];
 295
 296 /* Hardware decls.  */
 297
 298 extern CGEN_KEYWORD mt_cgen_opval_h_spr;
 299
 300 extern const CGEN_HW_ENTRY mt_cgen_hw_table[];
 301
 302
 303
 304    #ifdef __cplusplus
 305    }
 306    #endif
 307
 308 #endif /* MT_CPU_H */