sim/bfin/dv-bfin_pll.c

   1 /* Blackfin Phase Lock Loop (PLL) model.
   2
   3    Copyright (C) 2010-2015 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "config.h"
  22
  23 #include "sim-main.h"
  24 #include "machs.h"
  25 #include "devices.h"
  26 #include "dv-bfin_pll.h"
  27
  28 struct bfin_pll
  29 {
  30   bu32 base;
  31
  32   /* Order after here is important -- matches hardware MMR layout.  */
  33   bu16 BFIN_MMR_16(pll_ctl);
  34   bu16 BFIN_MMR_16(pll_div);
  35   bu16 BFIN_MMR_16(vr_ctl);
  36   bu16 BFIN_MMR_16(pll_stat);
  37   bu16 BFIN_MMR_16(pll_lockcnt);
  38
  39   /* XXX: Not really the best place for this ...  */
  40   bu32 chipid;
  41 };
  42 #define mmr_base()      offsetof(struct bfin_pll, pll_ctl)
  43 #define mmr_offset(mmr) (offsetof(struct bfin_pll, mmr) - mmr_base())
  44
  45 static const char * const mmr_names[] =
  46 {
  47   "PLL_CTL", "PLL_DIV", "VR_CTL", "PLL_STAT", "PLL_LOCKCNT", "CHIPID",
  48 };
  49 #define mmr_name(off) mmr_names[(off) / 4]
  50
  51 static unsigned
  52 bfin_pll_io_write_buffer (struct hw *me, const void *source,
  53                           int space, address_word addr, unsigned nr_bytes)
  54 {
  55   struct bfin_pll *pll = hw_data (me);
  56   bu32 mmr_off;
  57   bu32 value;
  58   bu16 *value16p;
  59   bu32 *value32p;
  60   void *valuep;
  61
  62   if (nr_bytes == 4)
  63     value = dv_load_4 (source);
  64   else
  65     value = dv_load_2 (source);
  66
  67   mmr_off = addr - pll->base;
  68   valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off);
  69   value16p = valuep;
  70   value32p = valuep;
  71
  72   HW_TRACE_WRITE ();
  73
  74   switch (mmr_off)
  75     {
  76     case mmr_offset(pll_stat):
  77       dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  78     case mmr_offset(chipid):
  79       /* Discard writes.  */
  80       break;
  81     default:
  82       dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  83       *value16p = value;
  84       break;
  85     }
  86
  87   return nr_bytes;
  88 }
  89
  90 static unsigned
  91 bfin_pll_io_read_buffer (struct hw *me, void *dest,
  92                          int space, address_word addr, unsigned nr_bytes)
  93 {
  94   struct bfin_pll *pll = hw_data (me);
  95   bu32 mmr_off;
  96   bu32 *value32p;
  97   bu16 *value16p;
  98   void *valuep;
  99
 100   mmr_off = addr - pll->base;
 101   valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off);
 102   value16p = valuep;
 103   value32p = valuep;
 104
 105   HW_TRACE_READ ();
 106
 107   switch (mmr_off)
 108     {
 109     case mmr_offset(chipid):
 110       dv_store_4 (dest, *value32p);
 111       break;
 112     default:
 113       dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
 114       dv_store_2 (dest, *value16p);
 115       break;
 116     }
 117
 118   return nr_bytes;
 119 }
 120
 121 static const struct hw_port_descriptor bfin_pll_ports[] =
 122 {
 123   { "pll", 0, 0, output_port, },
 124   { NULL, 0, 0, 0, },
 125 };
 126
 127 static void
 128 attach_bfin_pll_regs (struct hw *me, struct bfin_pll *pll)
 129 {
 130   address_word attach_address;
 131   int attach_space;
 132   unsigned attach_size;
 133   reg_property_spec reg;
 134
 135   if (hw_find_property (me, "reg") == NULL)
 136     hw_abort (me, "Missing \"reg\" property");
 137
 138   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 139     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 140
 141   hw_unit_address_to_attach_address (hw_parent (me),
 142                                      &reg.address,
 143                                      &attach_space, &attach_address, me);
 144   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 145
 146   if (attach_size != BFIN_MMR_PLL_SIZE)
 147     hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PLL_SIZE);
 148
 149   hw_attach_address (hw_parent (me),
 150                      0, attach_space, attach_address, attach_size, me);
 151
 152   pll->base = attach_address;
 153 }
 154
 155 static void
 156 bfin_pll_finish (struct hw *me)
 157 {
 158   struct bfin_pll *pll;
 159
 160   pll = HW_ZALLOC (me, struct bfin_pll);
 161
 162   set_hw_data (me, pll);
 163   set_hw_io_read_buffer (me, bfin_pll_io_read_buffer);
 164   set_hw_io_write_buffer (me, bfin_pll_io_write_buffer);
 165   set_hw_ports (me, bfin_pll_ports);
 166
 167   attach_bfin_pll_regs (me, pll);
 168
 169   /* Initialize the PLL.  */
 170   /* XXX: Depends on part ?  */
 171   pll->pll_ctl = 0x1400;
 172   pll->pll_div = 0x0005;
 173   pll->vr_ctl = 0x40DB;
 174   pll->pll_stat = 0x00A2;
 175   pll->pll_lockcnt = 0x0200;
 176   pll->chipid = bfin_model_get_chipid (hw_system (me));
 177
 178   /* XXX: slow it down!  */
 179   pll->pll_ctl = 0xa800;
 180   pll->pll_div = 0x4;
 181   pll->vr_ctl = 0x40fb;
 182   pll->pll_stat = 0xa2;
 183   pll->pll_lockcnt = 0x300;
 184 }
 185
 186 const struct hw_descriptor dv_bfin_pll_descriptor[] =
 187 {
 188   {"bfin_pll", bfin_pll_finish,},
 189   {NULL, NULL},
 190 };