[ARM] "svc" insn check at irrelevant address in ARM unwind info sniffer
[binutils-gdb.git] / sim / mcore / Makefile.in
blobc94e5bcd4c9838713528d133f27c9c42b17b8a57
1 # Makefile template for Configure for the MCore sim library.
2 # Copyright (C) 1990-2015 Free Software Foundation, Inc.
3 # Written by Cygnus Solutions.
5 # This program is free software; you can redistribute it and/or modify
6 # it under the terms of the GNU General Public License as published by
7 # the Free Software Foundation; either version 3 of the License, or
8 # (at your option) any later version.
10 # This program is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 # GNU General Public License for more details.
15 # You should have received a copy of the GNU General Public License
16 # along with this program. If not, see <http://www.gnu.org/licenses/>.
18 # This selects the bfin newlib/libgloss syscall definitions.
19 NL_TARGET = -DNL_TARGET_mcore
21 ## COMMON_PRE_CONFIG_FRAG
23 SIM_OBJS = \
24 interp.o \
25 $(SIM_NEW_COMMON_OBJS) \
26 sim-hload.o \
27 sim-resume.o
29 ## COMMON_POST_CONFIG_FRAG