gdb/nds32-tdep.c

   1 /* Target-dependent code for the NDS32 architecture, for GDB.
   2
   3    Copyright (C) 2013-2024 Free Software Foundation, Inc.
   4    Contributed by Andes Technology Corporation.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "extract-store-integer.h"
  22 #include "frame.h"
  23 #include "frame-unwind.h"
  24 #include "frame-base.h"
  25 #include "symtab.h"
  26 #include "gdbtypes.h"
  27 #include "gdbcore.h"
  28 #include "value.h"
  29 #include "reggroups.h"
  30 #include "inferior.h"
  31 #include "osabi.h"
  32 #include "arch-utils.h"
  33 #include "regcache.h"
  34 #include "dis-asm.h"
  35 #include "user-regs.h"
  36 #include "elf-bfd.h"
  37 #include "dwarf2/frame.h"
  38 #include "remote.h"
  39 #include "target-descriptions.h"
  40
  41 #include "nds32-tdep.h"
  42 #include "elf/nds32.h"
  43 #include "opcode/nds32.h"
  44 #include <algorithm>
  45
  46 #include "features/nds32.c"
  47
  48 /* Simple macros for instruction analysis.  */
  49 #define CHOP_BITS(insn, n)      (insn & ~__MASK (n))
  50 #define N32_LSMW_ENABLE4(insn)  (((insn) >> 6) & 0xf)
  51 #define N32_SMW_ADM \
  52         N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
  53 #define N32_LMW_BIM \
  54         N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
  55 #define N32_FLDI_SP \
  56         N32_TYPE2 (LDC, 0, REG_SP, 0)
  57
  58 /* Use an invalid address value as 'not available' marker.  */
  59 enum { REG_UNAVAIL = (CORE_ADDR) -1 };
  60
  61 /* Use an impossible value as invalid offset.  */
  62 enum { INVALID_OFFSET = (CORE_ADDR) -1 };
  63
  64 /* Instruction groups for NDS32 epilogue analysis.  */
  65 enum
  66 {
  67   /* Instructions used everywhere, not only in epilogue.  */
  68   INSN_NORMAL,
  69   /* Instructions used to reset sp for local vars, arguments, etc.  */
  70   INSN_RESET_SP,
  71   /* Instructions used to recover saved regs and to recover padding.  */
  72   INSN_RECOVER,
  73   /* Instructions used to return to the caller.  */
  74   INSN_RETURN,
  75   /* Instructions used to recover saved regs and to return to the caller.  */
  76   INSN_RECOVER_RETURN,
  77 };
  78
  79 static const char *const nds32_register_names[] =
  80 {
  81   /* 32 GPRs.  */
  82   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  83   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  84   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  85   "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
  86   /* PC.  */
  87   "pc",
  88 };
  89
  90 static const char *const nds32_fdr_register_names[] =
  91 {
  92   "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
  93   "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
  94   "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
  95   "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
  96 };
  97
  98 static const char *const nds32_fsr_register_names[] =
  99 {
 100   "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
 101   "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
 102   "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
 103   "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
 104 };
 105
 106 /* The number of registers for four FPU configuration options.  */
 107 const int num_fdr_map[] = { 4, 8, 16, 32 };
 108 const int num_fsr_map[] = { 8, 16, 32, 32 };
 109
 110 /* Aliases for registers.  */
 111 static const struct
 112 {
 113   const char *name;
 114   const char *alias;
 115 } nds32_register_aliases[] =
 116 {
 117   {"r15", "ta"},
 118   {"r26", "p0"},
 119   {"r27", "p1"},
 120   {"fp", "r28"},
 121   {"gp", "r29"},
 122   {"lp", "r30"},
 123   {"sp", "r31"},
 124
 125   {"cr0", "cpu_ver"},
 126   {"cr1", "icm_cfg"},
 127   {"cr2", "dcm_cfg"},
 128   {"cr3", "mmu_cfg"},
 129   {"cr4", "msc_cfg"},
 130   {"cr5", "core_id"},
 131   {"cr6", "fucop_exist"},
 132   {"cr7", "msc_cfg2"},
 133
 134   {"ir0", "psw"},
 135   {"ir1", "ipsw"},
 136   {"ir2", "p_psw"},
 137   {"ir3", "ivb"},
 138   {"ir4", "eva"},
 139   {"ir5", "p_eva"},
 140   {"ir6", "itype"},
 141   {"ir7", "p_itype"},
 142   {"ir8", "merr"},
 143   {"ir9", "ipc"},
 144   {"ir10", "p_ipc"},
 145   {"ir11", "oipc"},
 146   {"ir12", "p_p0"},
 147   {"ir13", "p_p1"},
 148   {"ir14", "int_mask"},
 149   {"ir15", "int_pend"},
 150   {"ir16", "sp_usr"},
 151   {"ir17", "sp_priv"},
 152   {"ir18", "int_pri"},
 153   {"ir19", "int_ctrl"},
 154   {"ir20", "sp_usr1"},
 155   {"ir21", "sp_priv1"},
 156   {"ir22", "sp_usr2"},
 157   {"ir23", "sp_priv2"},
 158   {"ir24", "sp_usr3"},
 159   {"ir25", "sp_priv3"},
 160   {"ir26", "int_mask2"},
 161   {"ir27", "int_pend2"},
 162   {"ir28", "int_pri2"},
 163   {"ir29", "int_trigger"},
 164
 165   {"mr0", "mmu_ctl"},
 166   {"mr1", "l1_pptb"},
 167   {"mr2", "tlb_vpn"},
 168   {"mr3", "tlb_data"},
 169   {"mr4", "tlb_misc"},
 170   {"mr5", "vlpt_idx"},
 171   {"mr6", "ilmb"},
 172   {"mr7", "dlmb"},
 173   {"mr8", "cache_ctl"},
 174   {"mr9", "hsmp_saddr"},
 175   {"mr10", "hsmp_eaddr"},
 176   {"mr11", "bg_region"},
 177
 178   {"dr0", "bpc0"},
 179   {"dr1", "bpc1"},
 180   {"dr2", "bpc2"},
 181   {"dr3", "bpc3"},
 182   {"dr4", "bpc4"},
 183   {"dr5", "bpc5"},
 184   {"dr6", "bpc6"},
 185   {"dr7", "bpc7"},
 186   {"dr8", "bpa0"},
 187   {"dr9", "bpa1"},
 188   {"dr10", "bpa2"},
 189   {"dr11", "bpa3"},
 190   {"dr12", "bpa4"},
 191   {"dr13", "bpa5"},
 192   {"dr14", "bpa6"},
 193   {"dr15", "bpa7"},
 194   {"dr16", "bpam0"},
 195   {"dr17", "bpam1"},
 196   {"dr18", "bpam2"},
 197   {"dr19", "bpam3"},
 198   {"dr20", "bpam4"},
 199   {"dr21", "bpam5"},
 200   {"dr22", "bpam6"},
 201   {"dr23", "bpam7"},
 202   {"dr24", "bpv0"},
 203   {"dr25", "bpv1"},
 204   {"dr26", "bpv2"},
 205   {"dr27", "bpv3"},
 206   {"dr28", "bpv4"},
 207   {"dr29", "bpv5"},
 208   {"dr30", "bpv6"},
 209   {"dr31", "bpv7"},
 210   {"dr32", "bpcid0"},
 211   {"dr33", "bpcid1"},
 212   {"dr34", "bpcid2"},
 213   {"dr35", "bpcid3"},
 214   {"dr36", "bpcid4"},
 215   {"dr37", "bpcid5"},
 216   {"dr38", "bpcid6"},
 217   {"dr39", "bpcid7"},
 218   {"dr40", "edm_cfg"},
 219   {"dr41", "edmsw"},
 220   {"dr42", "edm_ctl"},
 221   {"dr43", "edm_dtr"},
 222   {"dr44", "bpmtc"},
 223   {"dr45", "dimbr"},
 224   {"dr46", "tecr0"},
 225   {"dr47", "tecr1"},
 226
 227   {"hspr0", "hsp_ctl"},
 228   {"hspr1", "sp_bound"},
 229   {"hspr2", "sp_bound_priv"},
 230
 231   {"pfr0", "pfmc0"},
 232   {"pfr1", "pfmc1"},
 233   {"pfr2", "pfmc2"},
 234   {"pfr3", "pfm_ctl"},
 235   {"pfr4", "pft_ctl"},
 236
 237   {"dmar0", "dma_cfg"},
 238   {"dmar1", "dma_gcsw"},
 239   {"dmar2", "dma_chnsel"},
 240   {"dmar3", "dma_act"},
 241   {"dmar4", "dma_setup"},
 242   {"dmar5", "dma_isaddr"},
 243   {"dmar6", "dma_esaddr"},
 244   {"dmar7", "dma_tcnt"},
 245   {"dmar8", "dma_status"},
 246   {"dmar9", "dma_2dset"},
 247   {"dmar10", "dma_2dsctl"},
 248   {"dmar11", "dma_rcnt"},
 249   {"dmar12", "dma_hstatus"},
 250
 251   {"racr0", "prusr_acc_ctl"},
 252   {"fucpr", "fucop_ctl"},
 253
 254   {"idr0", "sdz_ctl"},
 255   {"idr1", "misc_ctl"},
 256   {"idr2", "ecc_misc"},
 257
 258   {"secur0", "sfcr"},
 259   {"secur1", "sign"},
 260   {"secur2", "isign"},
 261   {"secur3", "p_isign"},
 262 };
 263
 264 /* Value of a register alias.  BATON is the regnum of the corresponding
 265    register.  */
 266
 267 static struct value *
 268 value_of_nds32_reg (const frame_info_ptr &frame, const void *baton)
 269 {
 270   return value_of_register ((int) (intptr_t) baton,
 271                             get_next_frame_sentinel_okay (frame));
 272 }
 273
 274 /* Implement the "frame_align" gdbarch method.  */
 275
 276 static CORE_ADDR
 277 nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 278 {
 279   /* 8-byte aligned.  */
 280   return align_down (sp, 8);
 281 }
 282
 283 /* The same insn machine code is used for little-endian and big-endian.  */
 284 constexpr gdb_byte nds32_break_insn[] = { 0xEA, 0x00 };
 285
 286 typedef BP_MANIPULATION (nds32_break_insn) nds32_breakpoint;
 287
 288 /* Implement the "dwarf2_reg_to_regnum" gdbarch method.  */
 289
 290 static int
 291 nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
 292 {
 293   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
 294   const int FSR = 38;
 295   const int FDR = FSR + 32;
 296
 297   if (num >= 0 && num < 32)
 298     {
 299       /* General-purpose registers (R0 - R31).  */
 300       return num;
 301     }
 302   else if (num >= FSR && num < FSR + 32)
 303     {
 304       /* Single precision floating-point registers (FS0 - FS31).  */
 305       return num - FSR + tdep->fs0_regnum;
 306     }
 307   else if (num >= FDR && num < FDR + 32)
 308     {
 309       /* Double precision floating-point registers (FD0 - FD31).  */
 310       return num - FDR + NDS32_FD0_REGNUM;
 311     }
 312
 313   /* No match, return a inaccessible register number.  */
 314   return -1;
 315 }
 316 \f
 317 /* NDS32 register groups.  */
 318 static const reggroup *nds32_cr_reggroup;
 319 static const reggroup *nds32_ir_reggroup;
 320 static const reggroup *nds32_mr_reggroup;
 321 static const reggroup *nds32_dr_reggroup;
 322 static const reggroup *nds32_pfr_reggroup;
 323 static const reggroup *nds32_hspr_reggroup;
 324 static const reggroup *nds32_dmar_reggroup;
 325 static const reggroup *nds32_racr_reggroup;
 326 static const reggroup *nds32_idr_reggroup;
 327 static const reggroup *nds32_secur_reggroup;
 328
 329 static void
 330 nds32_init_reggroups (void)
 331 {
 332   nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
 333   nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
 334   nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
 335   nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
 336   nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
 337   nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
 338   nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
 339   nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
 340   nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
 341   nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
 342 }
 343
 344 static void
 345 nds32_add_reggroups (struct gdbarch *gdbarch)
 346 {
 347   /* Add NDS32 register groups.  */
 348   reggroup_add (gdbarch, nds32_cr_reggroup);
 349   reggroup_add (gdbarch, nds32_ir_reggroup);
 350   reggroup_add (gdbarch, nds32_mr_reggroup);
 351   reggroup_add (gdbarch, nds32_dr_reggroup);
 352   reggroup_add (gdbarch, nds32_pfr_reggroup);
 353   reggroup_add (gdbarch, nds32_hspr_reggroup);
 354   reggroup_add (gdbarch, nds32_dmar_reggroup);
 355   reggroup_add (gdbarch, nds32_racr_reggroup);
 356   reggroup_add (gdbarch, nds32_idr_reggroup);
 357   reggroup_add (gdbarch, nds32_secur_reggroup);
 358 }
 359
 360 /* Implement the "register_reggroup_p" gdbarch method.  */
 361
 362 static int
 363 nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
 364                            const struct reggroup *reggroup)
 365 {
 366   const char *reg_name;
 367   const char *group_name;
 368   int ret;
 369
 370   if (reggroup == all_reggroup)
 371     return 1;
 372
 373   /* General reggroup contains only GPRs and PC.  */
 374   if (reggroup == general_reggroup)
 375     return regnum <= NDS32_PC_REGNUM;
 376
 377   if (reggroup == float_reggroup || reggroup == save_reggroup
 378       || reggroup == restore_reggroup)
 379     {
 380       ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
 381       if (ret != -1)
 382         return ret;
 383
 384       return default_register_reggroup_p (gdbarch, regnum, reggroup);
 385     }
 386
 387   if (reggroup == system_reggroup)
 388     return (regnum > NDS32_PC_REGNUM)
 389             && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
 390
 391   /* The NDS32 reggroup contains registers whose name is prefixed
 392      by reggroup name.  */
 393   reg_name = gdbarch_register_name (gdbarch, regnum);
 394   group_name = reggroup->name ();
 395   return !strncmp (reg_name, group_name, strlen (group_name));
 396 }
 397 \f
 398 /* Implement the "pseudo_register_type" tdesc_arch_data method.  */
 399
 400 static struct type *
 401 nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
 402 {
 403   regnum -= gdbarch_num_regs (gdbarch);
 404
 405   /* Currently, only FSRs could be defined as pseudo registers.  */
 406   if (regnum < gdbarch_num_pseudo_regs (gdbarch))
 407     {
 408       type_allocator alloc (gdbarch);
 409       return init_float_type (alloc, -1, "builtin_type_ieee_single",
 410                               floatformats_ieee_single);
 411     }
 412
 413   warning (_("Unknown nds32 pseudo register %d."), regnum);
 414   return NULL;
 415 }
 416
 417 /* Implement the "pseudo_register_name" tdesc_arch_data method.  */
 418
 419 static const char *
 420 nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
 421 {
 422   regnum -= gdbarch_num_regs (gdbarch);
 423
 424   /* Currently, only FSRs could be defined as pseudo registers.  */
 425   gdb_assert (regnum < gdbarch_num_pseudo_regs (gdbarch));
 426   return nds32_fsr_register_names[regnum];
 427 }
 428
 429 /* Implement the "pseudo_register_read" gdbarch method.  */
 430
 431 static enum register_status
 432 nds32_pseudo_register_read (struct gdbarch *gdbarch,
 433                             readable_regcache *regcache, int regnum,
 434                             gdb_byte *buf)
 435 {
 436   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
 437   gdb_byte reg_buf[8];
 438   int offset, fdr_regnum;
 439   enum register_status status;
 440
 441   /* This function is registered in nds32_gdbarch_init only after these are
 442      set.  */
 443   gdb_assert (tdep->fpu_freg != -1);
 444   gdb_assert (tdep->use_pseudo_fsrs != 0);
 445
 446   regnum -= gdbarch_num_regs (gdbarch);
 447
 448   /* Currently, only FSRs could be defined as pseudo registers.  */
 449   if (regnum < gdbarch_num_pseudo_regs (gdbarch))
 450     {
 451       /* fs0 is always the most significant half of fd0.  */
 452       if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
 453         offset = (regnum & 1) ? 4 : 0;
 454       else
 455         offset = (regnum & 1) ? 0 : 4;
 456
 457       fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
 458       status = regcache->raw_read (fdr_regnum, reg_buf);
 459       if (status == REG_VALID)
 460         memcpy (buf, reg_buf + offset, 4);
 461
 462       return status;
 463     }
 464
 465   gdb_assert_not_reached ("invalid pseudo register number");
 466 }
 467
 468 /* Implement the "pseudo_register_write" gdbarch method.  */
 469
 470 static void
 471 nds32_pseudo_register_write (struct gdbarch *gdbarch,
 472                              struct regcache *regcache, int regnum,
 473                              const gdb_byte *buf)
 474 {
 475   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
 476   gdb_byte reg_buf[8];
 477   int offset, fdr_regnum;
 478
 479   /* This function is registered in nds32_gdbarch_init only after these are
 480      set.  */
 481   gdb_assert (tdep->fpu_freg != -1);
 482   gdb_assert (tdep->use_pseudo_fsrs != 0);
 483
 484   regnum -= gdbarch_num_regs (gdbarch);
 485
 486   /* Currently, only FSRs could be defined as pseudo registers.  */
 487   if (regnum < gdbarch_num_pseudo_regs (gdbarch))
 488     {
 489       /* fs0 is always the most significant half of fd0.  */
 490       if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
 491         offset = (regnum & 1) ? 4 : 0;
 492       else
 493         offset = (regnum & 1) ? 0 : 4;
 494
 495       fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
 496       regcache->raw_read (fdr_regnum, reg_buf);
 497       memcpy (reg_buf + offset, buf, 4);
 498       regcache->raw_write (fdr_regnum, reg_buf);
 499       return;
 500     }
 501
 502   gdb_assert_not_reached ("invalid pseudo register number");
 503 }
 504 \f
 505 /* Helper function for NDS32 ABI.  Return true if FPRs can be used
 506    to pass function arguments and return value.  */
 507
 508 static int
 509 nds32_abi_use_fpr (int elf_abi)
 510 {
 511   return elf_abi == E_NDS_ABI_V2FP_PLUS;
 512 }
 513
 514 /* Helper function for NDS32 ABI.  Return true if GPRs and stack
 515    can be used together to pass an argument.  */
 516
 517 static int
 518 nds32_abi_split (int elf_abi)
 519 {
 520   return elf_abi == E_NDS_ABI_AABI;
 521 }
 522
 523 #define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
 524
 525 struct nds32_frame_cache
 526 {
 527   /* The previous frame's inner most stack address.  Used as this
 528      frame ID's stack_addr.  */
 529   CORE_ADDR prev_sp;
 530
 531   /* The frame's base, optionally used by the high-level debug info.  */
 532   CORE_ADDR base;
 533
 534   /* During prologue analysis, keep how far the SP and FP have been offset
 535      from the start of the stack frame (as defined by the previous frame's
 536      stack pointer).
 537      During epilogue analysis, keep how far the SP has been offset from the
 538      current stack pointer.  */
 539   CORE_ADDR sp_offset;
 540   CORE_ADDR fp_offset;
 541
 542   /* The address of the first instruction in this function.  */
 543   CORE_ADDR pc;
 544
 545   /* Saved registers.  */
 546   CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
 547 };
 548
 549 /* Allocate and initialize a frame cache.  */
 550
 551 static struct nds32_frame_cache *
 552 nds32_alloc_frame_cache (void)
 553 {
 554   struct nds32_frame_cache *cache;
 555   int i;
 556
 557   cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
 558
 559   /* Initialize fp_offset to check if FP is set in prologue.  */
 560   cache->fp_offset = INVALID_OFFSET;
 561
 562   /* Saved registers.  We initialize these to -1 since zero is a valid
 563      offset.  */
 564   for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
 565     cache->saved_regs[i] = REG_UNAVAIL;
 566
 567   return cache;
 568 }
 569
 570 /* Helper function for instructions used to push multiple words.  */
 571
 572 static void
 573 nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
 574                            int enable4)
 575 {
 576   CORE_ADDR sp_offset = cache->sp_offset;
 577   int i;
 578
 579   /* Check LP, GP, FP in enable4.  */
 580   for (i = 1; i <= 3; i++)
 581     {
 582       if ((enable4 >> i) & 0x1)
 583         {
 584           sp_offset += 4;
 585           cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
 586         }
 587     }
 588
 589   /* Skip case where re == rb == sp.  */
 590   if ((rb < REG_FP) && (re < REG_FP))
 591     {
 592       for (i = re; i >= rb; i--)
 593         {
 594           sp_offset += 4;
 595           cache->saved_regs[i] = sp_offset;
 596         }
 597     }
 598
 599   /* For sp, update the offset.  */
 600   cache->sp_offset = sp_offset;
 601 }
 602
 603 /* Analyze the instructions within the given address range.  If CACHE
 604    is non-NULL, fill it in.  Return the first address beyond the given
 605    address range.  If CACHE is NULL, return the first address not
 606    recognized as a prologue instruction.  */
 607
 608 static CORE_ADDR
 609 nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
 610                         CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
 611 {
 612   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
 613   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
 614   /* Current scanning status.  */
 615   int in_prologue_bb = 0;
 616   int val_ta = 0;
 617   uint32_t insn, insn_len;
 618
 619   for (; pc < limit_pc; pc += insn_len)
 620     {
 621       insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
 622
 623       if ((insn & 0x80000000) == 0)
 624         {
 625           /* 32-bit instruction */
 626           insn_len = 4;
 627
 628           if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
 629             {
 630               /* addi $sp, $sp, imm15s */
 631               int imm15s = N32_IMM15S (insn);
 632
 633               if (imm15s < 0)
 634                 {
 635                   if (cache != NULL)
 636                     cache->sp_offset += -imm15s;
 637
 638                   in_prologue_bb = 1;
 639                   continue;
 640                 }
 641             }
 642           else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
 643             {
 644               /* addi $fp, $sp, imm15s */
 645               int imm15s = N32_IMM15S (insn);
 646
 647               if (imm15s > 0)
 648                 {
 649                   if (cache != NULL)
 650                     cache->fp_offset = cache->sp_offset - imm15s;
 651
 652                   in_prologue_bb = 1;
 653                   continue;
 654                 }
 655             }
 656           else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
 657                    && N32_RA5 (insn) == REG_SP)
 658             {
 659               /* smw.adm Rb, [$sp], Re, enable4 */
 660               if (cache != NULL)
 661                 nds32_push_multiple_words (cache, N32_RT5 (insn),
 662                                            N32_RB5 (insn),
 663                                            N32_LSMW_ENABLE4 (insn));
 664               in_prologue_bb = 1;
 665               continue;
 666             }
 667           else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
 668                    || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
 669             {
 670               /* add $sp, $sp, $ta */
 671               /* add $sp, $ta, $sp */
 672               if (val_ta < 0)
 673                 {
 674                   if (cache != NULL)
 675                     cache->sp_offset += -val_ta;
 676
 677                   in_prologue_bb = 1;
 678                   continue;
 679                 }
 680             }
 681           else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
 682             {
 683               /* movi $ta, imm20s */
 684               if (cache != NULL)
 685                 val_ta = N32_IMM20S (insn);
 686
 687               continue;
 688             }
 689           else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
 690             {
 691               /* sethi $ta, imm20u */
 692               if (cache != NULL)
 693                 val_ta = N32_IMM20U (insn) << 12;
 694
 695               continue;
 696             }
 697           else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
 698             {
 699               /* ori $ta, $ta, imm15u */
 700               if (cache != NULL)
 701                 val_ta |= N32_IMM15U (insn);
 702
 703               continue;
 704             }
 705           else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
 706             {
 707               /* addi $ta, $ta, imm15s */
 708               if (cache != NULL)
 709                 val_ta += N32_IMM15S (insn);
 710
 711               continue;
 712             }
 713           if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
 714               || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
 715             {
 716               /* add $gp, $ta, $gp */
 717               /* add $gp, $gp, $ta */
 718               in_prologue_bb = 1;
 719               continue;
 720             }
 721           else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
 722             {
 723               /* movi $gp, imm20s */
 724               in_prologue_bb = 1;
 725               continue;
 726             }
 727           else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
 728             {
 729               /* sethi $gp, imm20u */
 730               in_prologue_bb = 1;
 731               continue;
 732             }
 733           else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
 734             {
 735               /* ori $gp, $gp, imm15u */
 736               in_prologue_bb = 1;
 737               continue;
 738             }
 739           else
 740             {
 741               /* Jump/Branch insns never appear in prologue basic block.
 742                  The loop can be escaped early when these insns are met.  */
 743               if (in_prologue_bb == 1)
 744                 {
 745                   int op = N32_OP6 (insn);
 746
 747                   if (op == N32_OP6_JI
 748                       || op == N32_OP6_JREG
 749                       || op == N32_OP6_BR1
 750                       || op == N32_OP6_BR2
 751                       || op == N32_OP6_BR3)
 752                     break;
 753                 }
 754             }
 755
 756           if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
 757               && __GF (insn, 12, 3) == 0)
 758             {
 759               /* For FPU insns, CP (bit [13:14]) should be CP0,  and only
 760                  normal form (bit [12] == 0) is used.  */
 761
 762               /* fsdi FDt, [$sp + (imm12s << 2)] */
 763               if (N32_RA5 (insn) == REG_SP)
 764                 continue;
 765             }
 766
 767           /* The optimizer might shove anything into the prologue, if
 768              we build up cache (cache != NULL) from analyzing prologue,
 769              we just skip what we don't recognize and analyze further to
 770              make cache as complete as possible.  However, if we skip
 771              prologue, we'll stop immediately on unrecognized
 772              instruction.  */
 773           if (cache == NULL)
 774             break;
 775         }
 776       else
 777         {
 778           /* 16-bit instruction */
 779           insn_len = 2;
 780
 781           insn >>= 16;
 782
 783           if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
 784             {
 785               /* addi10s.sp */
 786               int imm10s = N16_IMM10S (insn);
 787
 788               if (imm10s < 0)
 789                 {
 790                   if (cache != NULL)
 791                     cache->sp_offset += -imm10s;
 792
 793                   in_prologue_bb = 1;
 794                   continue;
 795                 }
 796             }
 797           else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
 798             {
 799               /* push25 */
 800               if (cache != NULL)
 801                 {
 802                   int imm8u = (insn & 0x1f) << 3;
 803                   int re = (insn >> 5) & 0x3;
 804                   const int reg_map[] = { 6, 8, 10, 14 };
 805
 806                   /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
 807                   nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
 808
 809                   /* Operation 2 -- sp = sp - (imm5u << 3) */
 810                   cache->sp_offset += imm8u;
 811                 }
 812
 813               in_prologue_bb = 1;
 814               continue;
 815             }
 816           else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
 817             {
 818               /* add5.pc $gp */
 819               in_prologue_bb = 1;
 820               continue;
 821             }
 822           else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
 823             {
 824               /* movi55 $gp, imm5s */
 825               in_prologue_bb = 1;
 826               continue;
 827             }
 828           else
 829             {
 830               /* Jump/Branch insns never appear in prologue basic block.
 831                  The loop can be escaped early when these insns are met.  */
 832               if (in_prologue_bb == 1)
 833                 {
 834                   uint32_t insn5 = CHOP_BITS (insn, 5);
 835                   uint32_t insn8 = CHOP_BITS (insn, 8);
 836                   uint32_t insn38 = CHOP_BITS (insn, 11);
 837
 838                   if (insn5 == N16_TYPE5 (JR5, 0)
 839                       || insn5 == N16_TYPE5 (JRAL5, 0)
 840                       || insn5 == N16_TYPE5 (RET5, 0)
 841                       || insn8 == N16_TYPE8 (J8, 0)
 842                       || insn8 == N16_TYPE8 (BEQZS8, 0)
 843                       || insn8 == N16_TYPE8 (BNEZS8, 0)
 844                       || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
 845                       || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
 846                       || insn38 == N16_TYPE38 (BEQS38, 0, 0)
 847                       || insn38 == N16_TYPE38 (BNES38, 0, 0))
 848                     break;
 849                 }
 850             }
 851
 852           /* The optimizer might shove anything into the prologue, if
 853              we build up cache (cache != NULL) from analyzing prologue,
 854              we just skip what we don't recognize and analyze further to
 855              make cache as complete as possible.  However, if we skip
 856              prologue, we'll stop immediately on unrecognized
 857              instruction.  */
 858           if (cache == NULL)
 859             break;
 860         }
 861     }
 862
 863   return pc;
 864 }
 865
 866 /* Implement the "skip_prologue" gdbarch method.
 867
 868    Find the end of function prologue.  */
 869
 870 static CORE_ADDR
 871 nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 872 {
 873   CORE_ADDR func_addr, limit_pc;
 874
 875   /* See if we can determine the end of the prologue via the symbol table.
 876      If so, then return either PC, or the PC after the prologue, whichever
 877      is greater.  */
 878   if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
 879     {
 880       CORE_ADDR post_prologue_pc
 881         = skip_prologue_using_sal (gdbarch, func_addr);
 882       if (post_prologue_pc != 0)
 883         return std::max (pc, post_prologue_pc);
 884     }
 885
 886   /* Can't determine prologue from the symbol table, need to examine
 887      instructions.  */
 888
 889   /* Find an upper limit on the function prologue using the debug
 890      information.  If the debug information could not be used to provide
 891      that bound, then use an arbitrary large number as the upper bound.  */
 892   limit_pc = skip_prologue_using_sal (gdbarch, pc);
 893   if (limit_pc == 0)
 894     limit_pc = pc + 128;        /* Magic.  */
 895
 896   /* Find the end of prologue.  */
 897   return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
 898 }
 899
 900 /* Allocate and fill in *THIS_CACHE with information about the prologue of
 901    *THIS_FRAME.  Do not do this if *THIS_CACHE was already allocated.  Return
 902    a pointer to the current nds32_frame_cache in *THIS_CACHE.  */
 903
 904 static struct nds32_frame_cache *
 905 nds32_frame_cache (const frame_info_ptr &this_frame, void **this_cache)
 906 {
 907   struct gdbarch *gdbarch = get_frame_arch (this_frame);
 908   struct nds32_frame_cache *cache;
 909   CORE_ADDR current_pc;
 910   ULONGEST prev_sp;
 911   ULONGEST this_base;
 912   int i;
 913
 914   if (*this_cache)
 915     return (struct nds32_frame_cache *) *this_cache;
 916
 917   cache = nds32_alloc_frame_cache ();
 918   *this_cache = cache;
 919
 920   cache->pc = get_frame_func (this_frame);
 921   current_pc = get_frame_pc (this_frame);
 922   nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
 923
 924   /* Compute the previous frame's stack pointer (which is also the
 925      frame's ID's stack address), and this frame's base pointer.  */
 926   if (cache->fp_offset != INVALID_OFFSET)
 927     {
 928       /* FP is set in prologue, so it can be used to calculate other info.  */
 929       this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
 930       prev_sp = this_base + cache->fp_offset;
 931     }
 932   else
 933     {
 934       this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
 935       prev_sp = this_base + cache->sp_offset;
 936     }
 937
 938   cache->prev_sp = prev_sp;
 939   cache->base = this_base;
 940
 941   /* Adjust all the saved registers such that they contain addresses
 942      instead of offsets.  */
 943   for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
 944     if (cache->saved_regs[i] != REG_UNAVAIL)
 945       cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
 946
 947   return cache;
 948 }
 949
 950 /* Implement the "this_id" frame_unwind method.
 951
 952    Our frame ID for a normal frame is the current function's starting
 953    PC and the caller's SP when we were called.  */
 954
 955 static void
 956 nds32_frame_this_id (const frame_info_ptr &this_frame,
 957                      void **this_cache, struct frame_id *this_id)
 958 {
 959   struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
 960
 961   /* This marks the outermost frame.  */
 962   if (cache->prev_sp == 0)
 963     return;
 964
 965   *this_id = frame_id_build (cache->prev_sp, cache->pc);
 966 }
 967
 968 /* Implement the "prev_register" frame_unwind method.  */
 969
 970 static struct value *
 971 nds32_frame_prev_register (const frame_info_ptr &this_frame, void **this_cache,
 972                            int regnum)
 973 {
 974   struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
 975
 976   if (regnum == NDS32_SP_REGNUM)
 977     return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
 978
 979   /* The PC of the previous frame is stored in the LP register of
 980      the current frame.  */
 981   if (regnum == NDS32_PC_REGNUM)
 982     regnum = NDS32_LP_REGNUM;
 983
 984   if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
 985     return frame_unwind_got_memory (this_frame, regnum,
 986                                     cache->saved_regs[regnum]);
 987
 988   return frame_unwind_got_register (this_frame, regnum, regnum);
 989 }
 990
 991 static const struct frame_unwind nds32_frame_unwind =
 992 {
 993   "nds32 prologue",
 994   NORMAL_FRAME,
 995   default_frame_unwind_stop_reason,
 996   nds32_frame_this_id,
 997   nds32_frame_prev_register,
 998   NULL,
 999   default_frame_sniffer,
1000 };
1001
1002 /* Return the frame base address of *THIS_FRAME.  */
1003
1004 static CORE_ADDR
1005 nds32_frame_base_address (const frame_info_ptr &this_frame, void **this_cache)
1006 {
1007   struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1008
1009   return cache->base;
1010 }
1011
1012 static const struct frame_base nds32_frame_base =
1013 {
1014   &nds32_frame_unwind,
1015   nds32_frame_base_address,
1016   nds32_frame_base_address,
1017   nds32_frame_base_address
1018 };
1019 \f
1020 /* Helper function for instructions used to pop multiple words.  */
1021
1022 static void
1023 nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1024                           int enable4)
1025 {
1026   CORE_ADDR sp_offset = cache->sp_offset;
1027   int i;
1028
1029   /* Skip case where re == rb == sp.  */
1030   if ((rb < REG_FP) && (re < REG_FP))
1031     {
1032       for (i = rb; i <= re; i++)
1033         {
1034           cache->saved_regs[i] = sp_offset;
1035           sp_offset += 4;
1036         }
1037     }
1038
1039   /* Check FP, GP, LP in enable4.  */
1040   for (i = 3; i >= 1; i--)
1041     {
1042       if ((enable4 >> i) & 0x1)
1043         {
1044           cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1045           sp_offset += 4;
1046         }
1047     }
1048
1049   /* For sp, update the offset.  */
1050   cache->sp_offset = sp_offset;
1051 }
1052
1053 /* The instruction sequences in NDS32 epilogue are
1054
1055    INSN_RESET_SP  (optional)
1056                   (If exists, this must be the first instruction in epilogue
1057                    and the stack has not been destroyed.).
1058    INSN_RECOVER  (optional).
1059    INSN_RETURN/INSN_RECOVER_RETURN  (required).  */
1060
1061 /* Helper function for analyzing the given 32-bit INSN.  If CACHE is non-NULL,
1062    the necessary information will be recorded.  */
1063
1064 static inline int
1065 nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1066                                struct nds32_frame_cache *cache)
1067 {
1068   if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1069       && N32_IMM15S (insn) > 0)
1070     /* addi $sp, $sp, imm15s */
1071     return INSN_RESET_SP;
1072   else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1073            && N32_IMM15S (insn) < 0)
1074     /* addi $sp, $fp, imm15s */
1075     return INSN_RESET_SP;
1076   else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1077            && N32_RA5 (insn) == REG_SP)
1078     {
1079       /* lmw.bim Rb, [$sp], Re, enable4 */
1080       if (cache != NULL)
1081         nds32_pop_multiple_words (cache, N32_RT5 (insn),
1082                                   N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1083
1084       return INSN_RECOVER;
1085     }
1086   else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1087     /* ret $lp */
1088     return INSN_RETURN;
1089   else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1090            || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1091     /* add $sp, $sp, $ta */
1092     /* add $sp, $ta, $sp */
1093     return INSN_RESET_SP;
1094   else if (abi_use_fpr
1095            && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1096     {
1097       if (__GF (insn, 12, 1) == 0)
1098         /* fldi FDt, [$sp + (imm12s << 2)] */
1099         return INSN_RECOVER;
1100       else
1101         {
1102           /* fldi.bi FDt, [$sp], (imm12s << 2) */
1103           int offset = N32_IMM12S (insn) << 2;
1104
1105           if (offset == 8 || offset == 12)
1106             {
1107               if (cache != NULL)
1108                 cache->sp_offset += offset;
1109
1110               return INSN_RECOVER;
1111             }
1112         }
1113     }
1114
1115   return INSN_NORMAL;
1116 }
1117
1118 /* Helper function for analyzing the given 16-bit INSN.  If CACHE is non-NULL,
1119    the necessary information will be recorded.  */
1120
1121 static inline int
1122 nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1123 {
1124   if (insn == N16_TYPE5 (RET5, REG_LP))
1125     /* ret5 $lp */
1126     return INSN_RETURN;
1127   else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1128     {
1129       /* addi10s.sp */
1130       int imm10s = N16_IMM10S (insn);
1131
1132       if (imm10s > 0)
1133         {
1134           if (cache != NULL)
1135             cache->sp_offset += imm10s;
1136
1137           return INSN_RECOVER;
1138         }
1139     }
1140   else if (__GF (insn, 7, 8) == N16_T25_POP25)
1141     {
1142       /* pop25 */
1143       if (cache != NULL)
1144         {
1145           int imm8u = (insn & 0x1f) << 3;
1146           int re = (insn >> 5) & 0x3;
1147           const int reg_map[] = { 6, 8, 10, 14 };
1148
1149           /* Operation 1 -- sp = sp + (imm5u << 3) */
1150           cache->sp_offset += imm8u;
1151
1152           /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1153           nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1154         }
1155
1156       /* Operation 3 -- ret $lp */
1157       return INSN_RECOVER_RETURN;
1158     }
1159
1160   return INSN_NORMAL;
1161 }
1162
1163 /* Analyze a reasonable amount of instructions from the given PC to find
1164    the instruction used to return to the caller.  Return 1 if the 'return'
1165    instruction could be found, 0 otherwise.
1166
1167    If CACHE is non-NULL, fill it in.  */
1168
1169 static int
1170 nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1171                         struct nds32_frame_cache *cache)
1172 {
1173   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1174   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1175   CORE_ADDR limit_pc;
1176   uint32_t insn, insn_len;
1177   int insn_type = INSN_NORMAL;
1178
1179   if (abi_use_fpr)
1180     limit_pc = pc + 48;
1181   else
1182     limit_pc = pc + 16;
1183
1184   for (; pc < limit_pc; pc += insn_len)
1185     {
1186       insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1187
1188       if ((insn & 0x80000000) == 0)
1189         {
1190           /* 32-bit instruction */
1191           insn_len = 4;
1192
1193           insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1194           if (insn_type == INSN_RETURN)
1195             return 1;
1196           else if (insn_type == INSN_RECOVER)
1197             continue;
1198         }
1199       else
1200         {
1201           /* 16-bit instruction */
1202           insn_len = 2;
1203
1204           insn >>= 16;
1205           insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1206           if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1207             return 1;
1208           else if (insn_type == INSN_RECOVER)
1209             continue;
1210         }
1211
1212       /* Stop the scan if this is an unexpected instruction.  */
1213       break;
1214     }
1215
1216   return 0;
1217 }
1218
1219 /* Implement the "stack_frame_destroyed_p" gdbarch method.  */
1220
1221 static int
1222 nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1223 {
1224   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1225   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1226   int insn_type = INSN_NORMAL;
1227   int ret_found = 0;
1228   uint32_t insn;
1229
1230   insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1231
1232   if ((insn & 0x80000000) == 0)
1233     {
1234       /* 32-bit instruction */
1235
1236       insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1237     }
1238   else
1239     {
1240       /* 16-bit instruction */
1241
1242       insn >>= 16;
1243       insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1244     }
1245
1246   if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1247     return 0;
1248
1249   /* Search the required 'return' instruction within the following reasonable
1250      instructions.  */
1251   ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1252   if (ret_found == 0)
1253     return 0;
1254
1255   /* Scan backwards to make sure that the last instruction has adjusted
1256      stack.  Both a 16-bit and a 32-bit instruction will be tried.  This is
1257      just a heuristic, so the false positives will be acceptable.  */
1258   insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1259
1260   /* Only 16-bit instructions are possible at addr - 2.  */
1261   if ((insn & 0x80000000) != 0)
1262     {
1263       /* This may be a 16-bit instruction or part of a 32-bit instruction.  */
1264
1265       insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1266       if (insn_type == INSN_RECOVER)
1267         return 1;
1268     }
1269
1270   insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1271
1272   /* If this is a 16-bit instruction at addr - 4, then there must be another
1273      16-bit instruction at addr - 2, so only 32-bit instructions need to
1274      be analyzed here.  */
1275   if ((insn & 0x80000000) == 0)
1276     {
1277       /* This may be a 32-bit instruction or part of a 32-bit instruction.  */
1278
1279       insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1280       if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1281         return 1;
1282     }
1283
1284   return 0;
1285 }
1286
1287 /* Implement the "sniffer" frame_unwind method.  */
1288
1289 static int
1290 nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1291                               const frame_info_ptr &this_frame, void **this_cache)
1292 {
1293   if (frame_relative_level (this_frame) == 0)
1294     return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1295                                           get_frame_pc (this_frame));
1296   else
1297     return 0;
1298 }
1299
1300 /* Allocate and fill in *THIS_CACHE with information needed to unwind
1301    *THIS_FRAME within epilogue.  Do not do this if *THIS_CACHE was already
1302    allocated.  Return a pointer to the current nds32_frame_cache in
1303    *THIS_CACHE.  */
1304
1305 static struct nds32_frame_cache *
1306 nds32_epilogue_frame_cache (const frame_info_ptr &this_frame, void **this_cache)
1307 {
1308   struct gdbarch *gdbarch = get_frame_arch (this_frame);
1309   struct nds32_frame_cache *cache;
1310   CORE_ADDR current_pc, current_sp;
1311   int i;
1312
1313   if (*this_cache)
1314     return (struct nds32_frame_cache *) *this_cache;
1315
1316   cache = nds32_alloc_frame_cache ();
1317   *this_cache = cache;
1318
1319   cache->pc = get_frame_func (this_frame);
1320   current_pc = get_frame_pc (this_frame);
1321   nds32_analyze_epilogue (gdbarch, current_pc, cache);
1322
1323   current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1324   cache->prev_sp = current_sp + cache->sp_offset;
1325
1326   /* Adjust all the saved registers such that they contain addresses
1327      instead of offsets.  */
1328   for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1329     if (cache->saved_regs[i] != REG_UNAVAIL)
1330       cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1331
1332   return cache;
1333 }
1334
1335 /* Implement the "this_id" frame_unwind method.  */
1336
1337 static void
1338 nds32_epilogue_frame_this_id (const frame_info_ptr &this_frame,
1339                               void **this_cache, struct frame_id *this_id)
1340 {
1341   struct nds32_frame_cache *cache
1342     = nds32_epilogue_frame_cache (this_frame, this_cache);
1343
1344   /* This marks the outermost frame.  */
1345   if (cache->prev_sp == 0)
1346     return;
1347
1348   *this_id = frame_id_build (cache->prev_sp, cache->pc);
1349 }
1350
1351 /* Implement the "prev_register" frame_unwind method.  */
1352
1353 static struct value *
1354 nds32_epilogue_frame_prev_register (const frame_info_ptr &this_frame,
1355                                     void **this_cache, int regnum)
1356 {
1357   struct nds32_frame_cache *cache
1358     = nds32_epilogue_frame_cache (this_frame, this_cache);
1359
1360   if (regnum == NDS32_SP_REGNUM)
1361     return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1362
1363   /* The PC of the previous frame is stored in the LP register of
1364      the current frame.  */
1365   if (regnum == NDS32_PC_REGNUM)
1366     regnum = NDS32_LP_REGNUM;
1367
1368   if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1369     return frame_unwind_got_memory (this_frame, regnum,
1370                                     cache->saved_regs[regnum]);
1371
1372   return frame_unwind_got_register (this_frame, regnum, regnum);
1373 }
1374
1375 static const struct frame_unwind nds32_epilogue_frame_unwind =
1376 {
1377   "nds32 epilogue",
1378   NORMAL_FRAME,
1379   default_frame_unwind_stop_reason,
1380   nds32_epilogue_frame_this_id,
1381   nds32_epilogue_frame_prev_register,
1382   NULL,
1383   nds32_epilogue_frame_sniffer
1384 };
1385
1386 \f
1387 /* Floating type and struct type that has only one floating type member
1388    can pass value using FPU registers (when FPU ABI is used).  */
1389
1390 static int
1391 nds32_check_calling_use_fpr (struct type *type)
1392 {
1393   struct type *t;
1394   enum type_code typecode;
1395
1396   t = type;
1397   while (1)
1398     {
1399       t = check_typedef (t);
1400       typecode = t->code ();
1401       if (typecode != TYPE_CODE_STRUCT)
1402         break;
1403       else if (t->num_fields () != 1)
1404         return 0;
1405       else
1406         t = t->field (0).type ();
1407     }
1408
1409   return typecode == TYPE_CODE_FLT;
1410 }
1411
1412 /* Implement the "push_dummy_call" gdbarch method.  */
1413
1414 static CORE_ADDR
1415 nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1416                        struct regcache *regcache, CORE_ADDR bp_addr,
1417                        int nargs, struct value **args, CORE_ADDR sp,
1418                        function_call_return_method return_method,
1419                        CORE_ADDR struct_addr)
1420 {
1421   const int REND = 6;           /* End for register offset.  */
1422   int goff = 0;                 /* Current gpr offset for argument.  */
1423   int foff = 0;                 /* Current fpr offset for argument.  */
1424   int soff = 0;                 /* Current stack offset for argument.  */
1425   int i;
1426   ULONGEST regval;
1427   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1428   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1429   struct type *func_type = function->type ();
1430   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1431   int abi_split = nds32_abi_split (tdep->elf_abi);
1432
1433   /* Set the return address.  For the NDS32, the return breakpoint is
1434      always at BP_ADDR.  */
1435   regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1436
1437   /* If STRUCT_RETURN is true, then the struct return address (in
1438      STRUCT_ADDR) will consume the first argument-passing register.
1439      Both adjust the register count and store that value.  */
1440   if (return_method == return_method_struct)
1441     {
1442       regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1443       goff++;
1444     }
1445
1446   /* Now make sure there's space on the stack */
1447   for (i = 0; i < nargs; i++)
1448     {
1449       struct type *type = args[i]->type ();
1450       int align = type_align (type);
1451
1452       /* If align is zero, it may be an empty struct.
1453          Just ignore the argument of empty struct.  */
1454       if (align == 0)
1455         continue;
1456
1457       sp -= type->length ();
1458       sp = align_down (sp, align);
1459     }
1460
1461   /* Stack must be 8-byte aligned.  */
1462   sp = align_down (sp, 8);
1463
1464   soff = 0;
1465   for (i = 0; i < nargs; i++)
1466     {
1467       const gdb_byte *val;
1468       int align, len;
1469       struct type *type;
1470       int calling_use_fpr;
1471       int use_fpr = 0;
1472
1473       type = args[i]->type ();
1474       calling_use_fpr = nds32_check_calling_use_fpr (type);
1475       len = type->length ();
1476       align = type_align (type);
1477       val = args[i]->contents ().data ();
1478
1479       /* The size of a composite type larger than 4 bytes will be rounded
1480          up to the nearest multiple of 4.  */
1481       if (len > 4)
1482         len = align_up (len, 4);
1483
1484       /* Variadic functions are handled differently between AABI and ABI2FP+.
1485
1486          For AABI, the caller pushes arguments in registers, callee stores
1487          unnamed arguments in stack, and then va_arg fetch arguments in stack.
1488          Therefore, we don't have to handle variadic functions specially.
1489
1490          For ABI2FP+, the caller pushes only named arguments in registers
1491          and pushes all unnamed arguments in stack.  */
1492
1493       if (abi_use_fpr && func_type->has_varargs ()
1494           && i >= func_type->num_fields ())
1495         goto use_stack;
1496
1497       /* Try to use FPRs to pass arguments only when
1498          1. The program is built using toolchain with FPU support.
1499          2. The type of this argument can use FPR to pass value.  */
1500       use_fpr = abi_use_fpr && calling_use_fpr;
1501
1502       if (use_fpr)
1503         {
1504           if (tdep->fpu_freg == -1)
1505             goto error_no_fpr;
1506
1507           /* Adjust alignment.  */
1508           if ((align >> 2) > 0)
1509             foff = align_up (foff, align >> 2);
1510
1511           if (foff < REND)
1512             {
1513               switch (len)
1514                 {
1515                 case 4:
1516                   regcache->cooked_write (tdep->fs0_regnum + foff, val);
1517                   foff++;
1518                   break;
1519                 case 8:
1520                   regcache->cooked_write (NDS32_FD0_REGNUM + (foff >> 1), val);
1521                   foff += 2;
1522                   break;
1523                 default:
1524                   /* Long double?  */
1525                   internal_error ("Do not know how to handle %d-byte double.\n",
1526                                   len);
1527                   break;
1528                 }
1529               continue;
1530             }
1531         }
1532       else
1533         {
1534           /*
1535              When passing arguments using GPRs,
1536
1537              * A composite type not larger than 4 bytes is passed in $rN.
1538                The format is as if the value is loaded with load instruction
1539                of corresponding size (e.g., LB, LH, LW).
1540
1541                For example,
1542
1543                        r0
1544                        31      0
1545                LITTLE: [x x b a]
1546                   BIG: [x x a b]
1547
1548              * Otherwise, a composite type is passed in consecutive registers.
1549                The size is rounded up to the nearest multiple of 4.
1550                The successive registers hold the parts of the argument as if
1551                were loaded using lmw instructions.
1552
1553                For example,
1554
1555                        r0        r1
1556                        31      0 31      0
1557                LITTLE: [d c b a] [x x x e]
1558                   BIG: [a b c d] [e x x x]
1559            */
1560
1561           /* Adjust alignment.  */
1562           if ((align >> 2) > 0)
1563             goff = align_up (goff, align >> 2);
1564
1565           if (len <= (REND - goff) * 4)
1566             {
1567               /* This argument can be passed wholly via GPRs.  */
1568               while (len > 0)
1569                 {
1570                   regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1571                                                      byte_order);
1572                   regcache_cooked_write_unsigned (regcache,
1573                                                   NDS32_R0_REGNUM + goff,
1574                                                   regval);
1575                   len -= 4;
1576                   val += 4;
1577                   goff++;
1578                 }
1579               continue;
1580             }
1581           else if (abi_split)
1582             {
1583               /* Some parts of this argument can be passed via GPRs.  */
1584               while (goff < REND)
1585                 {
1586                   regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1587                                                      byte_order);
1588                   regcache_cooked_write_unsigned (regcache,
1589                                                   NDS32_R0_REGNUM + goff,
1590                                                   regval);
1591                   len -= 4;
1592                   val += 4;
1593                   goff++;
1594                 }
1595             }
1596         }
1597
1598 use_stack:
1599       /*
1600          When pushing (split parts of) an argument into stack,
1601
1602          * A composite type not larger than 4 bytes is copied to different
1603            base address.
1604            In little-endian, the first byte of this argument is aligned
1605            at the low address of the next free word.
1606            In big-endian, the last byte of this argument is aligned
1607            at the high address of the next free word.
1608
1609            For example,
1610
1611            sp [ - ]  [ c ] hi
1612               [ c ]  [ b ]
1613               [ b ]  [ a ]
1614               [ a ]  [ - ] lo
1615              LITTLE   BIG
1616        */
1617
1618       /* Adjust alignment.  */
1619       soff = align_up (soff, align);
1620
1621       while (len > 0)
1622         {
1623           int rlen = (len > 4) ? 4 : len;
1624
1625           if (byte_order == BFD_ENDIAN_BIG)
1626             write_memory (sp + soff + 4 - rlen, val, rlen);
1627           else
1628             write_memory (sp + soff, val, rlen);
1629
1630           len -= 4;
1631           val += 4;
1632           soff += 4;
1633         }
1634     }
1635
1636   /* Finally, update the SP register.  */
1637   regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1638
1639   return sp;
1640
1641 error_no_fpr:
1642   /* If use_fpr, but no floating-point register exists,
1643      then it is an error.  */
1644   error (_("Fail to call. FPU registers are required."));
1645 }
1646 \f
1647 /* Read, for architecture GDBARCH, a function return value of TYPE
1648    from REGCACHE, and copy that into VALBUF.  */
1649
1650 static void
1651 nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1652                             struct regcache *regcache, gdb_byte *valbuf)
1653 {
1654   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1655   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1656   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1657   int calling_use_fpr;
1658   int len;
1659
1660   calling_use_fpr = nds32_check_calling_use_fpr (type);
1661   len = type->length ();
1662
1663   if (abi_use_fpr && calling_use_fpr)
1664     {
1665       if (len == 4)
1666         regcache->cooked_read (tdep->fs0_regnum, valbuf);
1667       else if (len == 8)
1668         regcache->cooked_read (NDS32_FD0_REGNUM, valbuf);
1669       else
1670         internal_error (_("Cannot extract return value of %d bytes "
1671                           "long floating-point."), len);
1672     }
1673   else
1674     {
1675       /*
1676          When returning result,
1677
1678          * A composite type not larger than 4 bytes is returned in $r0.
1679            The format is as if the result is loaded with load instruction
1680            of corresponding size (e.g., LB, LH, LW).
1681
1682            For example,
1683
1684                    r0
1685                    31      0
1686            LITTLE: [x x b a]
1687               BIG: [x x a b]
1688
1689          * Otherwise, a composite type not larger than 8 bytes is returned
1690            in $r0 and $r1.
1691            In little-endian, the first word is loaded in $r0.
1692            In big-endian, the last word is loaded in $r1.
1693
1694            For example,
1695
1696                    r0        r1
1697                    31      0 31      0
1698            LITTLE: [d c b a] [x x x e]
1699               BIG: [x x x a] [b c d e]
1700        */
1701
1702       ULONGEST tmp;
1703
1704       if (len < 4)
1705         {
1706           /* By using store_unsigned_integer we avoid having to do
1707              anything special for small big-endian values.  */
1708           regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1709           store_unsigned_integer (valbuf, len, byte_order, tmp);
1710         }
1711       else if (len == 4)
1712         {
1713           regcache->cooked_read (NDS32_R0_REGNUM, valbuf);
1714         }
1715       else if (len < 8)
1716         {
1717           int len1, len2;
1718
1719           len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1720           len2 = len - len1;
1721
1722           regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1723           store_unsigned_integer (valbuf, len1, byte_order, tmp);
1724
1725           regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1726           store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1727         }
1728       else
1729         {
1730           regcache->cooked_read (NDS32_R0_REGNUM, valbuf);
1731           regcache->cooked_read (NDS32_R0_REGNUM + 1, valbuf + 4);
1732         }
1733     }
1734 }
1735
1736 /* Write, for architecture GDBARCH, a function return value of TYPE
1737    from VALBUF into REGCACHE.  */
1738
1739 static void
1740 nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1741                           struct regcache *regcache, const gdb_byte *valbuf)
1742 {
1743   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1744   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1745   int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1746   int calling_use_fpr;
1747   int len;
1748
1749   calling_use_fpr = nds32_check_calling_use_fpr (type);
1750   len = type->length ();
1751
1752   if (abi_use_fpr && calling_use_fpr)
1753     {
1754       if (len == 4)
1755         regcache->cooked_write (tdep->fs0_regnum, valbuf);
1756       else if (len == 8)
1757         regcache->cooked_write (NDS32_FD0_REGNUM, valbuf);
1758       else
1759         internal_error (_("Cannot store return value of %d bytes "
1760                           "long floating-point."), len);
1761     }
1762   else
1763     {
1764       ULONGEST regval;
1765
1766       if (len < 4)
1767         {
1768           regval = extract_unsigned_integer (valbuf, len, byte_order);
1769           regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1770         }
1771       else if (len == 4)
1772         {
1773           regcache->cooked_write (NDS32_R0_REGNUM, valbuf);
1774         }
1775       else if (len < 8)
1776         {
1777           int len1, len2;
1778
1779           len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1780           len2 = len - len1;
1781
1782           regval = extract_unsigned_integer (valbuf, len1, byte_order);
1783           regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1784
1785           regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1786           regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1787                                           regval);
1788         }
1789       else
1790         {
1791           regcache->cooked_write (NDS32_R0_REGNUM, valbuf);
1792           regcache->cooked_write (NDS32_R0_REGNUM + 1, valbuf + 4);
1793         }
1794     }
1795 }
1796
1797 /* Implement the "return_value" gdbarch method.
1798
1799    Determine, for architecture GDBARCH, how a return value of TYPE
1800    should be returned.  If it is supposed to be returned in registers,
1801    and READBUF is non-zero, read the appropriate value from REGCACHE,
1802    and copy it into READBUF.  If WRITEBUF is non-zero, write the value
1803    from WRITEBUF into REGCACHE.  */
1804
1805 static enum return_value_convention
1806 nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1807                     struct type *type, struct regcache *regcache,
1808                     gdb_byte *readbuf, const gdb_byte *writebuf)
1809 {
1810   if (type->length () > 8)
1811     {
1812       return RETURN_VALUE_STRUCT_CONVENTION;
1813     }
1814   else
1815     {
1816       if (readbuf != NULL)
1817         nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1818       if (writebuf != NULL)
1819         nds32_store_return_value (gdbarch, type, regcache, writebuf);
1820
1821       return RETURN_VALUE_REGISTER_CONVENTION;
1822     }
1823 }
1824 \f
1825 /* Implement the "get_longjmp_target" gdbarch method.  */
1826
1827 static int
1828 nds32_get_longjmp_target (const frame_info_ptr &frame, CORE_ADDR *pc)
1829 {
1830   gdb_byte buf[4];
1831   CORE_ADDR jb_addr;
1832   struct gdbarch *gdbarch = get_frame_arch (frame);
1833   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1834
1835   jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1836
1837   if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1838     return 0;
1839
1840   *pc = extract_unsigned_integer (buf, 4, byte_order);
1841   return 1;
1842 }
1843 \f
1844 /* Validate the given TDESC, and fixed-number some registers in it.
1845    Return 0 if the given TDESC does not contain the required feature
1846    or not contain required registers.  */
1847
1848 static int
1849 nds32_validate_tdesc_p (const struct target_desc *tdesc,
1850                         struct tdesc_arch_data *tdesc_data,
1851                         int *fpu_freg, int *use_pseudo_fsrs)
1852 {
1853   const struct tdesc_feature *feature;
1854   int i, valid_p;
1855
1856   feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1857   if (feature == NULL)
1858     return 0;
1859
1860   valid_p = 1;
1861   /* Validate and fixed-number R0-R10.  */
1862   for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1863     valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1864                                         nds32_register_names[i]);
1865
1866   /* Validate R15.  */
1867   valid_p &= tdesc_unnumbered_register (feature,
1868                                         nds32_register_names[NDS32_TA_REGNUM]);
1869
1870   /* Validate and fixed-number FP, GP, LP, SP, PC.  */
1871   for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1872     valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1873                                         nds32_register_names[i]);
1874
1875   if (!valid_p)
1876     return 0;
1877
1878   /* Fixed-number R11-R27.  */
1879   for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1880     tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1881
1882   feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1883   if (feature != NULL)
1884     {
1885       int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1886       int freg = -1;
1887
1888       /* Guess FPU configuration via listed registers.  */
1889       if (tdesc_unnumbered_register (feature, "fd31"))
1890         freg = 3;
1891       else if (tdesc_unnumbered_register (feature, "fd15"))
1892         freg = 2;
1893       else if (tdesc_unnumbered_register (feature, "fd7"))
1894         freg = 1;
1895       else if (tdesc_unnumbered_register (feature, "fd3"))
1896         freg = 0;
1897
1898       if (freg == -1)
1899         /* Required FDR is not found.  */
1900         return 0;
1901       else
1902         *fpu_freg = freg;
1903
1904       /* Validate and fixed-number required FDRs.  */
1905       num_fdr_regs = num_fdr_map[freg];
1906       for (i = 0; i < num_fdr_regs; i++)
1907         valid_p &= tdesc_numbered_register (feature, tdesc_data,
1908                                             NDS32_FD0_REGNUM + i,
1909                                             nds32_fdr_register_names[i]);
1910       if (!valid_p)
1911         return 0;
1912
1913       /* Count the number of listed FSRs, and fixed-number them if present.  */
1914       num_fsr_regs = num_fsr_map[freg];
1915       fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
1916       num_listed_fsr = 0;
1917       for (i = 0; i < num_fsr_regs; i++)
1918         num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
1919                                                    fs0_regnum + i,
1920                                                    nds32_fsr_register_names[i]);
1921
1922       if (num_listed_fsr == 0)
1923         /* No required FSRs are listed explicitly,  make them pseudo registers
1924            of FDRs.  */
1925         *use_pseudo_fsrs = 1;
1926       else if (num_listed_fsr == num_fsr_regs)
1927         /* All required FSRs are listed explicitly.  */
1928         *use_pseudo_fsrs = 0;
1929       else
1930         /* Some required FSRs are missing.  */
1931         return 0;
1932     }
1933
1934   return 1;
1935 }
1936
1937 /* Initialize the current architecture based on INFO.  If possible,
1938    re-use an architecture from ARCHES, which is a list of
1939    architectures already created during this debugging session.
1940
1941    Called e.g. at program startup, when reading a core file, and when
1942    reading a binary file.  */
1943
1944 static struct gdbarch *
1945 nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1946 {
1947   struct gdbarch_list *best_arch;
1948   tdesc_arch_data_up tdesc_data;
1949   const struct target_desc *tdesc = info.target_desc;
1950   int elf_abi = E_NDS_ABI_AABI;
1951   int fpu_freg = -1;
1952   int use_pseudo_fsrs = 0;
1953   int i, num_regs, maxregs;
1954
1955   /* Extract the elf_flags if available.  */
1956   if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1957     elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
1958
1959   /* If there is already a candidate, use it.  */
1960   for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
1961        best_arch != NULL;
1962        best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
1963     {
1964       nds32_gdbarch_tdep *idep
1965         = gdbarch_tdep<nds32_gdbarch_tdep> (best_arch->gdbarch);
1966
1967       if (idep->elf_abi != elf_abi)
1968         continue;
1969
1970       /* Found a match.  */
1971       break;
1972     }
1973
1974   if (best_arch != NULL)
1975     return best_arch->gdbarch;
1976
1977   if (!tdesc_has_registers (tdesc))
1978     tdesc = tdesc_nds32;
1979
1980   tdesc_data = tdesc_data_alloc ();
1981
1982   if (!nds32_validate_tdesc_p (tdesc, tdesc_data.get (), &fpu_freg,
1983                                &use_pseudo_fsrs))
1984     return NULL;
1985
1986   /* Allocate space for the new architecture.  */
1987   gdbarch *gdbarch
1988     = gdbarch_alloc (&info, gdbarch_tdep_up (new nds32_gdbarch_tdep));
1989   nds32_gdbarch_tdep *tdep = gdbarch_tdep<nds32_gdbarch_tdep> (gdbarch);
1990
1991   tdep->fpu_freg = fpu_freg;
1992   tdep->use_pseudo_fsrs = use_pseudo_fsrs;
1993   tdep->fs0_regnum = -1;
1994   tdep->elf_abi = elf_abi;
1995
1996   set_gdbarch_wchar_bit (gdbarch, 16);
1997   set_gdbarch_wchar_signed (gdbarch, 0);
1998
1999   if (fpu_freg == -1)
2000     num_regs = NDS32_NUM_REGS;
2001   else if (use_pseudo_fsrs == 1)
2002     {
2003       set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2004       set_gdbarch_deprecated_pseudo_register_write
2005         (gdbarch, nds32_pseudo_register_write);
2006       set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2007       set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2008       set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2009
2010       num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2011     }
2012   else
2013     num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2014
2015   set_gdbarch_num_regs (gdbarch, num_regs);
2016   tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
2017
2018   /* Cache the register number of fs0.  */
2019   if (fpu_freg != -1)
2020     tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2021
2022   /* Add NDS32 register aliases.  To avoid search in user register name space,
2023      user_reg_map_name_to_regnum is not used.  */
2024   maxregs = gdbarch_num_cooked_regs (gdbarch);
2025   for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2026     {
2027       int regnum, j;
2028
2029       regnum = -1;
2030       /* Search register name space.  */
2031       for (j = 0; j < maxregs; j++)
2032         {
2033           const char *regname = gdbarch_register_name (gdbarch, j);
2034
2035           if (strcmp (regname, nds32_register_aliases[i].name) == 0)
2036             {
2037               regnum = j;
2038               break;
2039             }
2040         }
2041
2042       /* Try next alias entry if the given name can not be found in register
2043          name space.  */
2044       if (regnum == -1)
2045         continue;
2046
2047       user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2048                     value_of_nds32_reg, (const void *) (intptr_t) regnum);
2049     }
2050
2051   nds32_add_reggroups (gdbarch);
2052
2053   /* Hook in ABI-specific overrides, if they have been registered.  */
2054   info.tdesc_data = tdesc_data.get ();
2055   gdbarch_init_osabi (info, gdbarch);
2056
2057   /* Override tdesc_register callbacks for system registers.  */
2058   set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2059
2060   set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2061   set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2062   set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2063   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2064
2065   set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2066   set_gdbarch_return_value (gdbarch, nds32_return_value);
2067
2068   set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2069   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2070   set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2071                                        nds32_breakpoint::kind_from_pc);
2072   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2073                                        nds32_breakpoint::bp_from_kind);
2074
2075   set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2076   frame_base_set_default (gdbarch, &nds32_frame_base);
2077
2078   /* Handle longjmp.  */
2079   set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2080
2081   /* The order of appending is the order it check frame.  */
2082   dwarf2_append_unwinders (gdbarch);
2083   frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2084   frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2085
2086   return gdbarch;
2087 }
2088
2089 void _initialize_nds32_tdep ();
2090 void
2091 _initialize_nds32_tdep ()
2092 {
2093   /* Initialize gdbarch.  */
2094   gdbarch_register (bfd_arch_nds32, nds32_gdbarch_init);
2095
2096   initialize_tdesc_nds32 ();
2097   nds32_init_reggroups ();
2098 }