| blob | e67aea8e66d6b6c43e46bf15bc46ea966a487836 |
1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2022 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
43 #include <algorithm>
54 /* Note that the AMD64 architecture was previously known as x86-64.
55 The latter is (forever) engraved into the canonical system name as
56 returned by config.guess, and used as the name for the AMD64 port
57 of GNU/Linux. The BSD's have renamed their ports to amd64; they
58 don't like to shout. For GDB we prefer the amd64_-prefix over the
59 x86_64_-prefix since it's so much easier to type. */
61 /* Register information. */
64 {
67 /* %r8 is indeed register number 8. */
71 /* %st0 is register number 24. */
75 /* %xmm0 is register number 40. */
79 };
82 {
87 };
90 {
95 };
98 {
103 };
106 {
111 };
114 {
116 };
119 {
122 };
125 {
134 };
137 {
146 };
153 };
156 "pkru"
157 };
159 /* DWARF Register Number Mapping as defined in the System V psABI,
160 section 3.6. */
163 {
164 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
169 /* Frame Pointer Register RBP. */
170 AMD64_RBP_REGNUM,
172 /* Stack Pointer Register RSP. */
173 AMD64_RSP_REGNUM,
175 /* Extended Integer Registers 8 - 15. */
185 /* Return Address RA. Mapped to RIP. */
186 AMD64_RIP_REGNUM,
188 /* SSE Registers 0 - 7. */
194 /* Extended SSE Registers 8 - 15. */
200 /* Floating Point Registers 0-7. */
206 /* MMX Registers 0 - 7.
207 We have to handle those registers specifically, as their register
208 number within GDB depends on the target (or they may even not be
209 available at all). */
212 /* Control and Status Flags Register. */
213 AMD64_EFLAGS_REGNUM,
215 /* Selector Registers. */
216 AMD64_ES_REGNUM,
217 AMD64_CS_REGNUM,
218 AMD64_SS_REGNUM,
219 AMD64_DS_REGNUM,
220 AMD64_FS_REGNUM,
221 AMD64_GS_REGNUM,
225 /* Segment Base Address Registers. */
231 /* Special Selector Registers. */
235 /* Floating Point Control Registers. */
236 AMD64_MXCSR_REGNUM,
237 AMD64_FCTRL_REGNUM,
238 AMD64_FSTAT_REGNUM
239 };
244 /* Convert DWARF register number REG to the appropriate register
245 number used by GDB. */
247 static int
249 {
262 }
264 /* Map architectural register numbers to gdb register numbers. */
267 {
283 AMD64_R15_REGNUM /* %r15 */
284 };
289 /* Convert architectural register number REG to the appropriate register
290 number used by GDB. */
292 static int
294 {
298 }
300 /* Register names for byte pseudo-registers. */
303 {
307 };
309 /* Number of lower byte registers. */
310 #define AMD64_NUM_LOWER_BYTE_REGS 16
312 /* Register names for word pseudo-registers. */
315 {
318 };
320 /* Register names for dword pseudo-registers. */
323 {
326 "eip"
327 };
329 /* Return the name of register REGNUM. */
333 {
347 else
349 }
355 {
364 {
367 /* Extract (always little endian). */
369 {
373 /* Special handling for AH, BH, CH, DH. */
377 else
380 }
381 else
382 {
387 else
390 }
391 }
393 {
396 /* Extract (always little endian). */
400 else
403 }
404 else
406 result_value);
409 }
411 static void
415 {
419 {
423 {
427 /* Read ... AH, BH, CH, DH. */
429 /* ... Modify ... (always little endian). */
431 /* ... Write. */
433 }
434 else
435 {
438 /* Read ... */
440 /* ... Modify ... (always little endian). */
442 /* ... Write. */
444 }
445 }
447 {
451 /* Read ... */
453 /* ... Modify ... (always little endian). */
455 /* ... Write. */
457 }
458 else
460 }
462 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
464 static int
467 {
471 {
476 else
479 }
481 {
486 }
487 else
489 }
491 \f
493 /* Register classes as defined in the psABI. */
495 enum amd64_reg_class
496 {
497 AMD64_INTEGER,
498 AMD64_SSE,
499 AMD64_SSEUP,
500 AMD64_X87,
501 AMD64_X87UP,
502 AMD64_COMPLEX_X87,
503 AMD64_NO_CLASS,
504 AMD64_MEMORY
505 };
507 /* Return the union class of CLASS1 and CLASS2. See the psABI for
508 details. */
510 static enum amd64_reg_class
512 {
513 /* Rule (a): If both classes are equal, this is the resulting class. */
517 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
518 is the other class. */
524 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
528 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
532 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
533 MEMORY is used as class. */
539 /* Rule (f): Otherwise class SSE is used. */
541 }
545 /* Return true if TYPE is a structure or union with unaligned fields. */
547 static bool
549 {
552 {
554 {
557 /* Ignore static fields, empty fields (for example nested
558 empty structures), and bitfields (these are handled by
559 the caller). */
581 }
582 }
585 }
587 /* Classify field I of TYPE starting at BITOFFSET according to the rules for
588 structures and union types, and store the result in THECLASS. */
590 static void
594 {
602 /* Ignore static fields, or empty fields, for example nested
603 empty structures.*/
613 {
614 /* Each field of an object is classified recursively. */
619 }
626 /* This is a bit of an odd case: We have a field that would
627 normally fit in one of the two eightbytes, except that
628 it is placed in a way that this field straddles them.
629 This has been seen with a structure containing an array.
631 The ABI is a bit unclear in this case, but we assume that
632 this field's class (stored in subclass[0]) must also be merged
633 into class[1]. In other words, our field has a piece stored
634 in the second eight-byte, and thus its class applies to
635 the second eight-byte as well.
637 In the case where the field length exceeds 8 bytes,
638 it should not be necessary to merge the field class
639 into class[1]. As LEN > 8, subclass[1] is necessarily
640 different from AMD64_NO_CLASS. If subclass[1] is equal
641 to subclass[0], then the normal class[1]/subclass[1]
642 merging will take care of everything. For subclass[1]
643 to be different from subclass[0], I can only see the case
644 where we have a SSE/SSEUP or X87/X87UP pair, which both
645 use up all 16 bytes of the aggregate, and are already
646 handled just fine (because each portion sits on its own
647 8-byte). */
651 }
653 /* Classify TYPE according to the rules for aggregate (structures and
654 arrays) and union types, and store the result in CLASS. */
656 static void
658 {
659 /* 1. If the size of an object is larger than two times eight bytes, or
660 it is a non-trivial C++ object, or it has unaligned fields, then it
661 has class memory.
663 It is important that the trivially_copyable check is before the
664 unaligned fields check, as C++ classes with virtual base classes
665 will have fields (for the virtual base classes) with non-constant
666 loc_bitpos attributes, which will cause an assert to trigger within
667 the unaligned field check. As classes with virtual bases are not
668 trivially copyable, checking that first avoids this problem. */
672 {
675 }
677 /* 2. Both eightbytes get initialized to class NO_CLASS. */
680 /* 3. Each field of an object is classified recursively so that
681 always two fields are considered. The resulting class is
682 calculated according to the classes of the fields in the
683 eightbyte: */
686 {
689 /* All fields in an array have the same type. */
693 }
694 else
695 {
698 /* Structure or union. */
704 }
706 /* 4. Then a post merger cleanup is done: */
708 /* Rule (a): If one of the classes is MEMORY, the whole argument is
709 passed in memory. */
713 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
714 SSE. */
719 }
721 /* Classify TYPE, and store the result in CLASS. */
723 static void
725 {
731 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
732 long, long long, and pointers are in the INTEGER class. Similarly,
733 range types, used by languages such as Ada, are also in the INTEGER
734 class. */
742 /* Arguments of types _Float16, float, double, _Decimal32, _Decimal64 and
743 __m64 are in class SSE. */
746 /* FIXME: __m64 . */
749 /* Arguments of types __float128, _Decimal128 and __m128 are split into
750 two halves. The least significant ones belong to class SSE, the most
751 significant one to class SSEUP. */
753 /* FIXME: __float128, __m128. */
756 /* The 64-bit mantissa of arguments of type long double belongs to
757 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
758 class X87UP. */
760 /* Class X87 and X87UP. */
763 /* Arguments of complex T - where T is one of the types _Float16, float or
764 double - get treated as if they are implemented as:
766 struct complexT {
767 T real;
768 T imag;
769 };
771 */
777 /* A variable of type complex long double is classified as type
778 COMPLEX_X87. */
782 /* Aggregates. */
786 }
788 static enum return_value_convention
792 {
803 /* 1. Classify the return type with the classification algorithm. */
806 /* 2. If the type has class MEMORY, then the caller provides space
807 for the return value and passes the address of this storage in
808 %rdi as if it were the first argument to the function. In effect,
809 this address becomes a hidden first argument.
811 On return %rax will contain the address that has been passed in
812 by the caller in %rdi. */
814 {
815 /* As indicated by the comment above, the ABI guarantees that we
816 can always find the return value just after the function has
817 returned. */
820 {
821 ULONGEST addr;
825 }
828 }
830 /* 8. If the class is COMPLEX_X87, the real part of the value is
831 returned in %st0 and the imaginary part in %st1. */
833 {
835 {
838 }
841 {
846 /* Fix up the tag word such that both %st(0) and %st(1) are
847 marked as valid. */
849 }
852 }
858 {
863 {
865 /* 3. If the class is INTEGER, the next available register
866 of the sequence %rax, %rdx is used. */
871 /* 4. If the class is SSE, the next available SSE register
872 of the sequence %xmm0, %xmm1 is used. */
877 /* 5. If the class is SSEUP, the eightbyte is passed in the
878 upper half of the last used SSE register. */
885 /* 6. If the class is X87, the value is returned on the X87
886 stack in %st0 as 80-bit x87 number. */
893 /* 7. If the class is X87UP, the value is returned together
894 with the previous X87 value in %st0. */
906 }
916 }
919 }
920 \f
922 static CORE_ADDR
925 {
927 {
933 AMD64_R9_REGNUM /* %r9 */
934 };
936 {
937 /* %xmm0 ... %xmm7 */
942 };
951 /* Reserve a register for the "hidden" argument. */
953 integer_reg++;
956 {
964 /* Classify argument. */
967 /* Calculate the number of integer and SSE registers needed for
968 this argument. */
970 {
972 needed_integer_regs++;
974 needed_sse_regs++;
975 }
977 /* Check whether enough registers are available, and if the
978 argument should be passed in registers at all. */
982 {
983 /* The argument will be passed on the stack. */
986 }
987 else
988 {
989 /* The argument will be passed in registers. */
996 {
1001 {
1021 }
1027 }
1028 }
1029 }
1031 /* Allocate space for the arguments on the stack. */
1034 /* The psABI says that "The end of the input argument area shall be
1035 aligned on a 16 byte boundary." */
1038 /* Write out the arguments to the stack. */
1040 {
1047 }
1049 /* The psABI says that "For calls that may call functions that use
1050 varargs or stdargs (prototype-less calls or calls to functions
1051 containing ellipsis (...) in the declaration) %al is used as
1052 hidden argument to specify the number of SSE registers used. */
1055 }
1057 static CORE_ADDR
1061 function_call_return_method return_method,
1062 CORE_ADDR struct_addr)
1063 {
1067 /* BND registers can be in arbitrary values at the moment of the
1068 inferior call. This can cause boundary violations that are not
1069 due to a real bug or even desired by the user. The best to be done
1070 is set the BND registers to allow access to the whole memory, INIT
1071 state, before pushing the inferior call. */
1074 /* Pass arguments. */
1077 /* Pass "hidden" argument". */
1079 {
1082 }
1084 /* Store return address. */
1089 /* Finally, update the stack pointer... */
1093 /* ...and fake a frame pointer. */
1097 }
1098 \f
1099 /* Displaced instruction handling. */
1101 /* A partially decoded instruction.
1102 This contains enough details for displaced stepping purposes. */
1104 struct amd64_insn
1105 {
1106 /* The number of opcode bytes. */
1108 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1109 not present. */
1111 /* The offset to the first opcode byte. */
1113 /* The offset to the modrm byte or -1 if not present. */
1116 /* The raw instruction. */
1118 };
1120 struct amd64_displaced_step_copy_insn_closure
1122 {
1125 {}
1127 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1130 ULONGEST tmp_save;
1132 /* Details of the instruction. */
1135 /* The possibly modified insn. */
1137 };
1139 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1140 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1141 at which point delete these in favor of libopcodes' versions). */
1144 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1145 /* ------------------------------- */
1162 /* ------------------------------- */
1163 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1164 };
1167 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1168 /* ------------------------------- */
1185 /* ------------------------------- */
1186 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1187 };
1191 static int
1193 {
1195 }
1197 /* True if PFX is the start of the 2-byte VEX prefix. */
1199 static bool
1201 {
1203 }
1205 /* True if PFX is the start of the 3-byte VEX prefix. */
1207 static bool
1209 {
1211 }
1213 /* Skip the legacy instruction prefixes in INSN.
1214 We assume INSN is properly sentineled so we don't have to worry
1215 about falling off the end of the buffer. */
1219 {
1221 {
1223 {
1239 }
1241 }
1244 }
1246 /* Return an integer register (other than RSP) that is unused as an input
1247 operand in INSN.
1248 In order to not require adding a rex prefix if the insn doesn't already
1249 have one, the result is restricted to RAX ... RDI, sans RSP.
1250 The register numbering of the result follows architecture ordering,
1251 e.g. RDI = 7. */
1253 static int
1255 {
1256 /* 1 bit for each reg */
1259 /* There can be at most 3 int regs used as inputs in an insn, and we have
1260 7 to choose from (RAX ... RDI, sans RSP).
1261 This allows us to take a conservative approach and keep things simple.
1262 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1263 that implicitly specify RAX. */
1265 /* Avoid RAX. */
1267 /* Similarily avoid RDX, implicit operand in divides. */
1269 /* Avoid RSP. */
1272 /* If the opcode is one byte long and there's no ModRM byte,
1273 assume the opcode specifies a register. */
1277 /* Mark used regs in the modrm/sib bytes. */
1279 {
1286 /* Assume the reg field of the modrm byte specifies a register. */
1290 {
1295 }
1296 else
1297 {
1299 }
1300 }
1305 /* Finally, find a free reg. */
1306 {
1310 {
1313 }
1315 /* We shouldn't get here. */
1317 }
1318 }
1320 /* Extract the details of INSN that we need. */
1322 static void
1324 {
1335 /* Skip legacy instruction prefixes. */
1338 /* Skip REX/VEX instruction encoding prefixes. */
1340 {
1343 }
1345 {
1346 /* Don't record the offset in this case because this prefix has
1347 no REX.B equivalent. */
1349 }
1351 {
1354 }
1359 {
1360 /* Two or three-byte opcode. */
1364 /* Check for three-byte opcode. */
1366 {
1379 }
1380 }
1381 else
1382 {
1383 /* One-byte opcode. */
1386 }
1389 {
1392 }
1393 }
1395 /* Update %rip-relative addressing in INSN.
1397 %rip-relative addressing only uses a 32-bit displacement.
1398 32 bits is not enough to be guaranteed to cover the distance between where
1399 the real instruction is and where its copy is.
1400 Convert the insn to use base+disp addressing.
1401 We set base = pc + insn_length so we can leave disp unchanged. */
1403 static void
1407 {
1411 CORE_ADDR rip_base;
1414 ULONGEST orig_value;
1416 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1419 /* Compute the rip-relative address. */
1424 /* We need a register to hold the address.
1425 Pick one not used in the insn.
1426 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1430 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1433 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1434 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1435 is not r8-r15. */
1437 {
1443 else
1445 }
1452 /* Convert the ModRM field to be base+disp. */
1462 }
1464 static void
1468 {
1472 {
1476 {
1477 /* The insn uses rip-relative addressing.
1478 Deal with it. */
1480 }
1481 }
1482 }
1484 displaced_step_copy_insn_closure_up
1488 {
1490 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1491 continually watch for running off the end of the buffer. */
1500 /* Set up the sentinel space so we don't have to worry about running
1501 off the end of the buffer. An excessive number of leading prefixes
1502 could otherwise cause this. */
1507 /* GDB may get control back after the insn after the syscall.
1508 Presumably this is a kernel bug.
1509 If this is a syscall, make sure there's a nop afterwards. */
1510 {
1515 }
1517 /* Modify the insn to cope with the address where it will be executed from.
1518 In particular, handle any rip-relative addressing. */
1527 /* This is a work around for a problem with g++ 4.8. */
1529 }
1531 static int
1533 {
1537 {
1538 /* jump near, absolute indirect (/4) */
1542 /* jump far, absolute indirect (/5) */
1545 }
1548 }
1550 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1552 static int
1554 {
1557 /* jump short, relative. */
1561 /* jump near, relative. */
1566 }
1568 static int
1570 {
1574 {
1575 /* Call near, absolute indirect (/2) */
1579 /* Call far, absolute indirect (/3) */
1582 }
1585 }
1587 static int
1589 {
1590 /* NOTE: gcc can emit "repz ; ret". */
1594 {
1604 }
1605 }
1607 static int
1609 {
1615 /* call near, relative */
1620 }
1622 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1623 length in bytes. Otherwise, return zero. */
1625 static int
1627 {
1631 {
1634 }
1637 }
1639 /* Classify the instruction at ADDR using PRED.
1640 Throw an error if the memory can't be read. */
1642 static int
1645 {
1659 }
1661 /* The gdbarch insn_is_call method. */
1663 static int
1665 {
1667 }
1669 /* The gdbarch insn_is_ret method. */
1671 static int
1673 {
1675 }
1677 /* The gdbarch insn_is_jump method. */
1679 static int
1681 {
1683 }
1685 /* Fix up the state of registers and memory after having single-stepped
1686 a displaced instruction. */
1688 void
1693 {
1694 amd64_displaced_step_copy_insn_closure *dsc
1697 /* The offset we applied to the instruction's address. */
1706 /* If we used a tmp reg, restore it. */
1709 {
1713 }
1715 /* The list of issues to contend with here is taken from
1716 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1717 Yay for Free Software! */
1719 /* Relocate the %rip back to the program's instruction stream,
1720 if necessary. */
1722 /* Except in the case of absolute or indirect jump or call
1723 instructions, or a return instruction, the new rip is relative to
1724 the displaced instruction; make it relative to the original insn.
1725 Well, signal handler returns don't need relocation either, but we use the
1726 value of %rip to recognize those; see below. */
1730 {
1731 ULONGEST orig_rip;
1736 /* A signal trampoline system call changes the %rip, resuming
1737 execution of the main program after the signal handler has
1738 returned. That makes them like 'return' instructions; we
1739 shouldn't relocate %rip.
1741 But most system calls don't, and we do need to relocate %rip.
1743 Our heuristic for distinguishing these cases: if stepping
1744 over the system call instruction left control directly after
1745 the instruction, the we relocate --- control almost certainly
1746 doesn't belong in the displaced copy. Otherwise, we assume
1747 the instruction has put control where it belongs, and leave
1748 it unrelocated. Goodness help us if there are PC-relative
1749 system calls. */
1752 /* GDB can get control back after the insn after the syscall.
1753 Presumably this is a kernel bug.
1754 Fixup ensures its a nop, we add one to the length for it. */
1757 else
1758 {
1761 /* If we just stepped over a breakpoint insn, we don't backup
1762 the pc on purpose; this is to match behaviour without
1763 stepping. */
1770 }
1771 }
1773 /* If the instruction was PUSHFL, then the TF bit will be set in the
1774 pushed value, and should be cleared. We'll leave this for later,
1775 since GDB already messes up the TF flag when stepping over a
1776 pushfl. */
1778 /* If the instruction was a call, the return address now atop the
1779 stack is the address following the copied instruction. We need
1780 to make it the address following the original instruction. */
1782 {
1783 ULONGEST rsp;
1784 ULONGEST retaddr;
1795 }
1796 }
1798 /* If the instruction INSN uses RIP-relative addressing, return the
1799 offset into the raw INSN where the displacement to be adjusted is
1800 found. Returns 0 if the instruction doesn't use RIP-relative
1801 addressing. */
1803 static int
1805 {
1807 {
1811 {
1812 /* The displacement is found right after the ModRM byte. */
1814 }
1815 }
1818 }
1820 static void
1822 {
1825 }
1827 static void
1830 {
1833 /* Extra space for sentinels. */
1844 /* Set up the sentinel space so we don't have to worry about running
1845 off the end of the buffer. An excessive number of leading prefixes
1846 could otherwise cause this. */
1854 /* Skip legacy instruction prefixes. */
1857 /* Adjust calls with 32-bit relative addresses as push/jump, with
1858 the address pushed being the location where the original call in
1859 the user program would return to. */
1861 {
1863 CORE_ADDR ret_addr;
1866 /* Where "ret" in the original code will return to. */
1869 /* If pushing an address higher than or equal to 0x80000000,
1870 avoid 'pushq', as that sign extends its 32-bit operand, which
1871 would be incorrect. */
1873 {
1877 }
1878 else
1879 {
1899 }
1901 /* Push the push. */
1904 /* Convert the relative call to a relative jump. */
1907 /* Adjust the destination offset. */
1916 /* Write the adjusted jump into its displaced location. */
1919 }
1923 {
1924 /* Adjust jumps with 32-bit relative addresses. Calls are
1925 already handled above. */
1928 /* Adjust conditional jumps. */
1931 }
1934 {
1941 }
1943 /* Write the adjusted instruction into its displaced location. */
1945 }
1947 \f
1948 /* The maximum number of saved registers. This should include %rip. */
1949 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1951 struct amd64_frame_cache
1952 {
1953 /* Base address. */
1954 CORE_ADDR base;
1956 CORE_ADDR sp_offset;
1957 CORE_ADDR pc;
1959 /* Saved registers. */
1961 CORE_ADDR saved_sp;
1964 /* Do we have a frame? */
1966 };
1968 /* Initialize a frame cache. */
1970 static void
1972 {
1975 /* Base address. */
1981 /* Saved registers. We initialize these to -1 since zero is a valid
1982 offset (that's where %rbp is supposed to be stored).
1983 The values start out as being offsets, and are later converted to
1984 addresses (at which point -1 is interpreted as an address, still meaning
1985 "invalid"). */
1991 /* Frameless until proven otherwise. */
1993 }
1995 /* Allocate and initialize a frame cache. */
1999 {
2005 }
2007 /* GCC 4.4 and later, can put code in the prologue to realign the
2008 stack pointer. Check whether PC points to such code, and update
2009 CACHE accordingly. Return the first instruction after the code
2010 sequence or CURRENT_PC, whichever is smaller. If we don't
2011 recognize the code, return PC. */
2013 static CORE_ADDR
2016 {
2017 /* There are 2 code sequences to re-align stack before the frame
2018 gets set up:
2020 1. Use a caller-saved saved register:
2022 leaq 8(%rsp), %reg
2023 andq $-XXX, %rsp
2024 pushq -8(%reg)
2026 2. Use a callee-saved saved register:
2028 pushq %reg
2029 leaq 16(%rsp), %reg
2030 andq $-XXX, %rsp
2031 pushq -8(%reg)
2033 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2035 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2036 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2037 */
2046 /* Check caller-saved saved register. The first instruction has
2047 to be "leaq 8(%rsp), %reg". */
2052 {
2053 /* MOD must be binary 10 and R/M must be binary 100. */
2057 /* REG has register number. */
2060 /* Check the REX.R bit. */
2065 }
2066 else
2067 {
2068 /* Check callee-saved saved register. The first instruction
2069 has to be "pushq %reg". */
2075 {
2076 /* Check the REX.B bit. */
2081 }
2082 else
2085 /* Get register. */
2088 offset++;
2090 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2097 /* MOD must be binary 10 and R/M must be binary 100. */
2101 /* REG has register number. */
2104 /* Check the REX.R bit. */
2108 /* Registers in pushq and leaq have to be the same. */
2113 }
2115 /* Rigister can't be %rsp nor %rbp. */
2119 /* The next instruction has to be "andq $-XXX, %rsp". */
2128 /* The next instruction has to be "pushq -8(%reg)". */
2131 offset++;
2134 {
2135 /* Check the REX.B bit. */
2139 }
2140 else
2143 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2144 01. */
2149 /* R/M has register. */
2152 /* Registers in leaq and pushq have to be the same. */
2160 }
2162 /* Similar to amd64_analyze_stack_align for x32. */
2164 static CORE_ADDR
2167 {
2168 /* There are 2 code sequences to re-align stack before the frame
2169 gets set up:
2171 1. Use a caller-saved saved register:
2173 leaq 8(%rsp), %reg
2174 andq $-XXX, %rsp
2175 pushq -8(%reg)
2177 or
2179 [addr32] leal 8(%rsp), %reg
2180 andl $-XXX, %esp
2181 [addr32] pushq -8(%reg)
2183 2. Use a callee-saved saved register:
2185 pushq %reg
2186 leaq 16(%rsp), %reg
2187 andq $-XXX, %rsp
2188 pushq -8(%reg)
2190 or
2192 pushq %reg
2193 [addr32] leal 16(%rsp), %reg
2194 andl $-XXX, %esp
2195 [addr32] pushq -8(%reg)
2197 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2199 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2200 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2202 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2204 0x83 0xe4 0xf0 andl $-16, %esp
2205 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2206 */
2215 /* Skip optional addr32 prefix. */
2218 /* Check caller-saved saved register. The first instruction has
2219 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2224 {
2225 /* MOD must be binary 10 and R/M must be binary 100. */
2229 /* REG has register number. */
2232 /* Check the REX.R bit. */
2237 }
2238 else
2239 {
2240 /* Check callee-saved saved register. The first instruction
2241 has to be "pushq %reg". */
2245 {
2246 /* Check the REX.B bit. */
2251 }
2255 /* Get register. */
2258 offset++;
2260 /* Skip optional addr32 prefix. */
2262 offset++;
2264 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2265 "leal 16(%rsp), %reg". */
2272 /* MOD must be binary 10 and R/M must be binary 100. */
2276 /* REG has register number. */
2279 /* Check the REX.R bit. */
2283 /* Registers in pushq and leaq have to be the same. */
2288 }
2290 /* Rigister can't be %rsp nor %rbp. */
2294 /* The next instruction may be "andq $-XXX, %rsp" or
2295 "andl $-XXX, %esp". */
2297 offset--;
2306 /* Skip optional addr32 prefix. */
2308 offset++;
2310 /* The next instruction has to be "pushq -8(%reg)". */
2313 offset++;
2316 {
2317 /* Check the REX.B bit. */
2321 }
2322 else
2325 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2326 01. */
2331 /* R/M has register. */
2334 /* Registers in leaq and pushq have to be the same. */
2342 }
2344 /* Do a limited analysis of the prologue at PC and update CACHE
2345 accordingly. Bail out early if CURRENT_PC is reached. Return the
2346 address where the analysis stopped.
2348 We will handle only functions beginning with:
2350 pushq %rbp 0x55
2351 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2353 or (for the X32 ABI):
2355 pushq %rbp 0x55
2356 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2358 The `endbr64` instruction can be found before these sequences, and will be
2359 skipped if found.
2361 Any function that doesn't start with one of these sequences will be
2362 assumed to have no prologue and thus no valid frame pointer in
2363 %rbp. */
2365 static CORE_ADDR
2369 {
2371 /* The `endbr64` instruction. */
2373 /* There are two variations of movq %rsp, %rbp. */
2376 /* Ditto for movl %esp, %ebp. */
2381 gdb_byte op;
2388 else
2393 /* Check for the `endbr64` instruction, skip it if found. */
2395 {
2402 }
2408 {
2409 /* Take into account that we've executed the `pushq %rbp' that
2410 starts this instruction sequence. */
2414 /* If that's all, return now. */
2420 /* Check for `movq %rsp, %rbp'. */
2423 {
2424 /* OK, we actually have a frame. */
2427 }
2429 /* For X32, also check for `movl %esp, %ebp'. */
2431 {
2434 {
2435 /* OK, we actually have a frame. */
2438 }
2439 }
2442 }
2445 }
2447 /* Work around false termination of prologue - GCC PR debug/48827.
2449 START_PC is the first instruction of a function, PC is its minimal already
2450 determined advanced address. Function returns PC if it has nothing to do.
2452 84 c0 test %al,%al
2453 74 23 je after
2454 <-- here is 0 lines advance - the false prologue end marker.
2455 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2456 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2457 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2458 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2459 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2460 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2461 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2462 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2463 after: */
2465 static CORE_ADDR
2467 {
2486 /* START_PC can be from overlayed memory, ignored here. */
2490 /* test %al,%al */
2493 /* je AFTER */
2499 {
2500 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2505 /* 0b01?????? */
2507 {
2508 /* 8-bit displacement. */
2510 }
2511 /* 0b10?????? */
2513 {
2514 /* 32-bit displacement. */
2516 }
2517 else
2519 }
2521 /* je AFTER */
2526 }
2528 /* Return PC of first real instruction. */
2530 static CORE_ADDR
2532 {
2534 CORE_ADDR pc;
2535 CORE_ADDR func_addr;
2538 {
2539 CORE_ADDR post_prologue_pc
2543 /* LLVM backend (Clang/Flang) always emits a line note before the
2544 prologue and another one after. We trust clang and newer Intel
2545 compilers to emit usable line notes. */
2552 }
2561 }
2562 \f
2564 /* Normal frames. */
2566 static void
2569 {
2578 cache);
2581 {
2582 /* We didn't find a valid frame. If we're at the start of a
2583 function, or somewhere half-way its prologue, the function's
2584 frame probably hasn't been fully setup yet. Try to
2585 reconstruct the base address for the stack frame by looking
2586 at the stack pointer. For truly "frameless" functions this
2587 might work too. */
2590 {
2591 /* Stack pointer has been saved. */
2595 /* We're halfway aligning the stack. */
2599 /* This will be added back below. */
2601 }
2602 else
2603 {
2607 }
2608 }
2609 else
2610 {
2613 }
2615 /* Now that we have the base address for the stack frame we can
2616 calculate the value of %rsp in the calling frame. */
2619 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2620 frame we find it at the same offset from the reconstructed base
2621 address. If we're halfway aligning the stack, %rip is handled
2622 differently (see above). */
2626 /* Adjust all the saved registers such that they contain addresses
2627 instead of offsets. */
2633 }
2637 {
2646 try
2647 {
2649 }
2651 {
2654 }
2657 }
2659 static enum unwind_stop_reason
2662 {
2669 /* This marks the outermost frame. */
2674 }
2676 static void
2679 {
2686 {
2687 /* This marks the outermost frame. */
2689 }
2690 else
2692 }
2697 {
2712 }
2715 {
2717 NORMAL_FRAME,
2718 amd64_frame_unwind_stop_reason,
2719 amd64_frame_this_id,
2720 amd64_frame_prev_register,
2721 NULL,
2722 default_frame_sniffer
2723 };
2724 \f
2725 /* Generate a bytecode expression to get the value of the saved PC. */
2727 static void
2730 CORE_ADDR scope)
2731 {
2732 /* The following sequence assumes the traditional use of the base
2733 register. */
2739 }
2740 \f
2742 /* Signal trampolines. */
2744 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2745 64-bit variants. This would require using identical frame caches
2746 on both platforms. */
2750 {
2755 CORE_ADDR addr;
2764 try
2765 {
2777 }
2779 {
2782 }
2786 }
2788 static enum unwind_stop_reason
2791 {
2799 }
2801 static void
2804 {
2811 {
2812 /* This marks the outermost frame. */
2814 }
2815 else
2817 }
2822 {
2823 /* Make sure we've initialized the cache. */
2827 }
2829 static int
2833 {
2837 /* We shouldn't even bother if we don't have a sigcontext_addr
2838 handler. */
2843 {
2846 }
2849 {
2855 }
2858 }
2861 {
2863 SIGTRAMP_FRAME,
2864 amd64_sigtramp_frame_unwind_stop_reason,
2865 amd64_sigtramp_frame_this_id,
2866 amd64_sigtramp_frame_prev_register,
2867 NULL,
2868 amd64_sigtramp_frame_sniffer
2869 };
2870 \f
2872 static CORE_ADDR
2874 {
2879 }
2882 {
2884 amd64_frame_base_address,
2885 amd64_frame_base_address,
2886 amd64_frame_base_address
2887 };
2889 /* Normal frames, but in a function epilogue. */
2891 /* Implement the stack_frame_destroyed_p gdbarch method.
2893 The epilogue is defined here as the 'ret' instruction, which will
2894 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2895 the function's stack frame. */
2897 static int
2899 {
2900 gdb_byte insn;
2914 }
2916 static int
2920 {
2924 else
2926 }
2930 {
2942 try
2943 {
2944 /* Cache base will be %esp plus cache->sp_offset (-8). */
2949 /* Cache pc will be the frame func. */
2952 /* The saved %esp will be at cache->base plus 16. */
2955 /* The saved %eip will be at cache->base plus 8. */
2959 }
2961 {
2964 }
2967 }
2969 static enum unwind_stop_reason
2972 {
2980 }
2982 static void
2986 {
2988 this_cache);
2992 else
2994 }
2997 {
2999 NORMAL_FRAME,
3000 amd64_epilogue_frame_unwind_stop_reason,
3001 amd64_epilogue_frame_this_id,
3002 amd64_frame_prev_register,
3003 NULL,
3004 amd64_epilogue_frame_sniffer
3005 };
3007 static struct frame_id
3009 {
3010 CORE_ADDR fp;
3015 }
3017 /* 16 byte align the SP per frame requirements. */
3019 static CORE_ADDR
3021 {
3023 }
3024 \f
3026 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3027 in the floating-point register set REGSET to register cache
3028 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3030 static void
3033 {
3039 }
3041 /* Collect register REGNUM from the register cache REGCACHE and store
3042 it in the buffer specified by FPREGS and LEN as described by the
3043 floating-point register set REGSET. If REGNUM is -1, do this for
3044 all registers in REGSET. */
3046 static void
3050 {
3056 }
3059 {
3061 };
3062 \f
3064 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
3065 %rdi. We expect its value to be a pointer to the jmp_buf structure
3066 from which we extract the address that we will land at. This
3067 address is copied into PC. This routine returns non-zero on
3068 success. */
3070 static int
3072 {
3074 CORE_ADDR jb_addr;
3080 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3081 longjmp will land. */
3086 jb_addr= extract_typed_address
3094 }
3097 {
3104 };
3106 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
3108 static bool
3110 {
3112 AMD64_RAX_REGNUM,
3113 AMD64_RIP_REGNUM);
3114 }
3116 void
3119 {
3125 NULL };
3127 NULL };
3129 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3130 floating-point registers. */
3142 {
3156 }
3159 {
3163 }
3166 {
3170 }
3173 {
3175 }
3178 {
3182 }
3187 /* Avoid wiring in the MMX registers for now. */
3191 amd64_pseudo_register_read_value);
3193 amd64_pseudo_register_write);
3195 amd64_ax_pseudo_register_collect);
3199 /* AMD64 has an FPU and 16 SSE registers. */
3203 /* This is what all the fuss is about. */
3208 /* In contrast to the i386, on AMD64 a `long double' actually takes
3209 up 128 bits, even though it's still based on the i387 extended
3210 floating-point format which has only 80 significant bits. */
3215 /* Register numbers of various important registers. */
3221 /* The "default" register numbering scheme for AMD64 is referred to
3222 as the "DWARF Register Number Mapping" in the System V psABI.
3223 The preferred debugging format for all known AMD64 targets is
3224 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3225 DWARF-1), but we provide the same mapping just in case. This
3226 mapping is also used for stabs, which GCC does support. */
3230 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3231 be in use on any of the supported AMD64 targets. */
3233 /* Call dummy code. */
3250 /* Hook the function epilogue frame unwinder. This unwinder is
3251 appended to the list first, so that it supercedes the other
3252 unwinders in function epilogues. */
3255 /* Hook the prologue-based frame unwinders. */
3266 /* SystemTap variables and functions. */
3270 stap_register_indirection_prefixes);
3272 stap_register_indirection_suffixes);
3274 i386_stap_is_single_operand);
3276 i386_stap_parse_special_token);
3282 amd64_in_indirect_branch_thunk);
3285 }
3287 /* Initialize ARCH for x86-64, no osabi. */
3289 static void
3291 {
3294 }
3298 {
3302 {
3308 }
3311 }
3313 void
3316 {
3326 }
3328 /* Initialize ARCH for x64-32, no osabi. */
3330 static void
3332 {
3335 }
3337 /* Return the target description for a specified XSAVE feature mask. */
3341 {
3354 segments);
3357 }
3360 void
3362 {
3364 amd64_none_init_abi);
3366 amd64_x32_none_init_abi);
3367 }
3368 \f
3370 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3371 sense that the instruction pointer and data pointer are simply
3372 64-bit offsets into the code segment and the data segment instead
3373 of a selector offset pair. The functions below store the upper 32
3374 bits of these pointers (instead of just the 16-bits of the segment
3375 selector). */
3377 /* Fill register REGNUM in REGCACHE with the appropriate
3378 floating-point or SSE register value from *FXSAVE. If REGNUM is
3379 -1, do this for all registers. This function masks off any of the
3380 reserved bits in *FXSAVE. */
3382 void
3385 {
3393 {
3400 }
3401 }
3403 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3405 void
3408 {
3416 {
3418 ULONGEST clear_bv;
3422 /* If the FISEG and FOSEG registers have not been initialised yet
3423 (their CLEAR_BV bit is set) then their default values of zero will
3424 have already been setup by I387_SUPPLY_XSAVE. */
3426 {
3431 }
3432 }
3433 }
3435 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3436 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3437 all registers. This function doesn't touch any of the reserved
3438 bits in *FXSAVE. */
3440 void
3443 {
3451 {
3456 }
3457 }
3459 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3461 void
3464 {
3472 {
3479 }
3480 }