opcodes/arc-dis.c

   1 /* Instruction printing code for the ARC.
   2    Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005, 2007, 2009,
   3    2010, 2012 Free Software Foundation, Inc.
   4    Contributed by Doug Evans (dje@cygnus.com).
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include "libiberty.h"
  25 #include "dis-asm.h"
  26 #include "opcode/arc.h"
  27 #include "elf-bfd.h"
  28 #include "elf/arc.h"
  29 #include "opintl.h"
  30
  31 #include <stdarg.h>
  32 #include "arc-dis.h"
  33 #include "arc-ext.h"
  34
  35 #ifndef dbg
  36 #define dbg (0)
  37 #endif
  38
  39 /* Classification of the opcodes for the decoder to print
  40    the instructions.  */
  41
  42 typedef enum
  43 {
  44   CLASS_A4_ARITH,
  45   CLASS_A4_OP3_GENERAL,
  46   CLASS_A4_FLAG,
  47   /* All branches other than JC.  */
  48   CLASS_A4_BRANCH,
  49   CLASS_A4_JC ,
  50   /* All loads other than immediate
  51      indexed loads.  */
  52   CLASS_A4_LD0,
  53   CLASS_A4_LD1,
  54   CLASS_A4_ST,
  55   CLASS_A4_SR,
  56   /* All single operand instructions.  */
  57   CLASS_A4_OP3_SUBOPC3F,
  58   CLASS_A4_LR
  59 } a4_decoding_class;
  60
  61 #define BIT(word,n)     ((word) & (1 << n))
  62 #define BITS(word,s,e)  (((word) >> s) & ((1 << (e + 1 - s)) - 1))
  63 #define OPCODE(word)    (BITS ((word), 27, 31))
  64 #define FIELDA(word)    (BITS ((word), 21, 26))
  65 #define FIELDB(word)    (BITS ((word), 15, 20))
  66 #define FIELDC(word)    (BITS ((word),  9, 14))
  67
  68 /* FIELD D is signed.  */
  69 #define FIELDD(word)    ((BITS ((word), 0, 8) ^ 0x100) - 0x100)
  70
  71 #define PUT_NEXT_WORD_IN(a)                                             \
  72   do                                                                    \
  73     {                                                                   \
  74       if (is_limm == 1 && !NEXT_WORD (1))                               \
  75         mwerror (state, _("Illegal limm reference in last instruction!\n")); \
  76       a = state->words[1];                                              \
  77     }                                                                   \
  78   while (0)
  79
  80 #define CHECK_FLAG_COND_NULLIFY()                               \
  81   do                                                            \
  82     {                                                           \
  83       if (is_shimm == 0)                                        \
  84         {                                                       \
  85           flag = BIT (state->words[0], 8);                      \
  86           state->nullifyMode = BITS (state->words[0], 5, 6);    \
  87           cond = BITS (state->words[0], 0, 4);                  \
  88         }                                                       \
  89     }                                                           \
  90   while (0)
  91
  92 #define CHECK_COND()                            \
  93   do                                            \
  94     {                                           \
  95       if (is_shimm == 0)                        \
  96         cond = BITS (state->words[0], 0, 4);    \
  97     }                                           \
  98   while (0)
  99
 100 #define CHECK_FIELD(field)                      \
 101   do                                            \
 102     {                                           \
 103       if (field == 62)                          \
 104         {                                       \
 105           is_limm++;                            \
 106           field##isReg = 0;                     \
 107           PUT_NEXT_WORD_IN (field);             \
 108           limm_value = field;                   \
 109         }                                       \
 110       else if (field > 60)                      \
 111         {                                       \
 112           field##isReg = 0;                     \
 113           is_shimm++;                           \
 114           flag = (field == 61);                 \
 115           field = FIELDD (state->words[0]);     \
 116         }                                       \
 117     }                                           \
 118   while (0)
 119
 120 #define CHECK_FIELD_A()                         \
 121   do                                            \
 122     {                                           \
 123       fieldA = FIELDA (state->words[0]);        \
 124       if (fieldA > 60)                          \
 125         {                                       \
 126           fieldAisReg = 0;                      \
 127           fieldA = 0;                           \
 128         }                                       \
 129     }                                           \
 130   while (0)
 131
 132 #define CHECK_FIELD_B()                         \
 133   do                                            \
 134     {                                           \
 135       fieldB = FIELDB (state->words[0]);        \
 136       CHECK_FIELD (fieldB);                     \
 137     }                                           \
 138   while (0)
 139
 140 #define CHECK_FIELD_C()                         \
 141   do                                            \
 142     {                                           \
 143       fieldC = FIELDC (state->words[0]);        \
 144       CHECK_FIELD (fieldC);                     \
 145     }                                           \
 146   while (0)
 147
 148 #define IS_SMALL(x)                 (((field##x) < 256) && ((field##x) > -257))
 149 #define IS_REG(x)                    (field##x##isReg)
 150 #define WRITE_FORMAT_LB_Rx_RB(x)     WRITE_FORMAT (x, "[","]","","")
 151 #define WRITE_FORMAT_x_COMMA_LB(x)   WRITE_FORMAT (x, "",",[","",",[")
 152 #define WRITE_FORMAT_COMMA_x_RB(x)   WRITE_FORMAT (x, ",","]",",","]")
 153 #define WRITE_FORMAT_x_RB(x)         WRITE_FORMAT (x, "","]","","]")
 154 #define WRITE_FORMAT_COMMA_x(x)      WRITE_FORMAT (x, ",","",",","")
 155 #define WRITE_FORMAT_x_COMMA(x)      WRITE_FORMAT (x, "",",","",",")
 156 #define WRITE_FORMAT_x(x)            WRITE_FORMAT (x, "","","","")
 157 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString,             \
 158                                      (IS_REG (x) ? cb1"%r"ca1 :         \
 159                                       usesAuxReg ? cb"%a"ca :           \
 160                                       IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
 161 #define WRITE_FORMAT_RB()       strcat (formatString, "]")
 162 #define WRITE_COMMENT(str)      (state->comm[state->commNum++] = (str))
 163 #define WRITE_NOP_COMMENT()     if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
 164
 165 #define NEXT_WORD(x)    (offset += 4, state->words[x])
 166
 167 #define add_target(x)   (state->targets[state->tcnt++] = (x))
 168
 169 static char comment_prefix[] = "\t; ";
 170
 171 static const char *
 172 core_reg_name (struct arcDisState * state, int val)
 173 {
 174   if (state->coreRegName)
 175     return (*state->coreRegName)(state->_this, val);
 176   return 0;
 177 }
 178
 179 static const char *
 180 aux_reg_name (struct arcDisState * state, int val)
 181 {
 182   if (state->auxRegName)
 183     return (*state->auxRegName)(state->_this, val);
 184   return 0;
 185 }
 186
 187 static const char *
 188 cond_code_name (struct arcDisState * state, int val)
 189 {
 190   if (state->condCodeName)
 191     return (*state->condCodeName)(state->_this, val);
 192   return 0;
 193 }
 194
 195 static const char *
 196 instruction_name (struct arcDisState * state,
 197                   int    op1,
 198                   int    op2,
 199                   int *  flags)
 200 {
 201   if (state->instName)
 202     return (*state->instName)(state->_this, op1, op2, flags);
 203   return 0;
 204 }
 205
 206 static void
 207 mwerror (struct arcDisState * state, const char * msg)
 208 {
 209   if (state->err != 0)
 210     (*state->err)(state->_this, (msg));
 211 }
 212
 213 static const char *
 214 post_address (struct arcDisState * state, int addr)
 215 {
 216   static char id[3 * ARRAY_SIZE (state->addresses)];
 217   int j, i = state->acnt;
 218
 219   if (i < ((int) ARRAY_SIZE (state->addresses)))
 220     {
 221       state->addresses[i] = addr;
 222       ++state->acnt;
 223       j = i*3;
 224       id[j+0] = '@';
 225       id[j+1] = '0'+i;
 226       id[j+2] = 0;
 227
 228       return id + j;
 229     }
 230   return "";
 231 }
 232
 233 static void
 234 arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
 235 {
 236   char *bp;
 237   const char *p;
 238   int size, leading_zero, regMap[2];
 239   va_list ap;
 240
 241   va_start (ap, format);
 242
 243   bp = buf;
 244   *bp = 0;
 245   p = format;
 246   regMap[0] = 0;
 247   regMap[1] = 0;
 248
 249   while (1)
 250     switch (*p++)
 251       {
 252       case 0:
 253         goto DOCOMM; /* (return)  */
 254       default:
 255         *bp++ = p[-1];
 256         break;
 257       case '%':
 258         size = 0;
 259         leading_zero = 0;
 260       RETRY: ;
 261         switch (*p++)
 262           {
 263           case '0':
 264           case '1':
 265           case '2':
 266           case '3':
 267           case '4':
 268           case '5':
 269           case '6':
 270           case '7':
 271           case '8':
 272           case '9':
 273             {
 274               /* size.  */
 275               size = p[-1] - '0';
 276               if (size == 0)
 277                 leading_zero = 1; /* e.g. %08x  */
 278               while (*p >= '0' && *p <= '9')
 279                 {
 280                   size = size * 10 + *p - '0';
 281                   p++;
 282                 }
 283               goto RETRY;
 284             }
 285 #define inc_bp() bp = bp + strlen (bp)
 286
 287           case 'h':
 288             {
 289               unsigned u = va_arg (ap, int);
 290
 291               /* Hex.  We can change the format to 0x%08x in
 292                  one place, here, if we wish.
 293                  We add underscores for easy reading.  */
 294               if (u > 65536)
 295                 sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
 296               else
 297                 sprintf (bp, "0x%x", u);
 298               inc_bp ();
 299             }
 300             break;
 301           case 'X': case 'x':
 302             {
 303               int val = va_arg (ap, int);
 304
 305               if (size != 0)
 306                 if (leading_zero)
 307                   sprintf (bp, "%0*x", size, val);
 308                 else
 309                   sprintf (bp, "%*x", size, val);
 310               else
 311                 sprintf (bp, "%x", val);
 312               inc_bp ();
 313             }
 314             break;
 315           case 'd':
 316             {
 317               int val = va_arg (ap, int);
 318
 319               if (size != 0)
 320                 sprintf (bp, "%*d", size, val);
 321               else
 322                 sprintf (bp, "%d", val);
 323               inc_bp ();
 324             }
 325             break;
 326           case 'r':
 327             {
 328               /* Register.  */
 329               int val = va_arg (ap, int);
 330
 331 #define REG2NAME(num, name) case num: sprintf (bp, ""name); \
 332   regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
 333
 334               switch (val)
 335                 {
 336                   REG2NAME (26, "gp");
 337                   REG2NAME (27, "fp");
 338                   REG2NAME (28, "sp");
 339                   REG2NAME (29, "ilink1");
 340                   REG2NAME (30, "ilink2");
 341                   REG2NAME (31, "blink");
 342                   REG2NAME (60, "lp_count");
 343                 default:
 344                   {
 345                     const char * ext;
 346
 347                     ext = core_reg_name (state, val);
 348                     if (ext)
 349                       sprintf (bp, "%s", ext);
 350                     else
 351                       sprintf (bp,"r%d",val);
 352                   }
 353                   break;
 354                 }
 355               inc_bp ();
 356             } break;
 357
 358           case 'a':
 359             {
 360               /* Aux Register.  */
 361               int val = va_arg (ap, int);
 362
 363 #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
 364
 365               switch (val)
 366                 {
 367                   AUXREG2NAME (0x0, "status");
 368                   AUXREG2NAME (0x1, "semaphore");
 369                   AUXREG2NAME (0x2, "lp_start");
 370                   AUXREG2NAME (0x3, "lp_end");
 371                   AUXREG2NAME (0x4, "identity");
 372                   AUXREG2NAME (0x5, "debug");
 373                 default:
 374                   {
 375                     const char *ext;
 376
 377                     ext = aux_reg_name (state, val);
 378                     if (ext)
 379                       sprintf (bp, "%s", ext);
 380                     else
 381                       arc_sprintf (state, bp, "%h", val);
 382                   }
 383                   break;
 384                 }
 385               inc_bp ();
 386             }
 387             break;
 388
 389           case 's':
 390             {
 391               sprintf (bp, "%s", va_arg (ap, char *));
 392               inc_bp ();
 393             }
 394             break;
 395
 396           default:
 397             fprintf (stderr, "?? format %c\n", p[-1]);
 398             break;
 399           }
 400       }
 401
 402  DOCOMM: *bp = 0;
 403   va_end (ap);
 404 }
 405
 406 static void
 407 write_comments_(struct arcDisState * state,
 408                 int shimm,
 409                 int is_limm,
 410                 long limm_value)
 411 {
 412   if (state->commentBuffer != 0)
 413     {
 414       int i;
 415
 416       if (is_limm)
 417         {
 418           const char *name = post_address (state, limm_value + shimm);
 419
 420           if (*name != 0)
 421             WRITE_COMMENT (name);
 422         }
 423       for (i = 0; i < state->commNum; i++)
 424         {
 425           if (i == 0)
 426             strcpy (state->commentBuffer, comment_prefix);
 427           else
 428             strcat (state->commentBuffer, ", ");
 429           strncat (state->commentBuffer, state->comm[i],
 430                    sizeof (state->commentBuffer));
 431         }
 432     }
 433 }
 434
 435 #define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
 436 #define write_comments()   write_comments2 (0)
 437
 438 static const char *condName[] =
 439 {
 440   /* 0..15.  */
 441   ""   , "z"  , "nz" , "p"  , "n"  , "c"  , "nc" , "v"  ,
 442   "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
 443 };
 444
 445 static void
 446 write_instr_name_(struct arcDisState * state,
 447                   const char * instrName,
 448                   int cond,
 449                   int condCodeIsPartOfName,
 450                   int flag,
 451                   int signExtend,
 452                   int addrWriteBack,
 453                   int directMem)
 454 {
 455   strcpy (state->instrBuffer, instrName);
 456
 457   if (cond > 0)
 458     {
 459       const char *cc = 0;
 460
 461       if (!condCodeIsPartOfName)
 462         strcat (state->instrBuffer, ".");
 463
 464       if (cond < 16)
 465         cc = condName[cond];
 466       else
 467         cc = cond_code_name (state, cond);
 468
 469       if (!cc)
 470         cc = "???";
 471
 472       strcat (state->instrBuffer, cc);
 473     }
 474
 475   if (flag)
 476     strcat (state->instrBuffer, ".f");
 477
 478   switch (state->nullifyMode)
 479     {
 480     case BR_exec_always:
 481       strcat (state->instrBuffer, ".d");
 482       break;
 483     case BR_exec_when_jump:
 484       strcat (state->instrBuffer, ".jd");
 485       break;
 486     }
 487
 488   if (signExtend)
 489     strcat (state->instrBuffer, ".x");
 490
 491   if (addrWriteBack)
 492     strcat (state->instrBuffer, ".a");
 493
 494   if (directMem)
 495     strcat (state->instrBuffer, ".di");
 496 }
 497
 498 #define write_instr_name()                                              \
 499   do                                                                    \
 500     {                                                                   \
 501       write_instr_name_(state, instrName,cond, condCodeIsPartOfName,    \
 502                         flag, signExtend, addrWriteBack, directMem);    \
 503       formatString[0] = '\0';                                           \
 504     }                                                                   \
 505   while (0)
 506
 507 enum
 508 {
 509   op_LD0 = 0, op_LD1 = 1, op_ST  = 2, op_3   = 3,
 510   op_BC  = 4, op_BLC = 5, op_LPC = 6, op_JC  = 7,
 511   op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
 512   op_AND = 12, op_OR  = 13, op_BIC = 14, op_XOR = 15
 513 };
 514
 515 extern disassemble_info tm_print_insn_info;
 516
 517 static int
 518 dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
 519 {
 520   int condCodeIsPartOfName = 0;
 521   a4_decoding_class decodingClass;
 522   const char * instrName;
 523   int repeatsOp = 0;
 524   int fieldAisReg = 1;
 525   int fieldBisReg = 1;
 526   int fieldCisReg = 1;
 527   int fieldA;
 528   int fieldB;
 529   int fieldC = 0;
 530   int flag = 0;
 531   int cond = 0;
 532   int is_shimm = 0;
 533   int is_limm = 0;
 534   long limm_value = 0;
 535   int signExtend = 0;
 536   int addrWriteBack = 0;
 537   int directMem = 0;
 538   int is_linked = 0;
 539   int offset = 0;
 540   int usesAuxReg = 0;
 541   int flags;
 542   int ignoreFirstOpd;
 543   char formatString[60];
 544
 545   state->instructionLen = 4;
 546   state->nullifyMode = BR_exec_when_no_jump;
 547   state->opWidth = 12;
 548   state->isBranch = 0;
 549
 550   state->_mem_load = 0;
 551   state->_ea_present = 0;
 552   state->_load_len = 0;
 553   state->ea_reg1 = no_reg;
 554   state->ea_reg2 = no_reg;
 555   state->_offset = 0;
 556
 557   if (! NEXT_WORD (0))
 558     return 0;
 559
 560   state->_opcode = OPCODE (state->words[0]);
 561   instrName = 0;
 562   decodingClass = CLASS_A4_ARITH; /* default!  */
 563   repeatsOp = 0;
 564   condCodeIsPartOfName=0;
 565   state->commNum = 0;
 566   state->tcnt = 0;
 567   state->acnt = 0;
 568   state->flow = noflow;
 569   ignoreFirstOpd = 0;
 570
 571   if (state->commentBuffer)
 572     state->commentBuffer[0] = '\0';
 573
 574   switch (state->_opcode)
 575     {
 576     case op_LD0:
 577       switch (BITS (state->words[0],1,2))
 578         {
 579         case 0:
 580           instrName = "ld";
 581           state->_load_len = 4;
 582           break;
 583         case 1:
 584           instrName = "ldb";
 585           state->_load_len = 1;
 586           break;
 587         case 2:
 588           instrName = "ldw";
 589           state->_load_len = 2;
 590           break;
 591         default:
 592           instrName = "??? (0[3])";
 593           state->flow = invalid_instr;
 594           break;
 595         }
 596       decodingClass = CLASS_A4_LD0;
 597       break;
 598
 599     case op_LD1:
 600       if (BIT (state->words[0],13))
 601         {
 602           instrName = "lr";
 603           decodingClass = CLASS_A4_LR;
 604         }
 605       else
 606         {
 607           switch (BITS (state->words[0], 10, 11))
 608             {
 609             case 0:
 610               instrName = "ld";
 611               state->_load_len = 4;
 612               break;
 613             case 1:
 614               instrName = "ldb";
 615               state->_load_len = 1;
 616               break;
 617             case 2:
 618               instrName = "ldw";
 619               state->_load_len = 2;
 620               break;
 621             default:
 622               instrName = "??? (1[3])";
 623               state->flow = invalid_instr;
 624               break;
 625             }
 626           decodingClass = CLASS_A4_LD1;
 627         }
 628       break;
 629
 630     case op_ST:
 631       if (BIT (state->words[0], 25))
 632         {
 633           instrName = "sr";
 634           decodingClass = CLASS_A4_SR;
 635         }
 636       else
 637         {
 638           switch (BITS (state->words[0], 22, 23))
 639             {
 640             case 0:
 641               instrName = "st";
 642               break;
 643             case 1:
 644               instrName = "stb";
 645               break;
 646             case 2:
 647               instrName = "stw";
 648               break;
 649             default:
 650               instrName = "??? (2[3])";
 651               state->flow = invalid_instr;
 652               break;
 653             }
 654           decodingClass = CLASS_A4_ST;
 655         }
 656       break;
 657
 658     case op_3:
 659       decodingClass = CLASS_A4_OP3_GENERAL;  /* default for opcode 3...  */
 660       switch (FIELDC (state->words[0]))
 661         {
 662         case  0:
 663           instrName = "flag";
 664           decodingClass = CLASS_A4_FLAG;
 665           break;
 666         case  1:
 667           instrName = "asr";
 668           break;
 669         case  2:
 670           instrName = "lsr";
 671           break;
 672         case  3:
 673           instrName = "ror";
 674           break;
 675         case  4:
 676           instrName = "rrc";
 677           break;
 678         case  5:
 679           instrName = "sexb";
 680           break;
 681         case  6:
 682           instrName = "sexw";
 683           break;
 684         case  7:
 685           instrName = "extb";
 686           break;
 687         case  8:
 688           instrName = "extw";
 689           break;
 690         case  0x3f:
 691           {
 692             decodingClass = CLASS_A4_OP3_SUBOPC3F;
 693             switch (FIELDD (state->words[0]))
 694               {
 695               case 0:
 696                 instrName = "brk";
 697                 break;
 698               case 1:
 699                 instrName = "sleep";
 700                 break;
 701               case 2:
 702                 instrName = "swi";
 703                 break;
 704               default:
 705                 instrName = "???";
 706                 state->flow=invalid_instr;
 707                 break;
 708               }
 709           }
 710           break;
 711
 712           /* ARC Extension Library Instructions
 713              NOTE: We assume that extension codes are these instrs.  */
 714         default:
 715           instrName = instruction_name (state,
 716                                         state->_opcode,
 717                                         FIELDC (state->words[0]),
 718                                         &flags);
 719           if (!instrName)
 720             {
 721               instrName = "???";
 722               state->flow = invalid_instr;
 723             }
 724           if (flags & IGNORE_FIRST_OPD)
 725             ignoreFirstOpd = 1;
 726           break;
 727         }
 728       break;
 729
 730     case op_BC:
 731       instrName = "b";
 732     case op_BLC:
 733       if (!instrName)
 734         instrName = "bl";
 735     case op_LPC:
 736       if (!instrName)
 737         instrName = "lp";
 738     case op_JC:
 739       if (!instrName)
 740         {
 741           if (BITS (state->words[0],9,9))
 742             {
 743               instrName = "jl";
 744               is_linked = 1;
 745             }
 746           else
 747             {
 748               instrName = "j";
 749               is_linked = 0;
 750             }
 751         }
 752       condCodeIsPartOfName = 1;
 753       decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH );
 754       state->isBranch = 1;
 755       break;
 756
 757     case op_ADD:
 758     case op_ADC:
 759     case op_AND:
 760       repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
 761
 762       switch (state->_opcode)
 763         {
 764         case op_ADD:
 765           instrName = (repeatsOp ? "asl" : "add");
 766           break;
 767         case op_ADC:
 768           instrName = (repeatsOp ? "rlc" : "adc");
 769           break;
 770         case op_AND:
 771           instrName = (repeatsOp ? "mov" : "and");
 772           break;
 773         }
 774       break;
 775
 776     case op_SUB: instrName = "sub";
 777       break;
 778     case op_SBC: instrName = "sbc";
 779       break;
 780     case op_OR:  instrName = "or";
 781       break;
 782     case op_BIC: instrName = "bic";
 783       break;
 784
 785     case op_XOR:
 786       if (state->words[0] == 0x7fffffff)
 787         {
 788           /* NOP encoded as xor -1, -1, -1.   */
 789           instrName = "nop";
 790           decodingClass = CLASS_A4_OP3_SUBOPC3F;
 791         }
 792       else
 793         instrName = "xor";
 794       break;
 795
 796     default:
 797       instrName = instruction_name (state,state->_opcode,0,&flags);
 798       /* if (instrName) printf("FLAGS=0x%x\n", flags);  */
 799       if (!instrName)
 800         {
 801           instrName = "???";
 802           state->flow=invalid_instr;
 803         }
 804       if (flags & IGNORE_FIRST_OPD)
 805         ignoreFirstOpd = 1;
 806       break;
 807     }
 808
 809   fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now.  */
 810   flag = cond = is_shimm = is_limm = 0;
 811   state->nullifyMode = BR_exec_when_no_jump;    /* 0  */
 812   signExtend = addrWriteBack = directMem = 0;
 813   usesAuxReg = 0;
 814
 815   switch (decodingClass)
 816     {
 817     case CLASS_A4_ARITH:
 818       CHECK_FIELD_A ();
 819       CHECK_FIELD_B ();
 820       if (!repeatsOp)
 821         CHECK_FIELD_C ();
 822       CHECK_FLAG_COND_NULLIFY ();
 823
 824       write_instr_name ();
 825       if (!ignoreFirstOpd)
 826         {
 827           WRITE_FORMAT_x (A);
 828           WRITE_FORMAT_COMMA_x (B);
 829           if (!repeatsOp)
 830             WRITE_FORMAT_COMMA_x (C);
 831           WRITE_NOP_COMMENT ();
 832           arc_sprintf (state, state->operandBuffer, formatString,
 833                       fieldA, fieldB, fieldC);
 834         }
 835       else
 836         {
 837           WRITE_FORMAT_x (B);
 838           if (!repeatsOp)
 839             WRITE_FORMAT_COMMA_x (C);
 840           arc_sprintf (state, state->operandBuffer, formatString,
 841                       fieldB, fieldC);
 842         }
 843       write_comments ();
 844       break;
 845
 846     case CLASS_A4_OP3_GENERAL:
 847       CHECK_FIELD_A ();
 848       CHECK_FIELD_B ();
 849       CHECK_FLAG_COND_NULLIFY ();
 850
 851       write_instr_name ();
 852       if (!ignoreFirstOpd)
 853         {
 854           WRITE_FORMAT_x (A);
 855           WRITE_FORMAT_COMMA_x (B);
 856           WRITE_NOP_COMMENT ();
 857           arc_sprintf (state, state->operandBuffer, formatString,
 858                       fieldA, fieldB);
 859         }
 860       else
 861         {
 862           WRITE_FORMAT_x (B);
 863           arc_sprintf (state, state->operandBuffer, formatString, fieldB);
 864         }
 865       write_comments ();
 866       break;
 867
 868     case CLASS_A4_FLAG:
 869       CHECK_FIELD_B ();
 870       CHECK_FLAG_COND_NULLIFY ();
 871       flag = 0; /* This is the FLAG instruction -- it's redundant.  */
 872
 873       write_instr_name ();
 874       WRITE_FORMAT_x (B);
 875       arc_sprintf (state, state->operandBuffer, formatString, fieldB);
 876       write_comments ();
 877       break;
 878
 879     case CLASS_A4_BRANCH:
 880       fieldA = BITS (state->words[0],7,26) << 2;
 881       fieldA = (fieldA << 10) >> 10; /* Make it signed.  */
 882       fieldA += addr + 4;
 883       CHECK_FLAG_COND_NULLIFY ();
 884       flag = 0;
 885
 886       write_instr_name ();
 887       /* This address could be a label we know. Convert it.  */
 888       if (state->_opcode != op_LPC /* LP  */)
 889         {
 890           add_target (fieldA); /* For debugger.  */
 891           state->flow = state->_opcode == op_BLC /* BL  */
 892             ? direct_call
 893             : direct_jump;
 894           /* indirect calls are achieved by "lr blink,[status];
 895              lr dest<- func addr; j [dest]"  */
 896         }
 897
 898       strcat (formatString, "%s"); /* Address/label name.  */
 899       arc_sprintf (state, state->operandBuffer, formatString,
 900                   post_address (state, fieldA));
 901       write_comments ();
 902       break;
 903
 904     case CLASS_A4_JC:
 905       /* For op_JC -- jump to address specified.
 906          Also covers jump and link--bit 9 of the instr. word
 907          selects whether linked, thus "is_linked" is set above.  */
 908       fieldA = 0;
 909       CHECK_FIELD_B ();
 910       CHECK_FLAG_COND_NULLIFY ();
 911
 912       if (!fieldBisReg)
 913         {
 914           fieldAisReg = 0;
 915           fieldA = (fieldB >> 25) & 0x7F; /* Flags.  */
 916           fieldB = (fieldB & 0xFFFFFF) << 2;
 917           state->flow = is_linked ? direct_call : direct_jump;
 918           add_target (fieldB);
 919           /* Screwy JLcc requires .jd mode to execute correctly
 920              but we pretend it is .nd (no delay slot).  */
 921           if (is_linked && state->nullifyMode == BR_exec_when_jump)
 922             state->nullifyMode = BR_exec_when_no_jump;
 923         }
 924       else
 925         {
 926           state->flow = is_linked ? indirect_call : indirect_jump;
 927           /* We should also treat this as indirect call if NOT linked
 928              but the preceding instruction was a "lr blink,[status]"
 929              and we have a delay slot with "add blink,blink,2".
 930              For now we can't detect such.  */
 931           state->register_for_indirect_jump = fieldB;
 932         }
 933
 934       write_instr_name ();
 935       strcat (formatString,
 936               IS_REG (B) ? "[%r]" : "%s"); /* Address/label name.  */
 937       if (fieldA != 0)
 938         {
 939           fieldAisReg = 0;
 940           WRITE_FORMAT_COMMA_x (A);
 941         }
 942       if (IS_REG (B))
 943         arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
 944       else
 945         arc_sprintf (state, state->operandBuffer, formatString,
 946                     post_address (state, fieldB), fieldA);
 947       write_comments ();
 948       break;
 949
 950     case CLASS_A4_LD0:
 951       /* LD instruction.
 952          B and C can be regs, or one (both?) can be limm.  */
 953       CHECK_FIELD_A ();
 954       CHECK_FIELD_B ();
 955       CHECK_FIELD_C ();
 956       if (dbg)
 957         printf ("5:b reg %d %d c reg %d %d  \n",
 958                 fieldBisReg,fieldB,fieldCisReg,fieldC);
 959       state->_offset = 0;
 960       state->_ea_present = 1;
 961       if (fieldBisReg)
 962         state->ea_reg1 = fieldB;
 963       else
 964         state->_offset += fieldB;
 965       if (fieldCisReg)
 966         state->ea_reg2 = fieldC;
 967       else
 968         state->_offset += fieldC;
 969       state->_mem_load = 1;
 970
 971       directMem     = BIT (state->words[0], 5);
 972       addrWriteBack = BIT (state->words[0], 3);
 973       signExtend    = BIT (state->words[0], 0);
 974
 975       write_instr_name ();
 976       WRITE_FORMAT_x_COMMA_LB(A);
 977       if (fieldBisReg || fieldB != 0)
 978         WRITE_FORMAT_x_COMMA (B);
 979       else
 980         fieldB = fieldC;
 981
 982       WRITE_FORMAT_x_RB (C);
 983       arc_sprintf (state, state->operandBuffer, formatString,
 984                   fieldA, fieldB, fieldC);
 985       write_comments ();
 986       break;
 987
 988     case CLASS_A4_LD1:
 989       /* LD instruction.  */
 990       CHECK_FIELD_B ();
 991       CHECK_FIELD_A ();
 992       fieldC = FIELDD (state->words[0]);
 993
 994       if (dbg)
 995         printf ("6:b reg %d %d c 0x%x  \n",
 996                 fieldBisReg, fieldB, fieldC);
 997       state->_ea_present = 1;
 998       state->_offset = fieldC;
 999       state->_mem_load = 1;
1000       if (fieldBisReg)
1001         state->ea_reg1 = fieldB;
1002       /* Field B is either a shimm (same as fieldC) or limm (different!)
1003          Say ea is not present, so only one of us will do the name lookup.  */
1004       else
1005         state->_offset += fieldB, state->_ea_present = 0;
1006
1007       directMem     = BIT (state->words[0],14);
1008       addrWriteBack = BIT (state->words[0],12);
1009       signExtend    = BIT (state->words[0],9);
1010
1011       write_instr_name ();
1012       WRITE_FORMAT_x_COMMA_LB (A);
1013       if (!fieldBisReg)
1014         {
1015           fieldB = state->_offset;
1016           WRITE_FORMAT_x_RB (B);
1017         }
1018       else
1019         {
1020           WRITE_FORMAT_x (B);
1021           if (fieldC != 0 && !BIT (state->words[0],13))
1022             {
1023               fieldCisReg = 0;
1024               WRITE_FORMAT_COMMA_x_RB (C);
1025             }
1026           else
1027             WRITE_FORMAT_RB ();
1028         }
1029       arc_sprintf (state, state->operandBuffer, formatString,
1030                   fieldA, fieldB, fieldC);
1031       write_comments ();
1032       break;
1033
1034     case CLASS_A4_ST:
1035       /* ST instruction.  */
1036       CHECK_FIELD_B();
1037       CHECK_FIELD_C();
1038       fieldA = FIELDD(state->words[0]); /* shimm  */
1039
1040       /* [B,A offset]  */
1041       if (dbg) printf("7:b reg %d %x off %x\n",
1042                       fieldBisReg,fieldB,fieldA);
1043       state->_ea_present = 1;
1044       state->_offset = fieldA;
1045       if (fieldBisReg)
1046         state->ea_reg1 = fieldB;
1047       /* Field B is either a shimm (same as fieldA) or limm (different!)
1048          Say ea is not present, so only one of us will do the name lookup.
1049          (for is_limm we do the name translation here).  */
1050       else
1051         state->_offset += fieldB, state->_ea_present = 0;
1052
1053       directMem     = BIT (state->words[0], 26);
1054       addrWriteBack = BIT (state->words[0], 24);
1055
1056       write_instr_name ();
1057       WRITE_FORMAT_x_COMMA_LB(C);
1058
1059       if (!fieldBisReg)
1060         {
1061           fieldB = state->_offset;
1062           WRITE_FORMAT_x_RB (B);
1063         }
1064       else
1065         {
1066           WRITE_FORMAT_x (B);
1067           if (fieldBisReg && fieldA != 0)
1068             {
1069               fieldAisReg = 0;
1070               WRITE_FORMAT_COMMA_x_RB(A);
1071             }
1072           else
1073             WRITE_FORMAT_RB();
1074         }
1075       arc_sprintf (state, state->operandBuffer, formatString,
1076                   fieldC, fieldB, fieldA);
1077       write_comments2 (fieldA);
1078       break;
1079
1080     case CLASS_A4_SR:
1081       /* SR instruction  */
1082       CHECK_FIELD_B();
1083       CHECK_FIELD_C();
1084
1085       write_instr_name ();
1086       WRITE_FORMAT_x_COMMA_LB(C);
1087       /* Try to print B as an aux reg if it is not a core reg.  */
1088       usesAuxReg = 1;
1089       WRITE_FORMAT_x (B);
1090       WRITE_FORMAT_RB ();
1091       arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
1092       write_comments ();
1093       break;
1094
1095     case CLASS_A4_OP3_SUBOPC3F:
1096       write_instr_name ();
1097       state->operandBuffer[0] = '\0';
1098       break;
1099
1100     case CLASS_A4_LR:
1101       /* LR instruction */
1102       CHECK_FIELD_A ();
1103       CHECK_FIELD_B ();
1104
1105       write_instr_name ();
1106       WRITE_FORMAT_x_COMMA_LB (A);
1107       /* Try to print B as an aux reg if it is not a core reg. */
1108       usesAuxReg = 1;
1109       WRITE_FORMAT_x (B);
1110       WRITE_FORMAT_RB ();
1111       arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
1112       write_comments ();
1113       break;
1114
1115     default:
1116       mwerror (state, "Bad decoding class in ARC disassembler");
1117       break;
1118     }
1119
1120   state->_cond = cond;
1121   return state->instructionLen = offset;
1122 }
1123
1124
1125 /* Returns the name the user specified core extension register.  */
1126
1127 static const char *
1128 _coreRegName(void * arg ATTRIBUTE_UNUSED, int regval)
1129 {
1130   return arcExtMap_coreRegName (regval);
1131 }
1132
1133 /* Returns the name the user specified AUX extension register.  */
1134
1135 static const char *
1136 _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
1137 {
1138   return arcExtMap_auxRegName(regval);
1139 }
1140
1141 /* Returns the name the user specified condition code name.  */
1142
1143 static const char *
1144 _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
1145 {
1146   return arcExtMap_condCodeName(regval);
1147 }
1148
1149 /* Returns the name the user specified extension instruction.  */
1150
1151 static const char *
1152 _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
1153 {
1154   return arcExtMap_instName(majop, minop, flags);
1155 }
1156
1157 /* Decode an instruction returning the size of the instruction
1158    in bytes or zero if unrecognized.  */
1159
1160 static int
1161 decodeInstr (bfd_vma            address, /* Address of this instruction.  */
1162              disassemble_info * info)
1163 {
1164   int status;
1165   bfd_byte buffer[4];
1166   struct arcDisState s;         /* ARC Disassembler state.  */
1167   void *stream = info->stream;  /* Output stream.  */
1168   fprintf_ftype func = info->fprintf_func;
1169
1170   memset (&s, 0, sizeof(struct arcDisState));
1171
1172   /* read first instruction  */
1173   status = (*info->read_memory_func) (address, buffer, 4, info);
1174   if (status != 0)
1175     {
1176       (*info->memory_error_func) (status, address, info);
1177       return 0;
1178     }
1179   if (info->endian == BFD_ENDIAN_LITTLE)
1180     s.words[0] = bfd_getl32(buffer);
1181   else
1182     s.words[0] = bfd_getb32(buffer);
1183   /* Always read second word in case of limm.  */
1184
1185   /* We ignore the result since last insn may not have a limm.  */
1186   status = (*info->read_memory_func) (address + 4, buffer, 4, info);
1187   if (info->endian == BFD_ENDIAN_LITTLE)
1188     s.words[1] = bfd_getl32(buffer);
1189   else
1190     s.words[1] = bfd_getb32(buffer);
1191
1192   s._this = &s;
1193   s.coreRegName = _coreRegName;
1194   s.auxRegName = _auxRegName;
1195   s.condCodeName = _condCodeName;
1196   s.instName = _instName;
1197
1198   /* Disassemble.  */
1199   dsmOneArcInst (address, & s);
1200
1201   /* Display the disassembly instruction.  */
1202   (*func) (stream, "%08lx ", s.words[0]);
1203   (*func) (stream, "    ");
1204   (*func) (stream, "%-10s ", s.instrBuffer);
1205
1206   if (__TRANSLATION_REQUIRED (s))
1207     {
1208       bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
1209
1210       (*info->print_address_func) ((bfd_vma) addr, info);
1211       (*func) (stream, "\n");
1212     }
1213   else
1214     (*func) (stream, "%s",s.operandBuffer);
1215
1216   return s.instructionLen;
1217 }
1218
1219 /* Return the print_insn function to use.
1220    Side effect: load (possibly empty) extension section  */
1221
1222 disassembler_ftype
1223 arc_get_disassembler (void *ptr)
1224 {
1225   if (ptr)
1226     build_ARC_extmap ((struct bfd *) ptr);
1227   return decodeInstr;
1228 }