gdb/nat/aarch64-hw-point.h

   1 /* Copyright (C) 2009-2022 Free Software Foundation, Inc.
   2
   3    This file is part of GDB.
   4
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 3 of the License, or
   8    (at your option) any later version.
   9
  10    This program is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  17
  18 #ifndef NAT_AARCH64_HW_POINT_H
  19 #define NAT_AARCH64_HW_POINT_H
  20
  21 /* Macro definitions, data structures, and code for the hardware
  22    breakpoint and hardware watchpoint support follow.  We use the
  23    following abbreviations throughout the code:
  24
  25    hw - hardware
  26    bp - breakpoint
  27    wp - watchpoint  */
  28
  29 /* Maximum number of hardware breakpoint and watchpoint registers.
  30    Neither of these values may exceed the width of dr_changed_t
  31    measured in bits.  */
  32
  33 #define AARCH64_HBP_MAX_NUM 16
  34 #define AARCH64_HWP_MAX_NUM 16
  35
  36 /* Alignment requirement in bytes for addresses written to
  37    hardware breakpoint and watchpoint value registers.
  38
  39    A ptrace call attempting to set an address that does not meet the
  40    alignment criteria will fail.  Limited support has been provided in
  41    this port for unaligned watchpoints, such that from a GDB user
  42    perspective, an unaligned watchpoint may be requested.
  43
  44    This is achieved by minimally enlarging the watched area to meet the
  45    alignment requirement, and if necessary, splitting the watchpoint
  46    over several hardware watchpoint registers.  */
  47
  48 #define AARCH64_HBP_ALIGNMENT 4
  49 #define AARCH64_HWP_ALIGNMENT 8
  50
  51 /* The maximum length of a memory region that can be watched by one
  52    hardware watchpoint register.  */
  53
  54 #define AARCH64_HWP_MAX_LEN_PER_REG 8
  55
  56 /* Macro for the expected version of the ARMv8-A debug architecture.  */
  57 #define AARCH64_DEBUG_ARCH_V8 0x6
  58 #define AARCH64_DEBUG_ARCH_V8_1 0x7
  59 #define AARCH64_DEBUG_ARCH_V8_2 0x8
  60 #define AARCH64_DEBUG_ARCH_V8_4 0x9
  61
  62 /* ptrace expects control registers to be formatted as follows:
  63
  64    31                             13          5      3      1     0
  65    +--------------------------------+----------+------+------+----+
  66    |         RESERVED (SBZ)         |   MASK   | TYPE | PRIV | EN |
  67    +--------------------------------+----------+------+------+----+
  68
  69    The TYPE field is ignored for breakpoints.  */
  70
  71 #define DR_CONTROL_ENABLED(ctrl)        (((ctrl) & 0x1) == 1)
  72 #define DR_CONTROL_MASK(ctrl)           (((ctrl) >> 5) & 0xff)
  73
  74 /* Structure for managing the hardware breakpoint/watchpoint resources.
  75    DR_ADDR_* stores the address, DR_CTRL_* stores the control register
  76    content, and DR_REF_COUNT_* counts the numbers of references to the
  77    corresponding bp/wp, by which way the limited hardware resources
  78    are not wasted on duplicated bp/wp settings (though so far gdb has
  79    done a good job by not sending duplicated bp/wp requests).  */
  80
  81 struct aarch64_debug_reg_state
  82 {
  83   /* hardware breakpoint */
  84   CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
  85   unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
  86   unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
  87
  88   /* hardware watchpoint */
  89   /* Address aligned down to AARCH64_HWP_ALIGNMENT.  */
  90   CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
  91   /* Address as entered by user without any forced alignment.  */
  92   CORE_ADDR dr_addr_orig_wp[AARCH64_HWP_MAX_NUM];
  93   unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
  94   unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
  95 };
  96
  97 extern int aarch64_num_bp_regs;
  98 extern int aarch64_num_wp_regs;
  99
 100 /* Invoked when IDXth breakpoint/watchpoint register pair needs to be
 101    updated.  */
 102 void aarch64_notify_debug_reg_change (ptid_t ptid, int is_watchpoint,
 103                                       unsigned int idx);
 104
 105 unsigned int aarch64_watchpoint_offset (unsigned int ctrl);
 106 unsigned int aarch64_watchpoint_length (unsigned int ctrl);
 107
 108 int aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
 109                                int len, int is_insert, ptid_t ptid,
 110                                struct aarch64_debug_reg_state *state);
 111 int aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
 112                                int len, int is_insert, ptid_t ptid,
 113                                struct aarch64_debug_reg_state *state);
 114
 115 /* Return TRUE if there are any hardware breakpoints.  If WATCHPOINT is TRUE,
 116    check hardware watchpoints instead.  */
 117 bool aarch64_any_set_debug_regs_state (aarch64_debug_reg_state *state,
 118                                        bool watchpoint);
 119
 120 void aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
 121                                    const char *func, CORE_ADDR addr,
 122                                    int len, enum target_hw_bp_type type);
 123
 124 int aarch64_region_ok_for_watchpoint (CORE_ADDR addr, int len);
 125
 126 #endif /* NAT_AARCH64_HW_POINT_H */