gdb/riscv-tdep.h

   1 /* Target-dependent header for the RISC-V architecture, for GDB, the
   2    GNU Debugger.
   3
   4    Copyright (C) 2018-2022 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef RISCV_TDEP_H
  22 #define RISCV_TDEP_H
  23
  24 #include "arch/riscv.h"
  25 #include "gdbarch.h"
  26
  27 /* RiscV register numbers.  */
  28 enum
  29 {
  30   RISCV_ZERO_REGNUM = 0,        /* Read-only register, always 0.  */
  31   RISCV_RA_REGNUM = 1,          /* Return Address.  */
  32   RISCV_SP_REGNUM = 2,          /* Stack Pointer.  */
  33   RISCV_GP_REGNUM = 3,          /* Global Pointer.  */
  34   RISCV_TP_REGNUM = 4,          /* Thread Pointer.  */
  35   RISCV_FP_REGNUM = 8,          /* Frame Pointer.  */
  36   RISCV_A0_REGNUM = 10,         /* First argument.  */
  37   RISCV_A1_REGNUM = 11,         /* Second argument.  */
  38   RISCV_A7_REGNUM = 17,         /* Seventh argument.  */
  39   RISCV_PC_REGNUM = 32,         /* Program Counter.  */
  40
  41   RISCV_NUM_INTEGER_REGS = 32,
  42
  43   RISCV_FIRST_FP_REGNUM = 33,   /* First Floating Point Register */
  44   RISCV_FA0_REGNUM = 43,
  45   RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
  46   RISCV_LAST_FP_REGNUM = 64,    /* Last Floating Point Register */
  47
  48   RISCV_FIRST_CSR_REGNUM = 65,  /* First CSR */
  49 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
  50   RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
  51 #include "opcode/riscv-opc.h"
  52 #undef DECLARE_CSR
  53   RISCV_LAST_CSR_REGNUM = 4160,
  54   RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
  55
  56   RISCV_PRIV_REGNUM = 4161,
  57
  58   RISCV_V0_REGNUM,
  59
  60   RISCV_V31_REGNUM = RISCV_V0_REGNUM + 31,
  61
  62   RISCV_LAST_REGNUM = RISCV_V31_REGNUM
  63 };
  64
  65 /* RiscV DWARF register numbers.  */
  66 enum
  67 {
  68   RISCV_DWARF_REGNUM_X0 = 0,
  69   RISCV_DWARF_REGNUM_X31 = 31,
  70   RISCV_DWARF_REGNUM_F0 = 32,
  71   RISCV_DWARF_REGNUM_F31 = 63,
  72   RISCV_DWARF_REGNUM_V0 = 96,
  73   RISCV_DWARF_REGNUM_V31 = 127,
  74   RISCV_DWARF_FIRST_CSR = 4096,
  75   RISCV_DWARF_LAST_CSR = 8191,
  76 };
  77
  78 /* RISC-V specific per-architecture information.  */
  79 struct riscv_gdbarch_tdep : gdbarch_tdep_base
  80 {
  81   /* Features about the target hardware that impact how the gdbarch is
  82      configured.  Two gdbarch instances are compatible only if this field
  83      matches.  */
  84   struct riscv_gdbarch_features isa_features;
  85
  86   /* Features about the abi that impact how the gdbarch is configured.  Two
  87      gdbarch instances are compatible only if this field matches.  */
  88   struct riscv_gdbarch_features abi_features;
  89
  90   /* ISA-specific data types.  */
  91   struct type *riscv_fpreg_d_type = nullptr;
  92
  93   /* The location of these registers, set to -2 by default so we don't
  94      match against -1 which is frequently used to mean "all registers",
  95      e.g. in the regcache supply/collect code.  */
  96   int fflags_regnum = -2;
  97   int frm_regnum = -2;
  98
  99   /* Use for tracking unknown CSRs in the target description.
 100      UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown
 101      CSR.  All other unknown CSRs will be assigned sequential numbers after
 102      this, with UNKNOWN_CSRS_COUNT being the total number of unknown CSRs.  */
 103   int unknown_csrs_first_regnum = -1;
 104   int unknown_csrs_count = 0;
 105
 106   /* Some targets (QEMU) are reporting three registers twice in the target
 107      description they send.  These three register numbers, when not set to
 108      -1, are for the duplicate copies of these registers.  */
 109   int duplicate_fflags_regnum = -1;
 110   int duplicate_frm_regnum = -1;
 111   int duplicate_fcsr_regnum = -1;
 112
 113   /* Return the expected next PC assuming FRAME is stopped at a syscall
 114      instruction.  */
 115   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame) = nullptr;
 116 };
 117
 118
 119 /* Return the width in bytes  of the general purpose registers for GDBARCH.
 120    Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
 121    RV128.  */
 122 extern int riscv_isa_xlen (struct gdbarch *gdbarch);
 123
 124 /* Return the width in bytes of the hardware floating point registers for
 125    GDBARCH.  If this architecture has no floating point registers, then
 126    return 0.  Possible values are 4, 8, or 16 for depending on which of
 127    single, double or quad floating point support is available.  */
 128 extern int riscv_isa_flen (struct gdbarch *gdbarch);
 129
 130 /* Return the width in bytes of the general purpose register abi for
 131    GDBARCH.  This can be equal to, or less than RISCV_ISA_XLEN and reflects
 132    how the binary was compiled rather than the hardware that is available.
 133    It is possible that a binary compiled for RV32 is being run on an RV64
 134    target, in which case the isa xlen is 8-bytes, and the abi xlen is
 135    4-bytes.  This will impact how inferior functions are called.  */
 136 extern int riscv_abi_xlen (struct gdbarch *gdbarch);
 137
 138 /* Return the width in bytes of the floating point register abi for
 139    GDBARCH.  This reflects how the binary was compiled rather than the
 140    hardware that is available.  It is possible that a binary is compiled
 141    for single precision floating point, and then run on a target with
 142    double precision floating point.  A return value of 0 indicates that no
 143    floating point abi is in use (floating point arguments will be passed
 144    in integer registers) other possible return value are 4, 8, or 16 as
 145    with RISCV_ISA_FLEN.  */
 146 extern int riscv_abi_flen (struct gdbarch *gdbarch);
 147
 148 /* Return true if GDBARCH is using the embedded x-regs abi, that is the
 149    target only has 16 x-registers, which includes a reduced number of
 150    argument registers.  */
 151 extern bool riscv_abi_embedded (struct gdbarch *gdbarch);
 152
 153 /* Single step based on where the current instruction will take us.  */
 154 extern std::vector<CORE_ADDR> riscv_software_single_step
 155   (struct regcache *regcache);
 156
 157 /* Supply register REGNUM from the buffer REGS (length LEN) into
 158    REGCACHE.  REGSET describes the layout of the buffer.  If REGNUM is -1
 159    then all registers described by REGSET are supplied.
 160
 161    The register RISCV_ZERO_REGNUM should not be described by REGSET,
 162    however, this register (which always has the value 0) will be supplied
 163    by this function if requested.
 164
 165    The registers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM should
 166    not be described by REGSET, however, these register will be provided if
 167    requested assuming either:
 168    (a) REGCACHE already contains the value of RISCV_CSR_FCSR_REGNUM, or
 169    (b) REGSET describes the location of RISCV_CSR_FCSR_REGNUM in the REGS
 170        buffer.
 171
 172    This function can be used as the supply function for either x-regs or
 173    f-regs when loading corefiles, and doesn't care which abi is currently
 174    in use.  */
 175
 176 extern void riscv_supply_regset (const struct regset *regset,
 177                                   struct regcache *regcache, int regnum,
 178                                   const void *regs, size_t len);
 179
 180 /* The names of the RISC-V target description features.  */
 181 extern const char *riscv_feature_name_csr;
 182
 183 #endif /* RISCV_TDEP_H */