gdb/ia64-linux-nat.c

   1 /* Functions specific to running gdb native on IA-64 running
   2    GNU/Linux.
   3
   4    Copyright (C) 1999-2022 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "inferior.h"
  23 #include "target.h"
  24 #include "gdbarch.h"
  25 #include "gdbcore.h"
  26 #include "regcache.h"
  27 #include "ia64-tdep.h"
  28 #include "linux-nat.h"
  29
  30 #include <signal.h>
  31 #include "nat/gdb_ptrace.h"
  32 #include "gdbsupport/gdb_wait.h"
  33 #ifdef HAVE_SYS_REG_H
  34 #include <sys/reg.h>
  35 #endif
  36 #include <sys/syscall.h>
  37 #include <sys/user.h>
  38
  39 #include <asm/ptrace_offsets.h>
  40 #include <sys/procfs.h>
  41
  42 /* Prototypes for supply_gregset etc.  */
  43 #include "gregset.h"
  44
  45 #include "inf-ptrace.h"
  46
  47 class ia64_linux_nat_target final : public linux_nat_target
  48 {
  49 public:
  50   /* Add our register access methods.  */
  51   void fetch_registers (struct regcache *, int) override;
  52   void store_registers (struct regcache *, int) override;
  53
  54   enum target_xfer_status xfer_partial (enum target_object object,
  55                                         const char *annex,
  56                                         gdb_byte *readbuf,
  57                                         const gdb_byte *writebuf,
  58                                         ULONGEST offset, ULONGEST len,
  59                                         ULONGEST *xfered_len) override;
  60
  61   /* Override watchpoint routines.  */
  62
  63   /* The IA-64 architecture can step over a watch point (without
  64      triggering it again) if the "dd" (data debug fault disable) bit
  65      in the processor status word is set.
  66
  67      This PSR bit is set in
  68      ia64_linux_nat_target::stopped_by_watchpoint when the code there
  69      has determined that a hardware watchpoint has indeed been hit.
  70      The CPU will then be able to execute one instruction without
  71      triggering a watchpoint.  */
  72   bool have_steppable_watchpoint () override { return true; }
  73
  74   int can_use_hw_breakpoint (enum bptype, int, int) override;
  75   bool stopped_by_watchpoint () override;
  76   bool stopped_data_address (CORE_ADDR *) override;
  77   int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
  78                          struct expression *) override;
  79   int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
  80                          struct expression *) override;
  81   /* Override linux_nat_target low methods.  */
  82   void low_new_thread (struct lwp_info *lp) override;
  83   bool low_status_is_event (int status) override;
  84
  85   void enable_watchpoints_in_psr (ptid_t ptid);
  86 };
  87
  88 static ia64_linux_nat_target the_ia64_linux_nat_target;
  89
  90 /* These must match the order of the register names.
  91
  92    Some sort of lookup table is needed because the offsets associated
  93    with the registers are all over the board.  */
  94
  95 static int u_offsets[] =
  96   {
  97     /* general registers */
  98     -1,         /* gr0 not available; i.e, it's always zero.  */
  99     PT_R1,
 100     PT_R2,
 101     PT_R3,
 102     PT_R4,
 103     PT_R5,
 104     PT_R6,
 105     PT_R7,
 106     PT_R8,
 107     PT_R9,
 108     PT_R10,
 109     PT_R11,
 110     PT_R12,
 111     PT_R13,
 112     PT_R14,
 113     PT_R15,
 114     PT_R16,
 115     PT_R17,
 116     PT_R18,
 117     PT_R19,
 118     PT_R20,
 119     PT_R21,
 120     PT_R22,
 121     PT_R23,
 122     PT_R24,
 123     PT_R25,
 124     PT_R26,
 125     PT_R27,
 126     PT_R28,
 127     PT_R29,
 128     PT_R30,
 129     PT_R31,
 130     /* gr32 through gr127 not directly available via the ptrace interface.  */
 131     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 132     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 133     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 134     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 135     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 136     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 137     /* Floating point registers */
 138     -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0).  */
 139     PT_F2,
 140     PT_F3,
 141     PT_F4,
 142     PT_F5,
 143     PT_F6,
 144     PT_F7,
 145     PT_F8,
 146     PT_F9,
 147     PT_F10,
 148     PT_F11,
 149     PT_F12,
 150     PT_F13,
 151     PT_F14,
 152     PT_F15,
 153     PT_F16,
 154     PT_F17,
 155     PT_F18,
 156     PT_F19,
 157     PT_F20,
 158     PT_F21,
 159     PT_F22,
 160     PT_F23,
 161     PT_F24,
 162     PT_F25,
 163     PT_F26,
 164     PT_F27,
 165     PT_F28,
 166     PT_F29,
 167     PT_F30,
 168     PT_F31,
 169     PT_F32,
 170     PT_F33,
 171     PT_F34,
 172     PT_F35,
 173     PT_F36,
 174     PT_F37,
 175     PT_F38,
 176     PT_F39,
 177     PT_F40,
 178     PT_F41,
 179     PT_F42,
 180     PT_F43,
 181     PT_F44,
 182     PT_F45,
 183     PT_F46,
 184     PT_F47,
 185     PT_F48,
 186     PT_F49,
 187     PT_F50,
 188     PT_F51,
 189     PT_F52,
 190     PT_F53,
 191     PT_F54,
 192     PT_F55,
 193     PT_F56,
 194     PT_F57,
 195     PT_F58,
 196     PT_F59,
 197     PT_F60,
 198     PT_F61,
 199     PT_F62,
 200     PT_F63,
 201     PT_F64,
 202     PT_F65,
 203     PT_F66,
 204     PT_F67,
 205     PT_F68,
 206     PT_F69,
 207     PT_F70,
 208     PT_F71,
 209     PT_F72,
 210     PT_F73,
 211     PT_F74,
 212     PT_F75,
 213     PT_F76,
 214     PT_F77,
 215     PT_F78,
 216     PT_F79,
 217     PT_F80,
 218     PT_F81,
 219     PT_F82,
 220     PT_F83,
 221     PT_F84,
 222     PT_F85,
 223     PT_F86,
 224     PT_F87,
 225     PT_F88,
 226     PT_F89,
 227     PT_F90,
 228     PT_F91,
 229     PT_F92,
 230     PT_F93,
 231     PT_F94,
 232     PT_F95,
 233     PT_F96,
 234     PT_F97,
 235     PT_F98,
 236     PT_F99,
 237     PT_F100,
 238     PT_F101,
 239     PT_F102,
 240     PT_F103,
 241     PT_F104,
 242     PT_F105,
 243     PT_F106,
 244     PT_F107,
 245     PT_F108,
 246     PT_F109,
 247     PT_F110,
 248     PT_F111,
 249     PT_F112,
 250     PT_F113,
 251     PT_F114,
 252     PT_F115,
 253     PT_F116,
 254     PT_F117,
 255     PT_F118,
 256     PT_F119,
 257     PT_F120,
 258     PT_F121,
 259     PT_F122,
 260     PT_F123,
 261     PT_F124,
 262     PT_F125,
 263     PT_F126,
 264     PT_F127,
 265     /* Predicate registers - we don't fetch these individually.  */
 266     -1, -1, -1, -1, -1, -1, -1, -1,
 267     -1, -1, -1, -1, -1, -1, -1, -1,
 268     -1, -1, -1, -1, -1, -1, -1, -1,
 269     -1, -1, -1, -1, -1, -1, -1, -1,
 270     -1, -1, -1, -1, -1, -1, -1, -1,
 271     -1, -1, -1, -1, -1, -1, -1, -1,
 272     -1, -1, -1, -1, -1, -1, -1, -1,
 273     -1, -1, -1, -1, -1, -1, -1, -1,
 274     /* branch registers */
 275     PT_B0,
 276     PT_B1,
 277     PT_B2,
 278     PT_B3,
 279     PT_B4,
 280     PT_B5,
 281     PT_B6,
 282     PT_B7,
 283     /* Virtual frame pointer and virtual return address pointer.  */
 284     -1, -1,
 285     /* other registers */
 286     PT_PR,
 287     PT_CR_IIP,  /* ip */
 288     PT_CR_IPSR, /* psr */
 289     PT_CFM,     /* cfm */
 290     /* kernel registers not visible via ptrace interface (?)  */
 291     -1, -1, -1, -1, -1, -1, -1, -1,
 292     /* hole */
 293     -1, -1, -1, -1, -1, -1, -1, -1,
 294     PT_AR_RSC,
 295     PT_AR_BSP,
 296     PT_AR_BSPSTORE,
 297     PT_AR_RNAT,
 298     -1,
 299     -1,         /* Not available: FCR, IA32 floating control register.  */
 300     -1, -1,
 301     -1,         /* Not available: EFLAG */
 302     -1,         /* Not available: CSD */
 303     -1,         /* Not available: SSD */
 304     -1,         /* Not available: CFLG */
 305     -1,         /* Not available: FSR */
 306     -1,         /* Not available: FIR */
 307     -1,         /* Not available: FDR */
 308     -1,
 309     PT_AR_CCV,
 310     -1, -1, -1,
 311     PT_AR_UNAT,
 312     -1, -1, -1,
 313     PT_AR_FPSR,
 314     -1, -1, -1,
 315     -1,         /* Not available: ITC */
 316     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 317     -1, -1, -1, -1, -1, -1, -1, -1, -1,
 318     PT_AR_PFS,
 319     PT_AR_LC,
 320     PT_AR_EC,
 321     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 322     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 323     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 324     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 325     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 326     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 327     -1,
 328     /* nat bits - not fetched directly; instead we obtain these bits from
 329        either rnat or unat or from memory.  */
 330     -1, -1, -1, -1, -1, -1, -1, -1,
 331     -1, -1, -1, -1, -1, -1, -1, -1,
 332     -1, -1, -1, -1, -1, -1, -1, -1,
 333     -1, -1, -1, -1, -1, -1, -1, -1,
 334     -1, -1, -1, -1, -1, -1, -1, -1,
 335     -1, -1, -1, -1, -1, -1, -1, -1,
 336     -1, -1, -1, -1, -1, -1, -1, -1,
 337     -1, -1, -1, -1, -1, -1, -1, -1,
 338     -1, -1, -1, -1, -1, -1, -1, -1,
 339     -1, -1, -1, -1, -1, -1, -1, -1,
 340     -1, -1, -1, -1, -1, -1, -1, -1,
 341     -1, -1, -1, -1, -1, -1, -1, -1,
 342     -1, -1, -1, -1, -1, -1, -1, -1,
 343     -1, -1, -1, -1, -1, -1, -1, -1,
 344     -1, -1, -1, -1, -1, -1, -1, -1,
 345     -1, -1, -1, -1, -1, -1, -1, -1,
 346   };
 347
 348 static CORE_ADDR
 349 ia64_register_addr (struct gdbarch *gdbarch, int regno)
 350 {
 351   CORE_ADDR addr;
 352
 353   if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
 354     error (_("Invalid register number %d."), regno);
 355
 356   if (u_offsets[regno] == -1)
 357     addr = 0;
 358   else
 359     addr = (CORE_ADDR) u_offsets[regno];
 360
 361   return addr;
 362 }
 363
 364 static int
 365 ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno)
 366 {
 367   return regno < 0
 368          || regno >= gdbarch_num_regs (gdbarch)
 369          || u_offsets[regno] == -1;
 370 }
 371
 372 static int
 373 ia64_cannot_store_register (struct gdbarch *gdbarch, int regno)
 374 {
 375   /* Rationale behind not permitting stores to bspstore...
 376
 377      The IA-64 architecture provides bspstore and bsp which refer
 378      memory locations in the RSE's backing store.  bspstore is the
 379      next location which will be written when the RSE needs to write
 380      to memory.  bsp is the address at which r32 in the current frame
 381      would be found if it were written to the backing store.
 382
 383      The IA-64 architecture provides read-only access to bsp and
 384      read/write access to bspstore (but only when the RSE is in
 385      the enforced lazy mode).  It should be noted that stores
 386      to bspstore also affect the value of bsp.  Changing bspstore
 387      does not affect the number of dirty entries between bspstore
 388      and bsp, so changing bspstore by N words will also cause bsp
 389      to be changed by (roughly) N as well.  (It could be N-1 or N+1
 390      depending upon where the NaT collection bits fall.)
 391
 392      OTOH, the Linux kernel provides read/write access to bsp (and
 393      currently read/write access to bspstore as well).  But it
 394      is definitely the case that if you change one, the other
 395      will change at the same time.  It is more useful to gdb to
 396      be able to change bsp.  So in order to prevent strange and
 397      undesirable things from happening when a dummy stack frame
 398      is popped (after calling an inferior function), we allow
 399      bspstore to be read, but not written.  (Note that popping
 400      a (generic) dummy stack frame causes all registers that
 401      were previously read from the inferior process to be written
 402      back.)  */
 403
 404   return regno < 0
 405          || regno >= gdbarch_num_regs (gdbarch)
 406          || u_offsets[regno] == -1
 407          || regno == IA64_BSPSTORE_REGNUM;
 408 }
 409
 410 void
 411 supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
 412 {
 413   int regi;
 414   const greg_t *regp = (const greg_t *) gregsetp;
 415
 416   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 417     {
 418       regcache->raw_supply (regi, regp + (regi - IA64_GR0_REGNUM));
 419     }
 420
 421   /* FIXME: NAT collection bits are at index 32; gotta deal with these
 422      somehow...  */
 423
 424   regcache->raw_supply (IA64_PR_REGNUM, regp + 33);
 425
 426   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 427     {
 428       regcache->raw_supply (regi, regp + 34 + (regi - IA64_BR0_REGNUM));
 429     }
 430
 431   regcache->raw_supply (IA64_IP_REGNUM, regp + 42);
 432   regcache->raw_supply (IA64_CFM_REGNUM, regp + 43);
 433   regcache->raw_supply (IA64_PSR_REGNUM, regp + 44);
 434   regcache->raw_supply (IA64_RSC_REGNUM, regp + 45);
 435   regcache->raw_supply (IA64_BSP_REGNUM, regp + 46);
 436   regcache->raw_supply (IA64_BSPSTORE_REGNUM, regp + 47);
 437   regcache->raw_supply (IA64_RNAT_REGNUM, regp + 48);
 438   regcache->raw_supply (IA64_CCV_REGNUM, regp + 49);
 439   regcache->raw_supply (IA64_UNAT_REGNUM, regp + 50);
 440   regcache->raw_supply (IA64_FPSR_REGNUM, regp + 51);
 441   regcache->raw_supply (IA64_PFS_REGNUM, regp + 52);
 442   regcache->raw_supply (IA64_LC_REGNUM, regp + 53);
 443   regcache->raw_supply (IA64_EC_REGNUM, regp + 54);
 444 }
 445
 446 void
 447 fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
 448 {
 449   int regi;
 450   greg_t *regp = (greg_t *) gregsetp;
 451
 452 #define COPY_REG(_idx_,_regi_) \
 453   if ((regno == -1) || regno == _regi_) \
 454     regcache->raw_collect (_regi_, regp + _idx_)
 455
 456   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 457     {
 458       COPY_REG (regi - IA64_GR0_REGNUM, regi);
 459     }
 460
 461   /* FIXME: NAT collection bits at index 32?  */
 462
 463   COPY_REG (33, IA64_PR_REGNUM);
 464
 465   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 466     {
 467       COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
 468     }
 469
 470   COPY_REG (42, IA64_IP_REGNUM);
 471   COPY_REG (43, IA64_CFM_REGNUM);
 472   COPY_REG (44, IA64_PSR_REGNUM);
 473   COPY_REG (45, IA64_RSC_REGNUM);
 474   COPY_REG (46, IA64_BSP_REGNUM);
 475   COPY_REG (47, IA64_BSPSTORE_REGNUM);
 476   COPY_REG (48, IA64_RNAT_REGNUM);
 477   COPY_REG (49, IA64_CCV_REGNUM);
 478   COPY_REG (50, IA64_UNAT_REGNUM);
 479   COPY_REG (51, IA64_FPSR_REGNUM);
 480   COPY_REG (52, IA64_PFS_REGNUM);
 481   COPY_REG (53, IA64_LC_REGNUM);
 482   COPY_REG (54, IA64_EC_REGNUM);
 483 }
 484
 485 /*  Given a pointer to a floating point register set in /proc format
 486    (fpregset_t *), unpack the register contents and supply them as gdb's
 487    idea of the current floating point register values.  */
 488
 489 void
 490 supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
 491 {
 492   int regi;
 493   const char *from;
 494   const gdb_byte f_zero[16] = { 0 };
 495   const gdb_byte f_one[16] =
 496     { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
 497
 498   /* Kernel generated cores have fr1==0 instead of 1.0.  Older GDBs
 499      did the same.  So ignore whatever might be recorded in fpregset_t
 500      for fr0/fr1 and always supply their expected values.  */
 501
 502   /* fr0 is always read as zero.  */
 503   regcache->raw_supply (IA64_FR0_REGNUM, f_zero);
 504   /* fr1 is always read as one (1.0).  */
 505   regcache->raw_supply (IA64_FR1_REGNUM, f_one);
 506
 507   for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 508     {
 509       from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 510       regcache->raw_supply (regi, from);
 511     }
 512 }
 513
 514 /*  Given a pointer to a floating point register set in /proc format
 515    (fpregset_t *), update the register specified by REGNO from gdb's idea
 516    of the current floating point register set.  If REGNO is -1, update
 517    them all.  */
 518
 519 void
 520 fill_fpregset (const struct regcache *regcache,
 521                fpregset_t *fpregsetp, int regno)
 522 {
 523   int regi;
 524
 525   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 526     {
 527       if ((regno == -1) || (regno == regi))
 528         regcache->raw_collect (regi, &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
 529     }
 530 }
 531
 532 #define IA64_PSR_DB (1UL << 24)
 533 #define IA64_PSR_DD (1UL << 39)
 534
 535 void
 536 ia64_linux_nat_target::enable_watchpoints_in_psr (ptid_t ptid)
 537 {
 538   struct regcache *regcache = get_thread_regcache (this, ptid);
 539   ULONGEST psr;
 540
 541   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
 542   if (!(psr & IA64_PSR_DB))
 543     {
 544       psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
 545                                    watchpoints and breakpoints.  */
 546       regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
 547     }
 548 }
 549
 550 static long debug_registers[8];
 551
 552 static void
 553 store_debug_register (ptid_t ptid, int idx, long val)
 554 {
 555   int tid;
 556
 557   tid = ptid.lwp ();
 558   if (tid == 0)
 559     tid = ptid.pid ();
 560
 561   (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
 562 }
 563
 564 static void
 565 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
 566                            long *dbr_mask)
 567 {
 568   if (dbr_addr)
 569     store_debug_register (ptid, 2 * idx, *dbr_addr);
 570   if (dbr_mask)
 571     store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
 572 }
 573
 574 static int
 575 is_power_of_2 (int val)
 576 {
 577   int i, onecount;
 578
 579   onecount = 0;
 580   for (i = 0; i < 8 * sizeof (val); i++)
 581     if (val & (1 << i))
 582       onecount++;
 583
 584   return onecount <= 1;
 585 }
 586
 587 int
 588 ia64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
 589                                           enum target_hw_bp_type type,
 590                                           struct expression *cond)
 591 {
 592   int idx;
 593   long dbr_addr, dbr_mask;
 594   int max_watchpoints = 4;
 595
 596   if (len <= 0 || !is_power_of_2 (len))
 597     return -1;
 598
 599   for (idx = 0; idx < max_watchpoints; idx++)
 600     {
 601       dbr_mask = debug_registers[idx * 2 + 1];
 602       if ((dbr_mask & (0x3UL << 62)) == 0)
 603         {
 604           /* Exit loop if both r and w bits clear.  */
 605           break;
 606         }
 607     }
 608
 609   if (idx == max_watchpoints)
 610     return -1;
 611
 612   dbr_addr = (long) addr;
 613   dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
 614   dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
 615   switch (type)
 616     {
 617     case hw_write:
 618       dbr_mask |= (1L << 62);                   /* Set w bit */
 619       break;
 620     case hw_read:
 621       dbr_mask |= (1L << 63);                   /* Set r bit */
 622       break;
 623     case hw_access:
 624       dbr_mask |= (3L << 62);                   /* Set both r and w bits */
 625       break;
 626     default:
 627       return -1;
 628     }
 629
 630   debug_registers[2 * idx] = dbr_addr;
 631   debug_registers[2 * idx + 1] = dbr_mask;
 632
 633   for (const lwp_info *lp : all_lwps ())
 634     {
 635       store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
 636       enable_watchpoints_in_psr (lp->ptid);
 637     }
 638
 639   return 0;
 640 }
 641
 642 int
 643 ia64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
 644                                           enum target_hw_bp_type type,
 645                                           struct expression *cond)
 646 {
 647   int idx;
 648   long dbr_addr, dbr_mask;
 649   int max_watchpoints = 4;
 650
 651   if (len <= 0 || !is_power_of_2 (len))
 652     return -1;
 653
 654   for (idx = 0; idx < max_watchpoints; idx++)
 655     {
 656       dbr_addr = debug_registers[2 * idx];
 657       dbr_mask = debug_registers[2 * idx + 1];
 658       if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
 659         {
 660           debug_registers[2 * idx] = 0;
 661           debug_registers[2 * idx + 1] = 0;
 662           dbr_addr = 0;
 663           dbr_mask = 0;
 664
 665           for (const lwp_info *lp : all_lwps ())
 666             store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
 667
 668           return 0;
 669         }
 670     }
 671   return -1;
 672 }
 673
 674 void
 675 ia64_linux_nat_target::low_new_thread (struct lwp_info *lp)
 676 {
 677   int i, any;
 678
 679   any = 0;
 680   for (i = 0; i < 8; i++)
 681     {
 682       if (debug_registers[i] != 0)
 683         any = 1;
 684       store_debug_register (lp->ptid, i, debug_registers[i]);
 685     }
 686
 687   if (any)
 688     enable_watchpoints_in_psr (lp->ptid);
 689 }
 690
 691 bool
 692 ia64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
 693 {
 694   CORE_ADDR psr;
 695   siginfo_t siginfo;
 696   struct regcache *regcache = get_current_regcache ();
 697
 698   if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
 699     return false;
 700
 701   if (siginfo.si_signo != SIGTRAP
 702       || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
 703     return false;
 704
 705   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
 706   psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
 707                            for the next instruction.  */
 708   regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
 709
 710   *addr_p = (CORE_ADDR) siginfo.si_addr;
 711   return true;
 712 }
 713
 714 bool
 715 ia64_linux_nat_target::stopped_by_watchpoint ()
 716 {
 717   CORE_ADDR addr;
 718   return stopped_data_address (&addr);
 719 }
 720
 721 int
 722 ia64_linux_nat_target::can_use_hw_breakpoint (enum bptype type,
 723                                               int cnt, int othertype)
 724 {
 725   return 1;
 726 }
 727
 728
 729 /* Fetch register REGNUM from the inferior.  */
 730
 731 static void
 732 ia64_linux_fetch_register (struct regcache *regcache, int regnum)
 733 {
 734   struct gdbarch *gdbarch = regcache->arch ();
 735   CORE_ADDR addr;
 736   size_t size;
 737   PTRACE_TYPE_RET *buf;
 738   pid_t pid;
 739   int i;
 740
 741   /* r0 cannot be fetched but is always zero.  */
 742   if (regnum == IA64_GR0_REGNUM)
 743     {
 744       const gdb_byte zero[8] = { 0 };
 745
 746       gdb_assert (sizeof (zero) == register_size (gdbarch, regnum));
 747       regcache->raw_supply (regnum, zero);
 748       return;
 749     }
 750
 751   /* fr0 cannot be fetched but is always zero.  */
 752   if (regnum == IA64_FR0_REGNUM)
 753     {
 754       const gdb_byte f_zero[16] = { 0 };
 755
 756       gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum));
 757       regcache->raw_supply (regnum, f_zero);
 758       return;
 759     }
 760
 761   /* fr1 cannot be fetched but is always one (1.0).  */
 762   if (regnum == IA64_FR1_REGNUM)
 763     {
 764       const gdb_byte f_one[16] =
 765         { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
 766
 767       gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum));
 768       regcache->raw_supply (regnum, f_one);
 769       return;
 770     }
 771
 772   if (ia64_cannot_fetch_register (gdbarch, regnum))
 773     {
 774       regcache->raw_supply (regnum, NULL);
 775       return;
 776     }
 777
 778   pid = get_ptrace_pid (regcache->ptid ());
 779
 780   /* This isn't really an address, but ptrace thinks of it as one.  */
 781   addr = ia64_register_addr (gdbarch, regnum);
 782   size = register_size (gdbarch, regnum);
 783
 784   gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
 785   buf = (PTRACE_TYPE_RET *) alloca (size);
 786
 787   /* Read the register contents from the inferior a chunk at a time.  */
 788   for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
 789     {
 790       errno = 0;
 791       buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
 792       if (errno != 0)
 793         error (_("Couldn't read register %s (#%d): %s."),
 794                gdbarch_register_name (gdbarch, regnum),
 795                regnum, safe_strerror (errno));
 796
 797       addr += sizeof (PTRACE_TYPE_RET);
 798     }
 799   regcache->raw_supply (regnum, buf);
 800 }
 801
 802 /* Fetch register REGNUM from the inferior.  If REGNUM is -1, do this
 803    for all registers.  */
 804
 805 void
 806 ia64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
 807 {
 808   if (regnum == -1)
 809     for (regnum = 0;
 810          regnum < gdbarch_num_regs (regcache->arch ());
 811          regnum++)
 812       ia64_linux_fetch_register (regcache, regnum);
 813   else
 814     ia64_linux_fetch_register (regcache, regnum);
 815 }
 816
 817 /* Store register REGNUM into the inferior.  */
 818
 819 static void
 820 ia64_linux_store_register (const struct regcache *regcache, int regnum)
 821 {
 822   struct gdbarch *gdbarch = regcache->arch ();
 823   CORE_ADDR addr;
 824   size_t size;
 825   PTRACE_TYPE_RET *buf;
 826   pid_t pid;
 827   int i;
 828
 829   if (ia64_cannot_store_register (gdbarch, regnum))
 830     return;
 831
 832   pid = get_ptrace_pid (regcache->ptid ());
 833
 834   /* This isn't really an address, but ptrace thinks of it as one.  */
 835   addr = ia64_register_addr (gdbarch, regnum);
 836   size = register_size (gdbarch, regnum);
 837
 838   gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
 839   buf = (PTRACE_TYPE_RET *) alloca (size);
 840
 841   /* Write the register contents into the inferior a chunk at a time.  */
 842   regcache->raw_collect (regnum, buf);
 843   for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
 844     {
 845       errno = 0;
 846       ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
 847       if (errno != 0)
 848         error (_("Couldn't write register %s (#%d): %s."),
 849                gdbarch_register_name (gdbarch, regnum),
 850                regnum, safe_strerror (errno));
 851
 852       addr += sizeof (PTRACE_TYPE_RET);
 853     }
 854 }
 855
 856 /* Store register REGNUM back into the inferior.  If REGNUM is -1, do
 857    this for all registers.  */
 858
 859 void
 860 ia64_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
 861 {
 862   if (regnum == -1)
 863     for (regnum = 0;
 864          regnum < gdbarch_num_regs (regcache->arch ());
 865          regnum++)
 866       ia64_linux_store_register (regcache, regnum);
 867   else
 868     ia64_linux_store_register (regcache, regnum);
 869 }
 870
 871 /* Implement the xfer_partial target_ops method.  */
 872
 873 enum target_xfer_status
 874 ia64_linux_nat_target::xfer_partial (enum target_object object,
 875                                      const char *annex,
 876                                      gdb_byte *readbuf, const gdb_byte *writebuf,
 877                                      ULONGEST offset, ULONGEST len,
 878                                      ULONGEST *xfered_len)
 879 {
 880   if (object == TARGET_OBJECT_UNWIND_TABLE && readbuf != NULL)
 881     {
 882       static long gate_table_size;
 883       gdb_byte *tmp_buf;
 884       long res;
 885
 886       /* Probe for the table size once.  */
 887       if (gate_table_size == 0)
 888         gate_table_size = syscall (__NR_getunwind, NULL, 0);
 889       if (gate_table_size < 0)
 890         return TARGET_XFER_E_IO;
 891
 892       if (offset >= gate_table_size)
 893         return TARGET_XFER_EOF;
 894
 895       tmp_buf = (gdb_byte *) alloca (gate_table_size);
 896       res = syscall (__NR_getunwind, tmp_buf, gate_table_size);
 897       if (res < 0)
 898         return TARGET_XFER_E_IO;
 899       gdb_assert (res == gate_table_size);
 900
 901       if (offset + len > gate_table_size)
 902         len = gate_table_size - offset;
 903
 904       memcpy (readbuf, tmp_buf + offset, len);
 905       *xfered_len = len;
 906       return TARGET_XFER_OK;
 907     }
 908
 909   return linux_nat_target::xfer_partial (object, annex, readbuf, writebuf,
 910                                          offset, len, xfered_len);
 911 }
 912
 913 /* For break.b instruction ia64 CPU forgets the immediate value and generates
 914    SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
 915    ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
 916    difference for the signals here.  */
 917
 918 bool
 919 ia64_linux_nat_target::low_status_is_event (int status)
 920 {
 921   return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
 922                                  || WSTOPSIG (status) == SIGILL);
 923 }
 924
 925 void _initialize_ia64_linux_nat ();
 926 void
 927 _initialize_ia64_linux_nat ()
 928 {
 929   /* Register the target.  */
 930   linux_target = &the_ia64_linux_nat_target;
 931   add_inf_child_target (&the_ia64_linux_nat_target);
 932 }