AArch64: Implement choice between Cortex-A53 erratum workarounds. (PR ld/24373)
[binutils-gdb.git] / ld / testsuite / ld-aarch64 / bti-plt-1.d
blob618a6a9c15395bf786fd8c60f4569f97d78fcc13
1 #name: Check --force-bti emits BTI PLT (shared)
2 #source: bti-plt-1.s
3 #as: -mabi=lp64
4 #ld: -shared --force-bti -T bti-plt.ld
5 #objdump: -dr -j .plt
7 [^:]*: *file format elf64-.*aarch64
9 Disassembly of section \.plt:
11 [0-9]+ <.*>:
12 .*: d503245f bti c
13 .*: a9bf7bf0 stp x16, x30, \[sp, #-16\]!
14 .*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
15 .*: f9400e11 ldr x17, \[x16, #24\]
16 .*: 91006210 add x16, x16, #0x18
17 .*: d61f0220 br x17
18 .*: d503201f nop
19 .*: d503201f nop
21 [0-9]+ <.*>:
22 .*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
23 .*: f9401211 ldr x17, \[x16, #32\]
24 .*: 91008210 add x16, x16, #0x20
25 .*: d61f0220 br x17
27 [0-9]+ <.*>:
28 .*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
29 .*: f9401611 ldr x17, \[x16, #40\]
30 .*: 9100a210 add x16, x16, #0x28
31 .*: d61f0220 br x17