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[PATCH 37/57][Arm][OBJDUMP] Add framework for MVE instructions
[binutils-gdb.git] / sim / iq2000 / sem-switch.c
blobc939e3a90ce0311ac72e88f5199e7c249fc39c4d
1 /* Simulator instruction semantics for iq2000bf.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright 1996-2019 Free Software Foundation, Inc.
6
7 This file is part of the GNU simulators.
8
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, see <http://www.gnu.org/licenses/>.
21
22 */
23
24 #ifdef DEFINE_LABELS
25
26 /* The labels have the case they have because the enum of insn types
27 is all uppercase and in the non-stdc case the insn symbol is built
28 into the enum name. */
29
30 static struct {
31 int index;
32 void *label;
33 } labels[] = {
34 { IQ2000BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
35 { IQ2000BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
36 { IQ2000BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
37 { IQ2000BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
38 { IQ2000BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
39 { IQ2000BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
40 { IQ2000BF_INSN_ADD, && case_sem_INSN_ADD },
41 { IQ2000BF_INSN_ADDI, && case_sem_INSN_ADDI },
42 { IQ2000BF_INSN_ADDIU, && case_sem_INSN_ADDIU },
43 { IQ2000BF_INSN_ADDU, && case_sem_INSN_ADDU },
44 { IQ2000BF_INSN_ADO16, && case_sem_INSN_ADO16 },
45 { IQ2000BF_INSN_AND, && case_sem_INSN_AND },
46 { IQ2000BF_INSN_ANDI, && case_sem_INSN_ANDI },
47 { IQ2000BF_INSN_ANDOI, && case_sem_INSN_ANDOI },
48 { IQ2000BF_INSN_NOR, && case_sem_INSN_NOR },
49 { IQ2000BF_INSN_OR, && case_sem_INSN_OR },
50 { IQ2000BF_INSN_ORI, && case_sem_INSN_ORI },
51 { IQ2000BF_INSN_RAM, && case_sem_INSN_RAM },
52 { IQ2000BF_INSN_SLL, && case_sem_INSN_SLL },
53 { IQ2000BF_INSN_SLLV, && case_sem_INSN_SLLV },
54 { IQ2000BF_INSN_SLMV, && case_sem_INSN_SLMV },
55 { IQ2000BF_INSN_SLT, && case_sem_INSN_SLT },
56 { IQ2000BF_INSN_SLTI, && case_sem_INSN_SLTI },
57 { IQ2000BF_INSN_SLTIU, && case_sem_INSN_SLTIU },
58 { IQ2000BF_INSN_SLTU, && case_sem_INSN_SLTU },
59 { IQ2000BF_INSN_SRA, && case_sem_INSN_SRA },
60 { IQ2000BF_INSN_SRAV, && case_sem_INSN_SRAV },
61 { IQ2000BF_INSN_SRL, && case_sem_INSN_SRL },
62 { IQ2000BF_INSN_SRLV, && case_sem_INSN_SRLV },
63 { IQ2000BF_INSN_SRMV, && case_sem_INSN_SRMV },
64 { IQ2000BF_INSN_SUB, && case_sem_INSN_SUB },
65 { IQ2000BF_INSN_SUBU, && case_sem_INSN_SUBU },
66 { IQ2000BF_INSN_XOR, && case_sem_INSN_XOR },
67 { IQ2000BF_INSN_XORI, && case_sem_INSN_XORI },
68 { IQ2000BF_INSN_BBI, && case_sem_INSN_BBI },
69 { IQ2000BF_INSN_BBIN, && case_sem_INSN_BBIN },
70 { IQ2000BF_INSN_BBV, && case_sem_INSN_BBV },
71 { IQ2000BF_INSN_BBVN, && case_sem_INSN_BBVN },
72 { IQ2000BF_INSN_BEQ, && case_sem_INSN_BEQ },
73 { IQ2000BF_INSN_BEQL, && case_sem_INSN_BEQL },
74 { IQ2000BF_INSN_BGEZ, && case_sem_INSN_BGEZ },
75 { IQ2000BF_INSN_BGEZAL, && case_sem_INSN_BGEZAL },
76 { IQ2000BF_INSN_BGEZALL, && case_sem_INSN_BGEZALL },
77 { IQ2000BF_INSN_BGEZL, && case_sem_INSN_BGEZL },
78 { IQ2000BF_INSN_BLTZ, && case_sem_INSN_BLTZ },
79 { IQ2000BF_INSN_BLTZL, && case_sem_INSN_BLTZL },
80 { IQ2000BF_INSN_BLTZAL, && case_sem_INSN_BLTZAL },
81 { IQ2000BF_INSN_BLTZALL, && case_sem_INSN_BLTZALL },
82 { IQ2000BF_INSN_BMB0, && case_sem_INSN_BMB0 },
83 { IQ2000BF_INSN_BMB1, && case_sem_INSN_BMB1 },
84 { IQ2000BF_INSN_BMB2, && case_sem_INSN_BMB2 },
85 { IQ2000BF_INSN_BMB3, && case_sem_INSN_BMB3 },
86 { IQ2000BF_INSN_BNE, && case_sem_INSN_BNE },
87 { IQ2000BF_INSN_BNEL, && case_sem_INSN_BNEL },
88 { IQ2000BF_INSN_JALR, && case_sem_INSN_JALR },
89 { IQ2000BF_INSN_JR, && case_sem_INSN_JR },
90 { IQ2000BF_INSN_LB, && case_sem_INSN_LB },
91 { IQ2000BF_INSN_LBU, && case_sem_INSN_LBU },
92 { IQ2000BF_INSN_LH, && case_sem_INSN_LH },
93 { IQ2000BF_INSN_LHU, && case_sem_INSN_LHU },
94 { IQ2000BF_INSN_LUI, && case_sem_INSN_LUI },
95 { IQ2000BF_INSN_LW, && case_sem_INSN_LW },
96 { IQ2000BF_INSN_SB, && case_sem_INSN_SB },
97 { IQ2000BF_INSN_SH, && case_sem_INSN_SH },
98 { IQ2000BF_INSN_SW, && case_sem_INSN_SW },
99 { IQ2000BF_INSN_BREAK, && case_sem_INSN_BREAK },
100 { IQ2000BF_INSN_SYSCALL, && case_sem_INSN_SYSCALL },
101 { IQ2000BF_INSN_ANDOUI, && case_sem_INSN_ANDOUI },
102 { IQ2000BF_INSN_ORUI, && case_sem_INSN_ORUI },
103 { IQ2000BF_INSN_BGTZ, && case_sem_INSN_BGTZ },
104 { IQ2000BF_INSN_BGTZL, && case_sem_INSN_BGTZL },
105 { IQ2000BF_INSN_BLEZ, && case_sem_INSN_BLEZ },
106 { IQ2000BF_INSN_BLEZL, && case_sem_INSN_BLEZL },
107 { IQ2000BF_INSN_MRGB, && case_sem_INSN_MRGB },
108 { IQ2000BF_INSN_BCTXT, && case_sem_INSN_BCTXT },
109 { IQ2000BF_INSN_BC0F, && case_sem_INSN_BC0F },
110 { IQ2000BF_INSN_BC0FL, && case_sem_INSN_BC0FL },
111 { IQ2000BF_INSN_BC3F, && case_sem_INSN_BC3F },
112 { IQ2000BF_INSN_BC3FL, && case_sem_INSN_BC3FL },
113 { IQ2000BF_INSN_BC0T, && case_sem_INSN_BC0T },
114 { IQ2000BF_INSN_BC0TL, && case_sem_INSN_BC0TL },
115 { IQ2000BF_INSN_BC3T, && case_sem_INSN_BC3T },
116 { IQ2000BF_INSN_BC3TL, && case_sem_INSN_BC3TL },
117 { IQ2000BF_INSN_CFC0, && case_sem_INSN_CFC0 },
118 { IQ2000BF_INSN_CFC1, && case_sem_INSN_CFC1 },
119 { IQ2000BF_INSN_CFC2, && case_sem_INSN_CFC2 },
120 { IQ2000BF_INSN_CFC3, && case_sem_INSN_CFC3 },
121 { IQ2000BF_INSN_CHKHDR, && case_sem_INSN_CHKHDR },
122 { IQ2000BF_INSN_CTC0, && case_sem_INSN_CTC0 },
123 { IQ2000BF_INSN_CTC1, && case_sem_INSN_CTC1 },
124 { IQ2000BF_INSN_CTC2, && case_sem_INSN_CTC2 },
125 { IQ2000BF_INSN_CTC3, && case_sem_INSN_CTC3 },
126 { IQ2000BF_INSN_JCR, && case_sem_INSN_JCR },
127 { IQ2000BF_INSN_LUC32, && case_sem_INSN_LUC32 },
128 { IQ2000BF_INSN_LUC32L, && case_sem_INSN_LUC32L },
129 { IQ2000BF_INSN_LUC64, && case_sem_INSN_LUC64 },
130 { IQ2000BF_INSN_LUC64L, && case_sem_INSN_LUC64L },
131 { IQ2000BF_INSN_LUK, && case_sem_INSN_LUK },
132 { IQ2000BF_INSN_LULCK, && case_sem_INSN_LULCK },
133 { IQ2000BF_INSN_LUM32, && case_sem_INSN_LUM32 },
134 { IQ2000BF_INSN_LUM32L, && case_sem_INSN_LUM32L },
135 { IQ2000BF_INSN_LUM64, && case_sem_INSN_LUM64 },
136 { IQ2000BF_INSN_LUM64L, && case_sem_INSN_LUM64L },
137 { IQ2000BF_INSN_LUR, && case_sem_INSN_LUR },
138 { IQ2000BF_INSN_LURL, && case_sem_INSN_LURL },
139 { IQ2000BF_INSN_LUULCK, && case_sem_INSN_LUULCK },
140 { IQ2000BF_INSN_MFC0, && case_sem_INSN_MFC0 },
141 { IQ2000BF_INSN_MFC1, && case_sem_INSN_MFC1 },
142 { IQ2000BF_INSN_MFC2, && case_sem_INSN_MFC2 },
143 { IQ2000BF_INSN_MFC3, && case_sem_INSN_MFC3 },
144 { IQ2000BF_INSN_MTC0, && case_sem_INSN_MTC0 },
145 { IQ2000BF_INSN_MTC1, && case_sem_INSN_MTC1 },
146 { IQ2000BF_INSN_MTC2, && case_sem_INSN_MTC2 },
147 { IQ2000BF_INSN_MTC3, && case_sem_INSN_MTC3 },
148 { IQ2000BF_INSN_PKRL, && case_sem_INSN_PKRL },
149 { IQ2000BF_INSN_PKRLR1, && case_sem_INSN_PKRLR1 },
150 { IQ2000BF_INSN_PKRLR30, && case_sem_INSN_PKRLR30 },
151 { IQ2000BF_INSN_RB, && case_sem_INSN_RB },
152 { IQ2000BF_INSN_RBR1, && case_sem_INSN_RBR1 },
153 { IQ2000BF_INSN_RBR30, && case_sem_INSN_RBR30 },
154 { IQ2000BF_INSN_RFE, && case_sem_INSN_RFE },
155 { IQ2000BF_INSN_RX, && case_sem_INSN_RX },
156 { IQ2000BF_INSN_RXR1, && case_sem_INSN_RXR1 },
157 { IQ2000BF_INSN_RXR30, && case_sem_INSN_RXR30 },
158 { IQ2000BF_INSN_SLEEP, && case_sem_INSN_SLEEP },
159 { IQ2000BF_INSN_SRRD, && case_sem_INSN_SRRD },
160 { IQ2000BF_INSN_SRRDL, && case_sem_INSN_SRRDL },
161 { IQ2000BF_INSN_SRULCK, && case_sem_INSN_SRULCK },
162 { IQ2000BF_INSN_SRWR, && case_sem_INSN_SRWR },
163 { IQ2000BF_INSN_SRWRU, && case_sem_INSN_SRWRU },
164 { IQ2000BF_INSN_TRAPQFL, && case_sem_INSN_TRAPQFL },
165 { IQ2000BF_INSN_TRAPQNE, && case_sem_INSN_TRAPQNE },
166 { IQ2000BF_INSN_TRAPREL, && case_sem_INSN_TRAPREL },
167 { IQ2000BF_INSN_WB, && case_sem_INSN_WB },
168 { IQ2000BF_INSN_WBU, && case_sem_INSN_WBU },
169 { IQ2000BF_INSN_WBR1, && case_sem_INSN_WBR1 },
170 { IQ2000BF_INSN_WBR1U, && case_sem_INSN_WBR1U },
171 { IQ2000BF_INSN_WBR30, && case_sem_INSN_WBR30 },
172 { IQ2000BF_INSN_WBR30U, && case_sem_INSN_WBR30U },
173 { IQ2000BF_INSN_WX, && case_sem_INSN_WX },
174 { IQ2000BF_INSN_WXU, && case_sem_INSN_WXU },
175 { IQ2000BF_INSN_WXR1, && case_sem_INSN_WXR1 },
176 { IQ2000BF_INSN_WXR1U, && case_sem_INSN_WXR1U },
177 { IQ2000BF_INSN_WXR30, && case_sem_INSN_WXR30 },
178 { IQ2000BF_INSN_WXR30U, && case_sem_INSN_WXR30U },
179 { IQ2000BF_INSN_LDW, && case_sem_INSN_LDW },
180 { IQ2000BF_INSN_SDW, && case_sem_INSN_SDW },
181 { IQ2000BF_INSN_J, && case_sem_INSN_J },
182 { IQ2000BF_INSN_JAL, && case_sem_INSN_JAL },
183 { IQ2000BF_INSN_BMB, && case_sem_INSN_BMB },
184 { 0, 0 }
185 };
186 int i;
187
188 for (i = 0; labels[i].label != 0; ++i)
189 {
190 #if FAST_P
191 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
192 #else
193 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
194 #endif
195 }
196
197 #undef DEFINE_LABELS
198 #endif /* DEFINE_LABELS */
199
200 #ifdef DEFINE_SWITCH
201
202 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
203 off frills like tracing and profiling. */
204 /* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something
205 that can cause it to be optimized out. Another way would be to emit
206 special handlers into the instruction "stream". */
207
208 #if FAST_P
209 #undef CGEN_TRACE_RESULT
210 #define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
211 #endif
212
213 #undef GET_ATTR
214 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
215
216 {
217
218 #if WITH_SCACHE_PBB
219
220 /* Branch to next handler without going around main loop. */
221 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
222 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
223
224 #else /* ! WITH_SCACHE_PBB */
225
226 #define NEXT(vpc) BREAK (sem)
227 #ifdef __GNUC__
228 #if FAST_P
229 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
230 #else
231 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
232 #endif
233 #else
234 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
235 #endif
236
237 #endif /* ! WITH_SCACHE_PBB */
238
239 {
240
241 CASE (sem, INSN_X_INVALID) : /* --invalid-- */
242 {
243 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
244 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
245 #define FLD(f) abuf->fields.sfmt_empty.f
246 int UNUSED written = 0;
247 IADDR UNUSED pc = abuf->addr;
248 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
249
250 {
251 /* Update the recorded pc in the cpu state struct.
252 Only necessary for WITH_SCACHE case, but to avoid the
253 conditional compilation .... */
254 SET_H_PC (pc);
255 /* Virtual insns have zero size. Overwrite vpc with address of next insn
256 using the default-insn-bitsize spec. When executing insns in parallel
257 we may want to queue the fault and continue execution. */
258 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
259 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
260 }
261
262 #undef FLD
263 }
264 NEXT (vpc);
265
266 CASE (sem, INSN_X_AFTER) : /* --after-- */
267 {
268 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
269 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
270 #define FLD(f) abuf->fields.sfmt_empty.f
271 int UNUSED written = 0;
272 IADDR UNUSED pc = abuf->addr;
273 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
274
275 {
276 #if WITH_SCACHE_PBB_IQ2000BF
277 iq2000bf_pbb_after (current_cpu, sem_arg);
278 #endif
279 }
280
281 #undef FLD
282 }
283 NEXT (vpc);
284
285 CASE (sem, INSN_X_BEFORE) : /* --before-- */
286 {
287 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
288 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
289 #define FLD(f) abuf->fields.sfmt_empty.f
290 int UNUSED written = 0;
291 IADDR UNUSED pc = abuf->addr;
292 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
293
294 {
295 #if WITH_SCACHE_PBB_IQ2000BF
296 iq2000bf_pbb_before (current_cpu, sem_arg);
297 #endif
298 }
299
300 #undef FLD
301 }
302 NEXT (vpc);
303
304 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
305 {
306 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
307 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
308 #define FLD(f) abuf->fields.sfmt_empty.f
309 int UNUSED written = 0;
310 IADDR UNUSED pc = abuf->addr;
311 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
312
313 {
314 #if WITH_SCACHE_PBB_IQ2000BF
315 #ifdef DEFINE_SWITCH
316 vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg,
317 pbb_br_type, pbb_br_npc);
318 BREAK (sem);
319 #else
320 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
321 vpc = iq2000bf_pbb_cti_chain (current_cpu, sem_arg,
322 CPU_PBB_BR_TYPE (current_cpu),
323 CPU_PBB_BR_NPC (current_cpu));
324 #endif
325 #endif
326 }
327
328 #undef FLD
329 }
330 NEXT (vpc);
331
332 CASE (sem, INSN_X_CHAIN) : /* --chain-- */
333 {
334 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
335 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
336 #define FLD(f) abuf->fields.sfmt_empty.f
337 int UNUSED written = 0;
338 IADDR UNUSED pc = abuf->addr;
339 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
340
341 {
342 #if WITH_SCACHE_PBB_IQ2000BF
343 vpc = iq2000bf_pbb_chain (current_cpu, sem_arg);
344 #ifdef DEFINE_SWITCH
345 BREAK (sem);
346 #endif
347 #endif
348 }
349
350 #undef FLD
351 }
352 NEXT (vpc);
353
354 CASE (sem, INSN_X_BEGIN) : /* --begin-- */
355 {
356 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
357 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
358 #define FLD(f) abuf->fields.sfmt_empty.f
359 int UNUSED written = 0;
360 IADDR UNUSED pc = abuf->addr;
361 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
362
363 {
364 #if WITH_SCACHE_PBB_IQ2000BF
365 #if defined DEFINE_SWITCH || defined FAST_P
366 /* In the switch case FAST_P is a constant, allowing several optimizations
367 in any called inline functions. */
368 vpc = iq2000bf_pbb_begin (current_cpu, FAST_P);
369 #else
370 #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
371 vpc = iq2000bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
372 #else
373 vpc = iq2000bf_pbb_begin (current_cpu, 0);
374 #endif
375 #endif
376 #endif
377 }
378
379 #undef FLD
380 }
381 NEXT (vpc);
382
383 CASE (sem, INSN_ADD) : /* add $rd,$rs,$rt */
384 {
385 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
386 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
387 #define FLD(f) abuf->fields.sfmt_mrgb.f
388 int UNUSED written = 0;
389 IADDR UNUSED pc = abuf->addr;
390 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
391
392 {
393 SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));
394 SET_H_GR (FLD (f_rd), opval);
395 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
396 }
397
398 #undef FLD
399 }
400 NEXT (vpc);
401
402 CASE (sem, INSN_ADDI) : /* addi $rt,$rs,$lo16 */
403 {
404 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
405 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
406 #define FLD(f) abuf->fields.sfmt_addi.f
407 int UNUSED written = 0;
408 IADDR UNUSED pc = abuf->addr;
409 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
410
411 {
412 SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))));
413 SET_H_GR (FLD (f_rt), opval);
414 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
415 }
416
417 #undef FLD
418 }
419 NEXT (vpc);
420
421 CASE (sem, INSN_ADDIU) : /* addiu $rt,$rs,$lo16 */
422 {
423 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
424 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
425 #define FLD(f) abuf->fields.sfmt_addi.f
426 int UNUSED written = 0;
427 IADDR UNUSED pc = abuf->addr;
428 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
429
430 {
431 SI opval = ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))));
432 SET_H_GR (FLD (f_rt), opval);
433 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
434 }
435
436 #undef FLD
437 }
438 NEXT (vpc);
439
440 CASE (sem, INSN_ADDU) : /* addu $rd,$rs,$rt */
441 {
442 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
443 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
444 #define FLD(f) abuf->fields.sfmt_mrgb.f
445 int UNUSED written = 0;
446 IADDR UNUSED pc = abuf->addr;
447 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
448
449 {
450 SI opval = ADDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));
451 SET_H_GR (FLD (f_rd), opval);
452 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
453 }
454
455 #undef FLD
456 }
457 NEXT (vpc);
458
459 CASE (sem, INSN_ADO16) : /* ado16 $rd,$rs,$rt */
460 {
461 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
462 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
463 #define FLD(f) abuf->fields.sfmt_mrgb.f
464 int UNUSED written = 0;
465 IADDR UNUSED pc = abuf->addr;
466 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
467
468 {
469 HI tmp_high;
470 HI tmp_low;
471 tmp_low = ADDHI (ANDHI (GET_H_GR (FLD (f_rs)), 65535), ANDHI (GET_H_GR (FLD (f_rt)), 65535));
472 tmp_high = ADDHI (SRLSI (GET_H_GR (FLD (f_rs)), 16), SRLSI (GET_H_GR (FLD (f_rt)), 16));
473 {
474 SI opval = ORSI (SLLSI (tmp_high, 16), tmp_low);
475 SET_H_GR (FLD (f_rd), opval);
476 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
477 }
478 }
479
480 #undef FLD
481 }
482 NEXT (vpc);
483
484 CASE (sem, INSN_AND) : /* and $rd,$rs,$rt */
485 {
486 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
487 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
488 #define FLD(f) abuf->fields.sfmt_mrgb.f
489 int UNUSED written = 0;
490 IADDR UNUSED pc = abuf->addr;
491 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
492
493 {
494 SI opval = ANDSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));
495 SET_H_GR (FLD (f_rd), opval);
496 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
497 }
498
499 #undef FLD
500 }
501 NEXT (vpc);
502
503 CASE (sem, INSN_ANDI) : /* andi $rt,$rs,$lo16 */
504 {
505 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
506 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
507 #define FLD(f) abuf->fields.sfmt_addi.f
508 int UNUSED written = 0;
509 IADDR UNUSED pc = abuf->addr;
510 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
511
512 {
513 SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm)));
514 SET_H_GR (FLD (f_rt), opval);
515 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
516 }
517
518 #undef FLD
519 }
520 NEXT (vpc);
521
522 CASE (sem, INSN_ANDOI) : /* andoi $rt,$rs,$lo16 */
523 {
524 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
525 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
526 #define FLD(f) abuf->fields.sfmt_addi.f
527 int UNUSED written = 0;
528 IADDR UNUSED pc = abuf->addr;
529 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
530
531 {
532 SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (0xffff0000, EXTHISI (TRUNCSIHI (FLD (f_imm)))));
533 SET_H_GR (FLD (f_rt), opval);
534 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
535 }
536
537 #undef FLD
538 }
539 NEXT (vpc);
540
541 CASE (sem, INSN_NOR) : /* nor $rd,$rs,$rt */
542 {
543 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
544 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
545 #define FLD(f) abuf->fields.sfmt_mrgb.f
546 int UNUSED written = 0;
547 IADDR UNUSED pc = abuf->addr;
548 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
549
550 {
551 SI opval = INVSI (ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt))));
552 SET_H_GR (FLD (f_rd), opval);
553 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
554 }
555
556 #undef FLD
557 }
558 NEXT (vpc);
559
560 CASE (sem, INSN_OR) : /* or $rd,$rs,$rt */
561 {
562 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
563 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
564 #define FLD(f) abuf->fields.sfmt_mrgb.f
565 int UNUSED written = 0;
566 IADDR UNUSED pc = abuf->addr;
567 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
568
569 {
570 SI opval = ORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));
571 SET_H_GR (FLD (f_rd), opval);
572 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
573 }
574
575 #undef FLD
576 }
577 NEXT (vpc);
578
579 CASE (sem, INSN_ORI) : /* ori $rt,$rs,$lo16 */
580 {
581 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
582 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
583 #define FLD(f) abuf->fields.sfmt_addi.f
584 int UNUSED written = 0;
585 IADDR UNUSED pc = abuf->addr;
586 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
587
588 {
589 SI opval = ORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm)));
590 SET_H_GR (FLD (f_rt), opval);
591 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
592 }
593
594 #undef FLD
595 }
596 NEXT (vpc);
597
598 CASE (sem, INSN_RAM) : /* ram $rd,$rt,$shamt,$maskl,$maskr */
599 {
600 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
601 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
602 #define FLD(f) abuf->fields.sfmt_ram.f
603 int UNUSED written = 0;
604 IADDR UNUSED pc = abuf->addr;
605 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
606
607 {
608 {
609 SI opval = RORSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt));
610 SET_H_GR (FLD (f_rd), opval);
611 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
612 }
613 {
614 SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SRLSI (0xffffffff, FLD (f_maskl)));
615 SET_H_GR (FLD (f_rd), opval);
616 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
617 }
618 {
619 SI opval = ANDSI (GET_H_GR (FLD (f_rd)), SLLSI (0xffffffff, FLD (f_rs)));
620 SET_H_GR (FLD (f_rd), opval);
621 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
622 }
623 }
624
625 #undef FLD
626 }
627 NEXT (vpc);
628
629 CASE (sem, INSN_SLL) : /* sll $rd,$rt,$shamt */
630 {
631 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
632 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
633 #define FLD(f) abuf->fields.sfmt_ram.f
634 int UNUSED written = 0;
635 IADDR UNUSED pc = abuf->addr;
636 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
637
638 {
639 SI opval = SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt));
640 SET_H_GR (FLD (f_rd), opval);
641 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
642 }
643
644 #undef FLD
645 }
646 NEXT (vpc);
647
648 CASE (sem, INSN_SLLV) : /* sllv $rd,$rt,$rs */
649 {
650 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
651 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
652 #define FLD(f) abuf->fields.sfmt_mrgb.f
653 int UNUSED written = 0;
654 IADDR UNUSED pc = abuf->addr;
655 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
656
657 {
658 SI opval = SLLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31));
659 SET_H_GR (FLD (f_rd), opval);
660 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
661 }
662
663 #undef FLD
664 }
665 NEXT (vpc);
666
667 CASE (sem, INSN_SLMV) : /* slmv $rd,$rt,$rs,$shamt */
668 {
669 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
670 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
671 #define FLD(f) abuf->fields.sfmt_ram.f
672 int UNUSED written = 0;
673 IADDR UNUSED pc = abuf->addr;
674 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
675
676 {
677 SI opval = ANDSI (SLLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SRLSI (0xffffffff, GET_H_GR (FLD (f_rs))));
678 SET_H_GR (FLD (f_rd), opval);
679 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
680 }
681
682 #undef FLD
683 }
684 NEXT (vpc);
685
686 CASE (sem, INSN_SLT) : /* slt $rd,$rs,$rt */
687 {
688 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
689 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
690 #define FLD(f) abuf->fields.sfmt_mrgb.f
691 int UNUSED written = 0;
692 IADDR UNUSED pc = abuf->addr;
693 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
694
695 if (LTSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) {
696 {
697 SI opval = 1;
698 SET_H_GR (FLD (f_rd), opval);
699 written |= (1 << 2);
700 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
701 }
702 } else {
703 {
704 SI opval = 0;
705 SET_H_GR (FLD (f_rd), opval);
706 written |= (1 << 2);
707 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
708 }
709 }
710
711 abuf->written = written;
712 #undef FLD
713 }
714 NEXT (vpc);
715
716 CASE (sem, INSN_SLTI) : /* slti $rt,$rs,$imm */
717 {
718 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
719 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
720 #define FLD(f) abuf->fields.sfmt_addi.f
721 int UNUSED written = 0;
722 IADDR UNUSED pc = abuf->addr;
723 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
724
725 if (LTSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))) {
726 {
727 SI opval = 1;
728 SET_H_GR (FLD (f_rt), opval);
729 written |= (1 << 2);
730 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
731 }
732 } else {
733 {
734 SI opval = 0;
735 SET_H_GR (FLD (f_rt), opval);
736 written |= (1 << 2);
737 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
738 }
739 }
740
741 abuf->written = written;
742 #undef FLD
743 }
744 NEXT (vpc);
745
746 CASE (sem, INSN_SLTIU) : /* sltiu $rt,$rs,$imm */
747 {
748 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
749 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
750 #define FLD(f) abuf->fields.sfmt_addi.f
751 int UNUSED written = 0;
752 IADDR UNUSED pc = abuf->addr;
753 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
754
755 if (LTUSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))) {
756 {
757 SI opval = 1;
758 SET_H_GR (FLD (f_rt), opval);
759 written |= (1 << 2);
760 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
761 }
762 } else {
763 {
764 SI opval = 0;
765 SET_H_GR (FLD (f_rt), opval);
766 written |= (1 << 2);
767 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
768 }
769 }
770
771 abuf->written = written;
772 #undef FLD
773 }
774 NEXT (vpc);
775
776 CASE (sem, INSN_SLTU) : /* sltu $rd,$rs,$rt */
777 {
778 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
779 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
780 #define FLD(f) abuf->fields.sfmt_mrgb.f
781 int UNUSED written = 0;
782 IADDR UNUSED pc = abuf->addr;
783 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
784
785 if (LTUSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) {
786 {
787 SI opval = 1;
788 SET_H_GR (FLD (f_rd), opval);
789 written |= (1 << 2);
790 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
791 }
792 } else {
793 {
794 SI opval = 0;
795 SET_H_GR (FLD (f_rd), opval);
796 written |= (1 << 2);
797 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
798 }
799 }
800
801 abuf->written = written;
802 #undef FLD
803 }
804 NEXT (vpc);
805
806 CASE (sem, INSN_SRA) : /* sra $rd,$rt,$shamt */
807 {
808 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
809 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
810 #define FLD(f) abuf->fields.sfmt_ram.f
811 int UNUSED written = 0;
812 IADDR UNUSED pc = abuf->addr;
813 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
814
815 {
816 SI opval = SRASI (GET_H_GR (FLD (f_rt)), FLD (f_shamt));
817 SET_H_GR (FLD (f_rd), opval);
818 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
819 }
820
821 #undef FLD
822 }
823 NEXT (vpc);
824
825 CASE (sem, INSN_SRAV) : /* srav $rd,$rt,$rs */
826 {
827 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
828 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
829 #define FLD(f) abuf->fields.sfmt_mrgb.f
830 int UNUSED written = 0;
831 IADDR UNUSED pc = abuf->addr;
832 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
833
834 {
835 SI opval = SRASI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31));
836 SET_H_GR (FLD (f_rd), opval);
837 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
838 }
839
840 #undef FLD
841 }
842 NEXT (vpc);
843
844 CASE (sem, INSN_SRL) : /* srl $rd,$rt,$shamt */
845 {
846 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
847 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
848 #define FLD(f) abuf->fields.sfmt_ram.f
849 int UNUSED written = 0;
850 IADDR UNUSED pc = abuf->addr;
851 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
852
853 {
854 SI opval = SRLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt));
855 SET_H_GR (FLD (f_rd), opval);
856 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
857 }
858
859 #undef FLD
860 }
861 NEXT (vpc);
862
863 CASE (sem, INSN_SRLV) : /* srlv $rd,$rt,$rs */
864 {
865 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
866 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
867 #define FLD(f) abuf->fields.sfmt_mrgb.f
868 int UNUSED written = 0;
869 IADDR UNUSED pc = abuf->addr;
870 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
871
872 {
873 SI opval = SRLSI (GET_H_GR (FLD (f_rt)), ANDSI (GET_H_GR (FLD (f_rs)), 31));
874 SET_H_GR (FLD (f_rd), opval);
875 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
876 }
877
878 #undef FLD
879 }
880 NEXT (vpc);
881
882 CASE (sem, INSN_SRMV) : /* srmv $rd,$rt,$rs,$shamt */
883 {
884 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
885 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
886 #define FLD(f) abuf->fields.sfmt_ram.f
887 int UNUSED written = 0;
888 IADDR UNUSED pc = abuf->addr;
889 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
890
891 {
892 SI opval = ANDSI (SRLSI (GET_H_GR (FLD (f_rt)), FLD (f_shamt)), SLLSI (0xffffffff, GET_H_GR (FLD (f_rs))));
893 SET_H_GR (FLD (f_rd), opval);
894 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
895 }
896
897 #undef FLD
898 }
899 NEXT (vpc);
900
901 CASE (sem, INSN_SUB) : /* sub $rd,$rs,$rt */
902 {
903 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
904 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
905 #define FLD(f) abuf->fields.sfmt_mrgb.f
906 int UNUSED written = 0;
907 IADDR UNUSED pc = abuf->addr;
908 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
909
910 {
911 SI opval = SUBSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));
912 SET_H_GR (FLD (f_rd), opval);
913 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
914 }
915
916 #undef FLD
917 }
918 NEXT (vpc);
919
920 CASE (sem, INSN_SUBU) : /* subu $rd,$rs,$rt */
921 {
922 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
923 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
924 #define FLD(f) abuf->fields.sfmt_mrgb.f
925 int UNUSED written = 0;
926 IADDR UNUSED pc = abuf->addr;
927 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
928
929 {
930 SI opval = SUBSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));
931 SET_H_GR (FLD (f_rd), opval);
932 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
933 }
934
935 #undef FLD
936 }
937 NEXT (vpc);
938
939 CASE (sem, INSN_XOR) : /* xor $rd,$rs,$rt */
940 {
941 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
942 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
943 #define FLD(f) abuf->fields.sfmt_mrgb.f
944 int UNUSED written = 0;
945 IADDR UNUSED pc = abuf->addr;
946 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
947
948 {
949 SI opval = XORSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)));
950 SET_H_GR (FLD (f_rd), opval);
951 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
952 }
953
954 #undef FLD
955 }
956 NEXT (vpc);
957
958 CASE (sem, INSN_XORI) : /* xori $rt,$rs,$lo16 */
959 {
960 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
961 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
962 #define FLD(f) abuf->fields.sfmt_addi.f
963 int UNUSED written = 0;
964 IADDR UNUSED pc = abuf->addr;
965 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
966
967 {
968 SI opval = XORSI (GET_H_GR (FLD (f_rs)), ZEXTSISI (FLD (f_imm)));
969 SET_H_GR (FLD (f_rt), opval);
970 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
971 }
972
973 #undef FLD
974 }
975 NEXT (vpc);
976
977 CASE (sem, INSN_BBI) : /* bbi $rs($bitnum),$offset */
978 {
979 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
980 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
981 #define FLD(f) abuf->fields.sfmt_bbi.f
982 int UNUSED written = 0;
983 IADDR UNUSED pc = abuf->addr;
984 SEM_BRANCH_INIT
985 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
986
987 if (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, FLD (f_rt)))) {
988 {
989 {
990 USI opval = FLD (i_offset);
991 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
992 written |= (1 << 3);
993 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
994 }
995 }
996 }
997
998 abuf->written = written;
999 SEM_BRANCH_FINI (vpc);
1000 #undef FLD
1001 }
1002 NEXT (vpc);
1003
1004 CASE (sem, INSN_BBIN) : /* bbin $rs($bitnum),$offset */
1005 {
1006 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1007 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1008 #define FLD(f) abuf->fields.sfmt_bbi.f
1009 int UNUSED written = 0;
1010 IADDR UNUSED pc = abuf->addr;
1011 SEM_BRANCH_INIT
1012 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1013
1014 if (NOTSI (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, FLD (f_rt))))) {
1015 {
1016 {
1017 USI opval = FLD (i_offset);
1018 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1019 written |= (1 << 3);
1020 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1021 }
1022 }
1023 }
1024
1025 abuf->written = written;
1026 SEM_BRANCH_FINI (vpc);
1027 #undef FLD
1028 }
1029 NEXT (vpc);
1030
1031 CASE (sem, INSN_BBV) : /* bbv $rs,$rt,$offset */
1032 {
1033 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1034 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1035 #define FLD(f) abuf->fields.sfmt_bbi.f
1036 int UNUSED written = 0;
1037 IADDR UNUSED pc = abuf->addr;
1038 SEM_BRANCH_INIT
1039 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1040
1041 if (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, ANDSI (GET_H_GR (FLD (f_rt)), 31)))) {
1042 {
1043 {
1044 USI opval = FLD (i_offset);
1045 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1046 written |= (1 << 3);
1047 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1048 }
1049 }
1050 }
1051
1052 abuf->written = written;
1053 SEM_BRANCH_FINI (vpc);
1054 #undef FLD
1055 }
1056 NEXT (vpc);
1057
1058 CASE (sem, INSN_BBVN) : /* bbvn $rs,$rt,$offset */
1059 {
1060 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1061 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1062 #define FLD(f) abuf->fields.sfmt_bbi.f
1063 int UNUSED written = 0;
1064 IADDR UNUSED pc = abuf->addr;
1065 SEM_BRANCH_INIT
1066 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1067
1068 if (NOTSI (ANDSI (GET_H_GR (FLD (f_rs)), SLLSI (1, ANDSI (GET_H_GR (FLD (f_rt)), 31))))) {
1069 {
1070 {
1071 USI opval = FLD (i_offset);
1072 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1073 written |= (1 << 3);
1074 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1075 }
1076 }
1077 }
1078
1079 abuf->written = written;
1080 SEM_BRANCH_FINI (vpc);
1081 #undef FLD
1082 }
1083 NEXT (vpc);
1084
1085 CASE (sem, INSN_BEQ) : /* beq $rs,$rt,$offset */
1086 {
1087 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1088 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1089 #define FLD(f) abuf->fields.sfmt_bbi.f
1090 int UNUSED written = 0;
1091 IADDR UNUSED pc = abuf->addr;
1092 SEM_BRANCH_INIT
1093 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1094
1095 if (EQSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) {
1096 {
1097 {
1098 USI opval = FLD (i_offset);
1099 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1100 written |= (1 << 3);
1101 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1102 }
1103 }
1104 }
1105
1106 abuf->written = written;
1107 SEM_BRANCH_FINI (vpc);
1108 #undef FLD
1109 }
1110 NEXT (vpc);
1111
1112 CASE (sem, INSN_BEQL) : /* beql $rs,$rt,$offset */
1113 {
1114 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1115 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1116 #define FLD(f) abuf->fields.sfmt_bbi.f
1117 int UNUSED written = 0;
1118 IADDR UNUSED pc = abuf->addr;
1119 SEM_BRANCH_INIT
1120 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1121
1122 if (EQSI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) {
1123 {
1124 {
1125 USI opval = FLD (i_offset);
1126 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1127 written |= (1 << 3);
1128 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1129 }
1130 }
1131 } else {
1132 if (1)
1133 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
1134 }
1135
1136 abuf->written = written;
1137 SEM_BRANCH_FINI (vpc);
1138 #undef FLD
1139 }
1140 NEXT (vpc);
1141
1142 CASE (sem, INSN_BGEZ) : /* bgez $rs,$offset */
1143 {
1144 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1145 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1146 #define FLD(f) abuf->fields.sfmt_bbi.f
1147 int UNUSED written = 0;
1148 IADDR UNUSED pc = abuf->addr;
1149 SEM_BRANCH_INIT
1150 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1151
1152 if (GESI (GET_H_GR (FLD (f_rs)), 0)) {
1153 {
1154 {
1155 USI opval = FLD (i_offset);
1156 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1157 written |= (1 << 2);
1158 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1159 }
1160 }
1161 }
1162
1163 abuf->written = written;
1164 SEM_BRANCH_FINI (vpc);
1165 #undef FLD
1166 }
1167 NEXT (vpc);
1168
1169 CASE (sem, INSN_BGEZAL) : /* bgezal $rs,$offset */
1170 {
1171 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1172 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1173 #define FLD(f) abuf->fields.sfmt_bbi.f
1174 int UNUSED written = 0;
1175 IADDR UNUSED pc = abuf->addr;
1176 SEM_BRANCH_INIT
1177 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1178
1179 if (GESI (GET_H_GR (FLD (f_rs)), 0)) {
1180 {
1181 {
1182 SI opval = ADDSI (pc, 8);
1183 SET_H_GR (((UINT) 31), opval);
1184 written |= (1 << 3);
1185 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1186 }
1187 {
1188 {
1189 USI opval = FLD (i_offset);
1190 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1191 written |= (1 << 4);
1192 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1193 }
1194 }
1195 }
1196 }
1197
1198 abuf->written = written;
1199 SEM_BRANCH_FINI (vpc);
1200 #undef FLD
1201 }
1202 NEXT (vpc);
1203
1204 CASE (sem, INSN_BGEZALL) : /* bgezall $rs,$offset */
1205 {
1206 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1207 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1208 #define FLD(f) abuf->fields.sfmt_bbi.f
1209 int UNUSED written = 0;
1210 IADDR UNUSED pc = abuf->addr;
1211 SEM_BRANCH_INIT
1212 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1213
1214 if (GESI (GET_H_GR (FLD (f_rs)), 0)) {
1215 {
1216 {
1217 SI opval = ADDSI (pc, 8);
1218 SET_H_GR (((UINT) 31), opval);
1219 written |= (1 << 3);
1220 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1221 }
1222 {
1223 {
1224 USI opval = FLD (i_offset);
1225 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1226 written |= (1 << 4);
1227 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1228 }
1229 }
1230 }
1231 } else {
1232 if (1)
1233 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
1234 }
1235
1236 abuf->written = written;
1237 SEM_BRANCH_FINI (vpc);
1238 #undef FLD
1239 }
1240 NEXT (vpc);
1241
1242 CASE (sem, INSN_BGEZL) : /* bgezl $rs,$offset */
1243 {
1244 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1245 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1246 #define FLD(f) abuf->fields.sfmt_bbi.f
1247 int UNUSED written = 0;
1248 IADDR UNUSED pc = abuf->addr;
1249 SEM_BRANCH_INIT
1250 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1251
1252 if (GESI (GET_H_GR (FLD (f_rs)), 0)) {
1253 {
1254 {
1255 USI opval = FLD (i_offset);
1256 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1257 written |= (1 << 2);
1258 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1259 }
1260 }
1261 } else {
1262 if (1)
1263 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
1264 }
1265
1266 abuf->written = written;
1267 SEM_BRANCH_FINI (vpc);
1268 #undef FLD
1269 }
1270 NEXT (vpc);
1271
1272 CASE (sem, INSN_BLTZ) : /* bltz $rs,$offset */
1273 {
1274 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1275 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1276 #define FLD(f) abuf->fields.sfmt_bbi.f
1277 int UNUSED written = 0;
1278 IADDR UNUSED pc = abuf->addr;
1279 SEM_BRANCH_INIT
1280 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1281
1282 if (LTSI (GET_H_GR (FLD (f_rs)), 0)) {
1283 {
1284 {
1285 USI opval = FLD (i_offset);
1286 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1287 written |= (1 << 2);
1288 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1289 }
1290 }
1291 }
1292
1293 abuf->written = written;
1294 SEM_BRANCH_FINI (vpc);
1295 #undef FLD
1296 }
1297 NEXT (vpc);
1298
1299 CASE (sem, INSN_BLTZL) : /* bltzl $rs,$offset */
1300 {
1301 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1302 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1303 #define FLD(f) abuf->fields.sfmt_bbi.f
1304 int UNUSED written = 0;
1305 IADDR UNUSED pc = abuf->addr;
1306 SEM_BRANCH_INIT
1307 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1308
1309 if (LTSI (GET_H_GR (FLD (f_rs)), 0)) {
1310 {
1311 {
1312 USI opval = FLD (i_offset);
1313 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1314 written |= (1 << 2);
1315 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1316 }
1317 }
1318 } else {
1319 if (1)
1320 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
1321 }
1322
1323 abuf->written = written;
1324 SEM_BRANCH_FINI (vpc);
1325 #undef FLD
1326 }
1327 NEXT (vpc);
1328
1329 CASE (sem, INSN_BLTZAL) : /* bltzal $rs,$offset */
1330 {
1331 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1332 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1333 #define FLD(f) abuf->fields.sfmt_bbi.f
1334 int UNUSED written = 0;
1335 IADDR UNUSED pc = abuf->addr;
1336 SEM_BRANCH_INIT
1337 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1338
1339 if (LTSI (GET_H_GR (FLD (f_rs)), 0)) {
1340 {
1341 {
1342 SI opval = ADDSI (pc, 8);
1343 SET_H_GR (((UINT) 31), opval);
1344 written |= (1 << 3);
1345 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1346 }
1347 {
1348 {
1349 USI opval = FLD (i_offset);
1350 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1351 written |= (1 << 4);
1352 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1353 }
1354 }
1355 }
1356 }
1357
1358 abuf->written = written;
1359 SEM_BRANCH_FINI (vpc);
1360 #undef FLD
1361 }
1362 NEXT (vpc);
1363
1364 CASE (sem, INSN_BLTZALL) : /* bltzall $rs,$offset */
1365 {
1366 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1367 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1368 #define FLD(f) abuf->fields.sfmt_bbi.f
1369 int UNUSED written = 0;
1370 IADDR UNUSED pc = abuf->addr;
1371 SEM_BRANCH_INIT
1372 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1373
1374 if (LTSI (GET_H_GR (FLD (f_rs)), 0)) {
1375 {
1376 {
1377 SI opval = ADDSI (pc, 8);
1378 SET_H_GR (((UINT) 31), opval);
1379 written |= (1 << 3);
1380 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1381 }
1382 {
1383 {
1384 USI opval = FLD (i_offset);
1385 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1386 written |= (1 << 4);
1387 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1388 }
1389 }
1390 }
1391 } else {
1392 if (1)
1393 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
1394 }
1395
1396 abuf->written = written;
1397 SEM_BRANCH_FINI (vpc);
1398 #undef FLD
1399 }
1400 NEXT (vpc);
1401
1402 CASE (sem, INSN_BMB0) : /* bmb0 $rs,$rt,$offset */
1403 {
1404 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1405 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1406 #define FLD(f) abuf->fields.sfmt_bbi.f
1407 int UNUSED written = 0;
1408 IADDR UNUSED pc = abuf->addr;
1409 SEM_BRANCH_INIT
1410 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1411
1412 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 255), ANDSI (GET_H_GR (FLD (f_rt)), 255))) {
1413 {
1414 {
1415 USI opval = FLD (i_offset);
1416 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1417 written |= (1 << 3);
1418 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1419 }
1420 }
1421 }
1422
1423 abuf->written = written;
1424 SEM_BRANCH_FINI (vpc);
1425 #undef FLD
1426 }
1427 NEXT (vpc);
1428
1429 CASE (sem, INSN_BMB1) : /* bmb1 $rs,$rt,$offset */
1430 {
1431 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1432 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1433 #define FLD(f) abuf->fields.sfmt_bbi.f
1434 int UNUSED written = 0;
1435 IADDR UNUSED pc = abuf->addr;
1436 SEM_BRANCH_INIT
1437 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1438
1439 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 65280), ANDSI (GET_H_GR (FLD (f_rt)), 65280))) {
1440 {
1441 {
1442 USI opval = FLD (i_offset);
1443 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1444 written |= (1 << 3);
1445 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1446 }
1447 }
1448 }
1449
1450 abuf->written = written;
1451 SEM_BRANCH_FINI (vpc);
1452 #undef FLD
1453 }
1454 NEXT (vpc);
1455
1456 CASE (sem, INSN_BMB2) : /* bmb2 $rs,$rt,$offset */
1457 {
1458 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1459 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1460 #define FLD(f) abuf->fields.sfmt_bbi.f
1461 int UNUSED written = 0;
1462 IADDR UNUSED pc = abuf->addr;
1463 SEM_BRANCH_INIT
1464 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1465
1466 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 16711680), ANDSI (GET_H_GR (FLD (f_rt)), 16711680))) {
1467 {
1468 {
1469 USI opval = FLD (i_offset);
1470 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1471 written |= (1 << 3);
1472 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1473 }
1474 }
1475 }
1476
1477 abuf->written = written;
1478 SEM_BRANCH_FINI (vpc);
1479 #undef FLD
1480 }
1481 NEXT (vpc);
1482
1483 CASE (sem, INSN_BMB3) : /* bmb3 $rs,$rt,$offset */
1484 {
1485 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1486 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1487 #define FLD(f) abuf->fields.sfmt_bbi.f
1488 int UNUSED written = 0;
1489 IADDR UNUSED pc = abuf->addr;
1490 SEM_BRANCH_INIT
1491 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1492
1493 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000), ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000))) {
1494 {
1495 {
1496 USI opval = FLD (i_offset);
1497 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1498 written |= (1 << 3);
1499 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1500 }
1501 }
1502 }
1503
1504 abuf->written = written;
1505 SEM_BRANCH_FINI (vpc);
1506 #undef FLD
1507 }
1508 NEXT (vpc);
1509
1510 CASE (sem, INSN_BNE) : /* bne $rs,$rt,$offset */
1511 {
1512 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1513 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1514 #define FLD(f) abuf->fields.sfmt_bbi.f
1515 int UNUSED written = 0;
1516 IADDR UNUSED pc = abuf->addr;
1517 SEM_BRANCH_INIT
1518 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1519
1520 if (NESI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) {
1521 {
1522 {
1523 USI opval = FLD (i_offset);
1524 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1525 written |= (1 << 3);
1526 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1527 }
1528 }
1529 }
1530
1531 abuf->written = written;
1532 SEM_BRANCH_FINI (vpc);
1533 #undef FLD
1534 }
1535 NEXT (vpc);
1536
1537 CASE (sem, INSN_BNEL) : /* bnel $rs,$rt,$offset */
1538 {
1539 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1540 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1541 #define FLD(f) abuf->fields.sfmt_bbi.f
1542 int UNUSED written = 0;
1543 IADDR UNUSED pc = abuf->addr;
1544 SEM_BRANCH_INIT
1545 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1546
1547 if (NESI (GET_H_GR (FLD (f_rs)), GET_H_GR (FLD (f_rt)))) {
1548 {
1549 {
1550 USI opval = FLD (i_offset);
1551 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1552 written |= (1 << 3);
1553 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1554 }
1555 }
1556 } else {
1557 if (1)
1558 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
1559 }
1560
1561 abuf->written = written;
1562 SEM_BRANCH_FINI (vpc);
1563 #undef FLD
1564 }
1565 NEXT (vpc);
1566
1567 CASE (sem, INSN_JALR) : /* jalr $rd,$rs */
1568 {
1569 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1570 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1571 #define FLD(f) abuf->fields.sfmt_mrgb.f
1572 int UNUSED written = 0;
1573 IADDR UNUSED pc = abuf->addr;
1574 SEM_BRANCH_INIT
1575 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1576
1577 {
1578 {
1579 {
1580 SI opval = ADDSI (pc, 8);
1581 SET_H_GR (FLD (f_rd), opval);
1582 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1583 }
1584 {
1585 USI opval = GET_H_GR (FLD (f_rs));
1586 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1587 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1588 }
1589 }
1590 }
1591
1592 SEM_BRANCH_FINI (vpc);
1593 #undef FLD
1594 }
1595 NEXT (vpc);
1596
1597 CASE (sem, INSN_JR) : /* jr $rs */
1598 {
1599 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1600 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1601 #define FLD(f) abuf->fields.sfmt_bbi.f
1602 int UNUSED written = 0;
1603 IADDR UNUSED pc = abuf->addr;
1604 SEM_BRANCH_INIT
1605 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1606
1607 {
1608 {
1609 USI opval = GET_H_GR (FLD (f_rs));
1610 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
1611 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1612 }
1613 }
1614
1615 SEM_BRANCH_FINI (vpc);
1616 #undef FLD
1617 }
1618 NEXT (vpc);
1619
1620 CASE (sem, INSN_LB) : /* lb $rt,$lo16($base) */
1621 {
1622 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1623 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1624 #define FLD(f) abuf->fields.sfmt_addi.f
1625 int UNUSED written = 0;
1626 IADDR UNUSED pc = abuf->addr;
1627 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1628
1629 {
1630 SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
1631 SET_H_GR (FLD (f_rt), opval);
1632 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1633 }
1634
1635 #undef FLD
1636 }
1637 NEXT (vpc);
1638
1639 CASE (sem, INSN_LBU) : /* lbu $rt,$lo16($base) */
1640 {
1641 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1642 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1643 #define FLD(f) abuf->fields.sfmt_addi.f
1644 int UNUSED written = 0;
1645 IADDR UNUSED pc = abuf->addr;
1646 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1647
1648 {
1649 SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
1650 SET_H_GR (FLD (f_rt), opval);
1651 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1652 }
1653
1654 #undef FLD
1655 }
1656 NEXT (vpc);
1657
1658 CASE (sem, INSN_LH) : /* lh $rt,$lo16($base) */
1659 {
1660 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1661 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1662 #define FLD(f) abuf->fields.sfmt_addi.f
1663 int UNUSED written = 0;
1664 IADDR UNUSED pc = abuf->addr;
1665 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1666
1667 {
1668 SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
1669 SET_H_GR (FLD (f_rt), opval);
1670 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1671 }
1672
1673 #undef FLD
1674 }
1675 NEXT (vpc);
1676
1677 CASE (sem, INSN_LHU) : /* lhu $rt,$lo16($base) */
1678 {
1679 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1680 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1681 #define FLD(f) abuf->fields.sfmt_addi.f
1682 int UNUSED written = 0;
1683 IADDR UNUSED pc = abuf->addr;
1684 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1685
1686 {
1687 SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm))))));
1688 SET_H_GR (FLD (f_rt), opval);
1689 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1690 }
1691
1692 #undef FLD
1693 }
1694 NEXT (vpc);
1695
1696 CASE (sem, INSN_LUI) : /* lui $rt,$hi16 */
1697 {
1698 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1699 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1700 #define FLD(f) abuf->fields.sfmt_addi.f
1701 int UNUSED written = 0;
1702 IADDR UNUSED pc = abuf->addr;
1703 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1704
1705 {
1706 SI opval = SLLSI (FLD (f_imm), 16);
1707 SET_H_GR (FLD (f_rt), opval);
1708 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1709 }
1710
1711 #undef FLD
1712 }
1713 NEXT (vpc);
1714
1715 CASE (sem, INSN_LW) : /* lw $rt,$lo16($base) */
1716 {
1717 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1718 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1719 #define FLD(f) abuf->fields.sfmt_addi.f
1720 int UNUSED written = 0;
1721 IADDR UNUSED pc = abuf->addr;
1722 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1723
1724 {
1725 SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))));
1726 SET_H_GR (FLD (f_rt), opval);
1727 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1728 }
1729
1730 #undef FLD
1731 }
1732 NEXT (vpc);
1733
1734 CASE (sem, INSN_SB) : /* sb $rt,$lo16($base) */
1735 {
1736 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1737 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1738 #define FLD(f) abuf->fields.sfmt_addi.f
1739 int UNUSED written = 0;
1740 IADDR UNUSED pc = abuf->addr;
1741 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1742
1743 {
1744 QI opval = ANDQI (GET_H_GR (FLD (f_rt)), 255);
1745 SETMEMQI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1746 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1747 }
1748
1749 #undef FLD
1750 }
1751 NEXT (vpc);
1752
1753 CASE (sem, INSN_SH) : /* sh $rt,$lo16($base) */
1754 {
1755 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1756 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1757 #define FLD(f) abuf->fields.sfmt_addi.f
1758 int UNUSED written = 0;
1759 IADDR UNUSED pc = abuf->addr;
1760 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1761
1762 {
1763 HI opval = ANDHI (GET_H_GR (FLD (f_rt)), 65535);
1764 SETMEMHI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1765 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1766 }
1767
1768 #undef FLD
1769 }
1770 NEXT (vpc);
1771
1772 CASE (sem, INSN_SW) : /* sw $rt,$lo16($base) */
1773 {
1774 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1775 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1776 #define FLD(f) abuf->fields.sfmt_addi.f
1777 int UNUSED written = 0;
1778 IADDR UNUSED pc = abuf->addr;
1779 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1780
1781 {
1782 SI opval = GET_H_GR (FLD (f_rt));
1783 SETMEMSI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_rs)), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval);
1784 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1785 }
1786
1787 #undef FLD
1788 }
1789 NEXT (vpc);
1790
1791 CASE (sem, INSN_BREAK) : /* break */
1792 {
1793 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1794 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1795 #define FLD(f) abuf->fields.sfmt_empty.f
1796 int UNUSED written = 0;
1797 IADDR UNUSED pc = abuf->addr;
1798 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1799
1800 do_break (current_cpu, pc);
1801
1802 #undef FLD
1803 }
1804 NEXT (vpc);
1805
1806 CASE (sem, INSN_SYSCALL) : /* syscall */
1807 {
1808 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1809 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1810 #define FLD(f) abuf->fields.sfmt_empty.f
1811 int UNUSED written = 0;
1812 IADDR UNUSED pc = abuf->addr;
1813 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1814
1815 do_syscall (current_cpu);
1816
1817 #undef FLD
1818 }
1819 NEXT (vpc);
1820
1821 CASE (sem, INSN_ANDOUI) : /* andoui $rt,$rs,$hi16 */
1822 {
1823 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1824 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1825 #define FLD(f) abuf->fields.sfmt_addi.f
1826 int UNUSED written = 0;
1827 IADDR UNUSED pc = abuf->addr;
1828 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1829
1830 {
1831 SI opval = ANDSI (GET_H_GR (FLD (f_rs)), ORSI (SLLSI (FLD (f_imm), 16), 65535));
1832 SET_H_GR (FLD (f_rt), opval);
1833 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1834 }
1835
1836 #undef FLD
1837 }
1838 NEXT (vpc);
1839
1840 CASE (sem, INSN_ORUI) : /* orui $rt,$rs,$hi16 */
1841 {
1842 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1843 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1844 #define FLD(f) abuf->fields.sfmt_addi.f
1845 int UNUSED written = 0;
1846 IADDR UNUSED pc = abuf->addr;
1847 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1848
1849 {
1850 SI opval = ORSI (GET_H_GR (FLD (f_rs)), SLLSI (FLD (f_imm), 16));
1851 SET_H_GR (FLD (f_rt), opval);
1852 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1853 }
1854
1855 #undef FLD
1856 }
1857 NEXT (vpc);
1858
1859 CASE (sem, INSN_BGTZ) : /* bgtz $rs,$offset */
1860 {
1861 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1862 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1863 #define FLD(f) abuf->fields.sfmt_bbi.f
1864 int UNUSED written = 0;
1865 IADDR UNUSED pc = abuf->addr;
1866 SEM_BRANCH_INIT
1867 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1868
1869 if (GTSI (GET_H_GR (FLD (f_rs)), 0)) {
1870 {
1871 {
1872 USI opval = FLD (i_offset);
1873 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1874 written |= (1 << 2);
1875 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1876 }
1877 }
1878 }
1879
1880 abuf->written = written;
1881 SEM_BRANCH_FINI (vpc);
1882 #undef FLD
1883 }
1884 NEXT (vpc);
1885
1886 CASE (sem, INSN_BGTZL) : /* bgtzl $rs,$offset */
1887 {
1888 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1889 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1890 #define FLD(f) abuf->fields.sfmt_bbi.f
1891 int UNUSED written = 0;
1892 IADDR UNUSED pc = abuf->addr;
1893 SEM_BRANCH_INIT
1894 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1895
1896 if (GTSI (GET_H_GR (FLD (f_rs)), 0)) {
1897 {
1898 {
1899 USI opval = FLD (i_offset);
1900 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1901 written |= (1 << 2);
1902 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1903 }
1904 }
1905 } else {
1906 if (1)
1907 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
1908 }
1909
1910 abuf->written = written;
1911 SEM_BRANCH_FINI (vpc);
1912 #undef FLD
1913 }
1914 NEXT (vpc);
1915
1916 CASE (sem, INSN_BLEZ) : /* blez $rs,$offset */
1917 {
1918 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1919 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1920 #define FLD(f) abuf->fields.sfmt_bbi.f
1921 int UNUSED written = 0;
1922 IADDR UNUSED pc = abuf->addr;
1923 SEM_BRANCH_INIT
1924 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1925
1926 if (LESI (GET_H_GR (FLD (f_rs)), 0)) {
1927 {
1928 {
1929 USI opval = FLD (i_offset);
1930 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1931 written |= (1 << 2);
1932 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1933 }
1934 }
1935 }
1936
1937 abuf->written = written;
1938 SEM_BRANCH_FINI (vpc);
1939 #undef FLD
1940 }
1941 NEXT (vpc);
1942
1943 CASE (sem, INSN_BLEZL) : /* blezl $rs,$offset */
1944 {
1945 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1946 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1947 #define FLD(f) abuf->fields.sfmt_bbi.f
1948 int UNUSED written = 0;
1949 IADDR UNUSED pc = abuf->addr;
1950 SEM_BRANCH_INIT
1951 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1952
1953 if (LESI (GET_H_GR (FLD (f_rs)), 0)) {
1954 {
1955 {
1956 USI opval = FLD (i_offset);
1957 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
1958 written |= (1 << 2);
1959 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
1960 }
1961 }
1962 } else {
1963 if (1)
1964 SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
1965 }
1966
1967 abuf->written = written;
1968 SEM_BRANCH_FINI (vpc);
1969 #undef FLD
1970 }
1971 NEXT (vpc);
1972
1973 CASE (sem, INSN_MRGB) : /* mrgb $rd,$rs,$rt,$mask */
1974 {
1975 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1976 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1977 #define FLD(f) abuf->fields.sfmt_mrgb.f
1978 int UNUSED written = 0;
1979 IADDR UNUSED pc = abuf->addr;
1980 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1981
1982 {
1983 SI tmp_temp;
1984 if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 0)))) {
1985 tmp_temp = ANDSI (GET_H_GR (FLD (f_rs)), 255);
1986 } else {
1987 tmp_temp = ANDSI (GET_H_GR (FLD (f_rt)), 255);
1988 }
1989 if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 1)))) {
1990 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 65280));
1991 } else {
1992 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 65280));
1993 }
1994 if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 2)))) {
1995 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 16711680));
1996 } else {
1997 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 16711680));
1998 }
1999 if (NOTSI (ANDSI (FLD (f_mask), SLLSI (1, 3)))) {
2000 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000));
2001 } else {
2002 tmp_temp = ORSI (tmp_temp, ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000));
2003 }
2004 {
2005 SI opval = tmp_temp;
2006 SET_H_GR (FLD (f_rd), opval);
2007 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2008 }
2009 }
2010
2011 #undef FLD
2012 }
2013 NEXT (vpc);
2014
2015 CASE (sem, INSN_BCTXT) : /* bctxt $rs,$offset */
2016 {
2017 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2018 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2019 #define FLD(f) abuf->fields.sfmt_empty.f
2020 int UNUSED written = 0;
2021 IADDR UNUSED pc = abuf->addr;
2022 SEM_BRANCH_INIT
2023 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2024
2025 ((void) 0); /*nop*/
2026
2027 SEM_BRANCH_FINI (vpc);
2028 #undef FLD
2029 }
2030 NEXT (vpc);
2031
2032 CASE (sem, INSN_BC0F) : /* bc0f $offset */
2033 {
2034 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2035 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2036 #define FLD(f) abuf->fields.sfmt_empty.f
2037 int UNUSED written = 0;
2038 IADDR UNUSED pc = abuf->addr;
2039 SEM_BRANCH_INIT
2040 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2041
2042 ((void) 0); /*nop*/
2043
2044 SEM_BRANCH_FINI (vpc);
2045 #undef FLD
2046 }
2047 NEXT (vpc);
2048
2049 CASE (sem, INSN_BC0FL) : /* bc0fl $offset */
2050 {
2051 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2052 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2053 #define FLD(f) abuf->fields.sfmt_empty.f
2054 int UNUSED written = 0;
2055 IADDR UNUSED pc = abuf->addr;
2056 SEM_BRANCH_INIT
2057 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2058
2059 ((void) 0); /*nop*/
2060
2061 SEM_BRANCH_FINI (vpc);
2062 #undef FLD
2063 }
2064 NEXT (vpc);
2065
2066 CASE (sem, INSN_BC3F) : /* bc3f $offset */
2067 {
2068 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2069 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2070 #define FLD(f) abuf->fields.sfmt_empty.f
2071 int UNUSED written = 0;
2072 IADDR UNUSED pc = abuf->addr;
2073 SEM_BRANCH_INIT
2074 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2075
2076 ((void) 0); /*nop*/
2077
2078 SEM_BRANCH_FINI (vpc);
2079 #undef FLD
2080 }
2081 NEXT (vpc);
2082
2083 CASE (sem, INSN_BC3FL) : /* bc3fl $offset */
2084 {
2085 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2086 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2087 #define FLD(f) abuf->fields.sfmt_empty.f
2088 int UNUSED written = 0;
2089 IADDR UNUSED pc = abuf->addr;
2090 SEM_BRANCH_INIT
2091 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2092
2093 ((void) 0); /*nop*/
2094
2095 SEM_BRANCH_FINI (vpc);
2096 #undef FLD
2097 }
2098 NEXT (vpc);
2099
2100 CASE (sem, INSN_BC0T) : /* bc0t $offset */
2101 {
2102 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2103 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2104 #define FLD(f) abuf->fields.sfmt_empty.f
2105 int UNUSED written = 0;
2106 IADDR UNUSED pc = abuf->addr;
2107 SEM_BRANCH_INIT
2108 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2109
2110 ((void) 0); /*nop*/
2111
2112 SEM_BRANCH_FINI (vpc);
2113 #undef FLD
2114 }
2115 NEXT (vpc);
2116
2117 CASE (sem, INSN_BC0TL) : /* bc0tl $offset */
2118 {
2119 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2120 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2121 #define FLD(f) abuf->fields.sfmt_empty.f
2122 int UNUSED written = 0;
2123 IADDR UNUSED pc = abuf->addr;
2124 SEM_BRANCH_INIT
2125 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2126
2127 ((void) 0); /*nop*/
2128
2129 SEM_BRANCH_FINI (vpc);
2130 #undef FLD
2131 }
2132 NEXT (vpc);
2133
2134 CASE (sem, INSN_BC3T) : /* bc3t $offset */
2135 {
2136 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2137 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2138 #define FLD(f) abuf->fields.sfmt_empty.f
2139 int UNUSED written = 0;
2140 IADDR UNUSED pc = abuf->addr;
2141 SEM_BRANCH_INIT
2142 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2143
2144 ((void) 0); /*nop*/
2145
2146 SEM_BRANCH_FINI (vpc);
2147 #undef FLD
2148 }
2149 NEXT (vpc);
2150
2151 CASE (sem, INSN_BC3TL) : /* bc3tl $offset */
2152 {
2153 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2154 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2155 #define FLD(f) abuf->fields.sfmt_empty.f
2156 int UNUSED written = 0;
2157 IADDR UNUSED pc = abuf->addr;
2158 SEM_BRANCH_INIT
2159 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2160
2161 ((void) 0); /*nop*/
2162
2163 SEM_BRANCH_FINI (vpc);
2164 #undef FLD
2165 }
2166 NEXT (vpc);
2167
2168 CASE (sem, INSN_CFC0) : /* cfc0 $rt,$rd */
2169 {
2170 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2171 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2172 #define FLD(f) abuf->fields.sfmt_empty.f
2173 int UNUSED written = 0;
2174 IADDR UNUSED pc = abuf->addr;
2175 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2176
2177 ((void) 0); /*nop*/
2178
2179 #undef FLD
2180 }
2181 NEXT (vpc);
2182
2183 CASE (sem, INSN_CFC1) : /* cfc1 $rt,$rd */
2184 {
2185 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2186 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2187 #define FLD(f) abuf->fields.sfmt_empty.f
2188 int UNUSED written = 0;
2189 IADDR UNUSED pc = abuf->addr;
2190 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2191
2192 ((void) 0); /*nop*/
2193
2194 #undef FLD
2195 }
2196 NEXT (vpc);
2197
2198 CASE (sem, INSN_CFC2) : /* cfc2 $rt,$rd */
2199 {
2200 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2201 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2202 #define FLD(f) abuf->fields.sfmt_empty.f
2203 int UNUSED written = 0;
2204 IADDR UNUSED pc = abuf->addr;
2205 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2206
2207 ((void) 0); /*nop*/
2208
2209 #undef FLD
2210 }
2211 NEXT (vpc);
2212
2213 CASE (sem, INSN_CFC3) : /* cfc3 $rt,$rd */
2214 {
2215 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2216 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2217 #define FLD(f) abuf->fields.sfmt_empty.f
2218 int UNUSED written = 0;
2219 IADDR UNUSED pc = abuf->addr;
2220 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2221
2222 ((void) 0); /*nop*/
2223
2224 #undef FLD
2225 }
2226 NEXT (vpc);
2227
2228 CASE (sem, INSN_CHKHDR) : /* chkhdr $rd,$rt */
2229 {
2230 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2231 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2232 #define FLD(f) abuf->fields.sfmt_empty.f
2233 int UNUSED written = 0;
2234 IADDR UNUSED pc = abuf->addr;
2235 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2236
2237 ((void) 0); /*nop*/
2238
2239 #undef FLD
2240 }
2241 NEXT (vpc);
2242
2243 CASE (sem, INSN_CTC0) : /* ctc0 $rt,$rd */
2244 {
2245 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2246 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2247 #define FLD(f) abuf->fields.sfmt_empty.f
2248 int UNUSED written = 0;
2249 IADDR UNUSED pc = abuf->addr;
2250 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2251
2252 ((void) 0); /*nop*/
2253
2254 #undef FLD
2255 }
2256 NEXT (vpc);
2257
2258 CASE (sem, INSN_CTC1) : /* ctc1 $rt,$rd */
2259 {
2260 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2261 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2262 #define FLD(f) abuf->fields.sfmt_empty.f
2263 int UNUSED written = 0;
2264 IADDR UNUSED pc = abuf->addr;
2265 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2266
2267 ((void) 0); /*nop*/
2268
2269 #undef FLD
2270 }
2271 NEXT (vpc);
2272
2273 CASE (sem, INSN_CTC2) : /* ctc2 $rt,$rd */
2274 {
2275 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2276 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2277 #define FLD(f) abuf->fields.sfmt_empty.f
2278 int UNUSED written = 0;
2279 IADDR UNUSED pc = abuf->addr;
2280 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2281
2282 ((void) 0); /*nop*/
2283
2284 #undef FLD
2285 }
2286 NEXT (vpc);
2287
2288 CASE (sem, INSN_CTC3) : /* ctc3 $rt,$rd */
2289 {
2290 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2291 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2292 #define FLD(f) abuf->fields.sfmt_empty.f
2293 int UNUSED written = 0;
2294 IADDR UNUSED pc = abuf->addr;
2295 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2296
2297 ((void) 0); /*nop*/
2298
2299 #undef FLD
2300 }
2301 NEXT (vpc);
2302
2303 CASE (sem, INSN_JCR) : /* jcr $rs */
2304 {
2305 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2306 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2307 #define FLD(f) abuf->fields.sfmt_empty.f
2308 int UNUSED written = 0;
2309 IADDR UNUSED pc = abuf->addr;
2310 SEM_BRANCH_INIT
2311 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2312
2313 ((void) 0); /*nop*/
2314
2315 SEM_BRANCH_FINI (vpc);
2316 #undef FLD
2317 }
2318 NEXT (vpc);
2319
2320 CASE (sem, INSN_LUC32) : /* luc32 $rt,$rd */
2321 {
2322 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2323 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2324 #define FLD(f) abuf->fields.sfmt_empty.f
2325 int UNUSED written = 0;
2326 IADDR UNUSED pc = abuf->addr;
2327 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2328
2329 ((void) 0); /*nop*/
2330
2331 #undef FLD
2332 }
2333 NEXT (vpc);
2334
2335 CASE (sem, INSN_LUC32L) : /* luc32l $rt,$rd */
2336 {
2337 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2338 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2339 #define FLD(f) abuf->fields.sfmt_empty.f
2340 int UNUSED written = 0;
2341 IADDR UNUSED pc = abuf->addr;
2342 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2343
2344 ((void) 0); /*nop*/
2345
2346 #undef FLD
2347 }
2348 NEXT (vpc);
2349
2350 CASE (sem, INSN_LUC64) : /* luc64 $rt,$rd */
2351 {
2352 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2353 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2354 #define FLD(f) abuf->fields.sfmt_empty.f
2355 int UNUSED written = 0;
2356 IADDR UNUSED pc = abuf->addr;
2357 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2358
2359 ((void) 0); /*nop*/
2360
2361 #undef FLD
2362 }
2363 NEXT (vpc);
2364
2365 CASE (sem, INSN_LUC64L) : /* luc64l $rt,$rd */
2366 {
2367 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2368 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2369 #define FLD(f) abuf->fields.sfmt_empty.f
2370 int UNUSED written = 0;
2371 IADDR UNUSED pc = abuf->addr;
2372 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2373
2374 ((void) 0); /*nop*/
2375
2376 #undef FLD
2377 }
2378 NEXT (vpc);
2379
2380 CASE (sem, INSN_LUK) : /* luk $rt,$rd */
2381 {
2382 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2383 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2384 #define FLD(f) abuf->fields.sfmt_empty.f
2385 int UNUSED written = 0;
2386 IADDR UNUSED pc = abuf->addr;
2387 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2388
2389 ((void) 0); /*nop*/
2390
2391 #undef FLD
2392 }
2393 NEXT (vpc);
2394
2395 CASE (sem, INSN_LULCK) : /* lulck $rt */
2396 {
2397 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2398 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2399 #define FLD(f) abuf->fields.sfmt_empty.f
2400 int UNUSED written = 0;
2401 IADDR UNUSED pc = abuf->addr;
2402 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2403
2404 ((void) 0); /*nop*/
2405
2406 #undef FLD
2407 }
2408 NEXT (vpc);
2409
2410 CASE (sem, INSN_LUM32) : /* lum32 $rt,$rd */
2411 {
2412 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2413 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2414 #define FLD(f) abuf->fields.sfmt_empty.f
2415 int UNUSED written = 0;
2416 IADDR UNUSED pc = abuf->addr;
2417 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2418
2419 ((void) 0); /*nop*/
2420
2421 #undef FLD
2422 }
2423 NEXT (vpc);
2424
2425 CASE (sem, INSN_LUM32L) : /* lum32l $rt,$rd */
2426 {
2427 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2428 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2429 #define FLD(f) abuf->fields.sfmt_empty.f
2430 int UNUSED written = 0;
2431 IADDR UNUSED pc = abuf->addr;
2432 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2433
2434 ((void) 0); /*nop*/
2435
2436 #undef FLD
2437 }
2438 NEXT (vpc);
2439
2440 CASE (sem, INSN_LUM64) : /* lum64 $rt,$rd */
2441 {
2442 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2443 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2444 #define FLD(f) abuf->fields.sfmt_empty.f
2445 int UNUSED written = 0;
2446 IADDR UNUSED pc = abuf->addr;
2447 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2448
2449 ((void) 0); /*nop*/
2450
2451 #undef FLD
2452 }
2453 NEXT (vpc);
2454
2455 CASE (sem, INSN_LUM64L) : /* lum64l $rt,$rd */
2456 {
2457 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2458 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2459 #define FLD(f) abuf->fields.sfmt_empty.f
2460 int UNUSED written = 0;
2461 IADDR UNUSED pc = abuf->addr;
2462 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2463
2464 ((void) 0); /*nop*/
2465
2466 #undef FLD
2467 }
2468 NEXT (vpc);
2469
2470 CASE (sem, INSN_LUR) : /* lur $rt,$rd */
2471 {
2472 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2473 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2474 #define FLD(f) abuf->fields.sfmt_empty.f
2475 int UNUSED written = 0;
2476 IADDR UNUSED pc = abuf->addr;
2477 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2478
2479 ((void) 0); /*nop*/
2480
2481 #undef FLD
2482 }
2483 NEXT (vpc);
2484
2485 CASE (sem, INSN_LURL) : /* lurl $rt,$rd */
2486 {
2487 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2488 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2489 #define FLD(f) abuf->fields.sfmt_empty.f
2490 int UNUSED written = 0;
2491 IADDR UNUSED pc = abuf->addr;
2492 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2493
2494 ((void) 0); /*nop*/
2495
2496 #undef FLD
2497 }
2498 NEXT (vpc);
2499
2500 CASE (sem, INSN_LUULCK) : /* luulck $rt */
2501 {
2502 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2503 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2504 #define FLD(f) abuf->fields.sfmt_empty.f
2505 int UNUSED written = 0;
2506 IADDR UNUSED pc = abuf->addr;
2507 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2508
2509 ((void) 0); /*nop*/
2510
2511 #undef FLD
2512 }
2513 NEXT (vpc);
2514
2515 CASE (sem, INSN_MFC0) : /* mfc0 $rt,$rd */
2516 {
2517 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2518 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2519 #define FLD(f) abuf->fields.sfmt_empty.f
2520 int UNUSED written = 0;
2521 IADDR UNUSED pc = abuf->addr;
2522 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2523
2524 ((void) 0); /*nop*/
2525
2526 #undef FLD
2527 }
2528 NEXT (vpc);
2529
2530 CASE (sem, INSN_MFC1) : /* mfc1 $rt,$rd */
2531 {
2532 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2533 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2534 #define FLD(f) abuf->fields.sfmt_empty.f
2535 int UNUSED written = 0;
2536 IADDR UNUSED pc = abuf->addr;
2537 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2538
2539 ((void) 0); /*nop*/
2540
2541 #undef FLD
2542 }
2543 NEXT (vpc);
2544
2545 CASE (sem, INSN_MFC2) : /* mfc2 $rt,$rd */
2546 {
2547 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2548 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2549 #define FLD(f) abuf->fields.sfmt_empty.f
2550 int UNUSED written = 0;
2551 IADDR UNUSED pc = abuf->addr;
2552 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2553
2554 ((void) 0); /*nop*/
2555
2556 #undef FLD
2557 }
2558 NEXT (vpc);
2559
2560 CASE (sem, INSN_MFC3) : /* mfc3 $rt,$rd */
2561 {
2562 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2563 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2564 #define FLD(f) abuf->fields.sfmt_empty.f
2565 int UNUSED written = 0;
2566 IADDR UNUSED pc = abuf->addr;
2567 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2568
2569 ((void) 0); /*nop*/
2570
2571 #undef FLD
2572 }
2573 NEXT (vpc);
2574
2575 CASE (sem, INSN_MTC0) : /* mtc0 $rt,$rd */
2576 {
2577 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2578 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2579 #define FLD(f) abuf->fields.sfmt_empty.f
2580 int UNUSED written = 0;
2581 IADDR UNUSED pc = abuf->addr;
2582 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2583
2584 ((void) 0); /*nop*/
2585
2586 #undef FLD
2587 }
2588 NEXT (vpc);
2589
2590 CASE (sem, INSN_MTC1) : /* mtc1 $rt,$rd */
2591 {
2592 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2593 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2594 #define FLD(f) abuf->fields.sfmt_empty.f
2595 int UNUSED written = 0;
2596 IADDR UNUSED pc = abuf->addr;
2597 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2598
2599 ((void) 0); /*nop*/
2600
2601 #undef FLD
2602 }
2603 NEXT (vpc);
2604
2605 CASE (sem, INSN_MTC2) : /* mtc2 $rt,$rd */
2606 {
2607 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2608 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2609 #define FLD(f) abuf->fields.sfmt_empty.f
2610 int UNUSED written = 0;
2611 IADDR UNUSED pc = abuf->addr;
2612 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2613
2614 ((void) 0); /*nop*/
2615
2616 #undef FLD
2617 }
2618 NEXT (vpc);
2619
2620 CASE (sem, INSN_MTC3) : /* mtc3 $rt,$rd */
2621 {
2622 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2623 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2624 #define FLD(f) abuf->fields.sfmt_empty.f
2625 int UNUSED written = 0;
2626 IADDR UNUSED pc = abuf->addr;
2627 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2628
2629 ((void) 0); /*nop*/
2630
2631 #undef FLD
2632 }
2633 NEXT (vpc);
2634
2635 CASE (sem, INSN_PKRL) : /* pkrl $rd,$rt */
2636 {
2637 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2638 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2639 #define FLD(f) abuf->fields.sfmt_empty.f
2640 int UNUSED written = 0;
2641 IADDR UNUSED pc = abuf->addr;
2642 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2643
2644 ((void) 0); /*nop*/
2645
2646 #undef FLD
2647 }
2648 NEXT (vpc);
2649
2650 CASE (sem, INSN_PKRLR1) : /* pkrlr1 $rt,$_index,$count */
2651 {
2652 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2653 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2654 #define FLD(f) abuf->fields.sfmt_empty.f
2655 int UNUSED written = 0;
2656 IADDR UNUSED pc = abuf->addr;
2657 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2658
2659 ((void) 0); /*nop*/
2660
2661 #undef FLD
2662 }
2663 NEXT (vpc);
2664
2665 CASE (sem, INSN_PKRLR30) : /* pkrlr30 $rt,$_index,$count */
2666 {
2667 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2668 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2669 #define FLD(f) abuf->fields.sfmt_empty.f
2670 int UNUSED written = 0;
2671 IADDR UNUSED pc = abuf->addr;
2672 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2673
2674 ((void) 0); /*nop*/
2675
2676 #undef FLD
2677 }
2678 NEXT (vpc);
2679
2680 CASE (sem, INSN_RB) : /* rb $rd,$rt */
2681 {
2682 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2683 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2684 #define FLD(f) abuf->fields.sfmt_empty.f
2685 int UNUSED written = 0;
2686 IADDR UNUSED pc = abuf->addr;
2687 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2688
2689 ((void) 0); /*nop*/
2690
2691 #undef FLD
2692 }
2693 NEXT (vpc);
2694
2695 CASE (sem, INSN_RBR1) : /* rbr1 $rt,$_index,$count */
2696 {
2697 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2698 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2699 #define FLD(f) abuf->fields.sfmt_empty.f
2700 int UNUSED written = 0;
2701 IADDR UNUSED pc = abuf->addr;
2702 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2703
2704 ((void) 0); /*nop*/
2705
2706 #undef FLD
2707 }
2708 NEXT (vpc);
2709
2710 CASE (sem, INSN_RBR30) : /* rbr30 $rt,$_index,$count */
2711 {
2712 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2713 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2714 #define FLD(f) abuf->fields.sfmt_empty.f
2715 int UNUSED written = 0;
2716 IADDR UNUSED pc = abuf->addr;
2717 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2718
2719 ((void) 0); /*nop*/
2720
2721 #undef FLD
2722 }
2723 NEXT (vpc);
2724
2725 CASE (sem, INSN_RFE) : /* rfe */
2726 {
2727 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2728 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2729 #define FLD(f) abuf->fields.sfmt_empty.f
2730 int UNUSED written = 0;
2731 IADDR UNUSED pc = abuf->addr;
2732 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2733
2734 ((void) 0); /*nop*/
2735
2736 #undef FLD
2737 }
2738 NEXT (vpc);
2739
2740 CASE (sem, INSN_RX) : /* rx $rd,$rt */
2741 {
2742 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2743 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2744 #define FLD(f) abuf->fields.sfmt_empty.f
2745 int UNUSED written = 0;
2746 IADDR UNUSED pc = abuf->addr;
2747 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2748
2749 ((void) 0); /*nop*/
2750
2751 #undef FLD
2752 }
2753 NEXT (vpc);
2754
2755 CASE (sem, INSN_RXR1) : /* rxr1 $rt,$_index,$count */
2756 {
2757 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2758 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2759 #define FLD(f) abuf->fields.sfmt_empty.f
2760 int UNUSED written = 0;
2761 IADDR UNUSED pc = abuf->addr;
2762 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2763
2764 ((void) 0); /*nop*/
2765
2766 #undef FLD
2767 }
2768 NEXT (vpc);
2769
2770 CASE (sem, INSN_RXR30) : /* rxr30 $rt,$_index,$count */
2771 {
2772 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2773 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2774 #define FLD(f) abuf->fields.sfmt_empty.f
2775 int UNUSED written = 0;
2776 IADDR UNUSED pc = abuf->addr;
2777 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2778
2779 ((void) 0); /*nop*/
2780
2781 #undef FLD
2782 }
2783 NEXT (vpc);
2784
2785 CASE (sem, INSN_SLEEP) : /* sleep */
2786 {
2787 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2788 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2789 #define FLD(f) abuf->fields.sfmt_empty.f
2790 int UNUSED written = 0;
2791 IADDR UNUSED pc = abuf->addr;
2792 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2793
2794 ((void) 0); /*nop*/
2795
2796 #undef FLD
2797 }
2798 NEXT (vpc);
2799
2800 CASE (sem, INSN_SRRD) : /* srrd $rt */
2801 {
2802 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2803 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2804 #define FLD(f) abuf->fields.sfmt_empty.f
2805 int UNUSED written = 0;
2806 IADDR UNUSED pc = abuf->addr;
2807 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2808
2809 ((void) 0); /*nop*/
2810
2811 #undef FLD
2812 }
2813 NEXT (vpc);
2814
2815 CASE (sem, INSN_SRRDL) : /* srrdl $rt */
2816 {
2817 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2818 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2819 #define FLD(f) abuf->fields.sfmt_empty.f
2820 int UNUSED written = 0;
2821 IADDR UNUSED pc = abuf->addr;
2822 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2823
2824 ((void) 0); /*nop*/
2825
2826 #undef FLD
2827 }
2828 NEXT (vpc);
2829
2830 CASE (sem, INSN_SRULCK) : /* srulck $rt */
2831 {
2832 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2833 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2834 #define FLD(f) abuf->fields.sfmt_empty.f
2835 int UNUSED written = 0;
2836 IADDR UNUSED pc = abuf->addr;
2837 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2838
2839 ((void) 0); /*nop*/
2840
2841 #undef FLD
2842 }
2843 NEXT (vpc);
2844
2845 CASE (sem, INSN_SRWR) : /* srwr $rt,$rd */
2846 {
2847 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2848 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2849 #define FLD(f) abuf->fields.sfmt_empty.f
2850 int UNUSED written = 0;
2851 IADDR UNUSED pc = abuf->addr;
2852 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2853
2854 ((void) 0); /*nop*/
2855
2856 #undef FLD
2857 }
2858 NEXT (vpc);
2859
2860 CASE (sem, INSN_SRWRU) : /* srwru $rt,$rd */
2861 {
2862 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2863 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2864 #define FLD(f) abuf->fields.sfmt_empty.f
2865 int UNUSED written = 0;
2866 IADDR UNUSED pc = abuf->addr;
2867 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2868
2869 ((void) 0); /*nop*/
2870
2871 #undef FLD
2872 }
2873 NEXT (vpc);
2874
2875 CASE (sem, INSN_TRAPQFL) : /* trapqfl */
2876 {
2877 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2878 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2879 #define FLD(f) abuf->fields.sfmt_empty.f
2880 int UNUSED written = 0;
2881 IADDR UNUSED pc = abuf->addr;
2882 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2883
2884 ((void) 0); /*nop*/
2885
2886 #undef FLD
2887 }
2888 NEXT (vpc);
2889
2890 CASE (sem, INSN_TRAPQNE) : /* trapqne */
2891 {
2892 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2893 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2894 #define FLD(f) abuf->fields.sfmt_empty.f
2895 int UNUSED written = 0;
2896 IADDR UNUSED pc = abuf->addr;
2897 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2898
2899 ((void) 0); /*nop*/
2900
2901 #undef FLD
2902 }
2903 NEXT (vpc);
2904
2905 CASE (sem, INSN_TRAPREL) : /* traprel $rt */
2906 {
2907 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2908 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2909 #define FLD(f) abuf->fields.sfmt_empty.f
2910 int UNUSED written = 0;
2911 IADDR UNUSED pc = abuf->addr;
2912 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2913
2914 ((void) 0); /*nop*/
2915
2916 #undef FLD
2917 }
2918 NEXT (vpc);
2919
2920 CASE (sem, INSN_WB) : /* wb $rd,$rt */
2921 {
2922 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2923 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2924 #define FLD(f) abuf->fields.sfmt_empty.f
2925 int UNUSED written = 0;
2926 IADDR UNUSED pc = abuf->addr;
2927 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2928
2929 ((void) 0); /*nop*/
2930
2931 #undef FLD
2932 }
2933 NEXT (vpc);
2934
2935 CASE (sem, INSN_WBU) : /* wbu $rd,$rt */
2936 {
2937 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2938 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2939 #define FLD(f) abuf->fields.sfmt_empty.f
2940 int UNUSED written = 0;
2941 IADDR UNUSED pc = abuf->addr;
2942 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2943
2944 ((void) 0); /*nop*/
2945
2946 #undef FLD
2947 }
2948 NEXT (vpc);
2949
2950 CASE (sem, INSN_WBR1) : /* wbr1 $rt,$_index,$count */
2951 {
2952 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2953 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2954 #define FLD(f) abuf->fields.sfmt_empty.f
2955 int UNUSED written = 0;
2956 IADDR UNUSED pc = abuf->addr;
2957 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2958
2959 ((void) 0); /*nop*/
2960
2961 #undef FLD
2962 }
2963 NEXT (vpc);
2964
2965 CASE (sem, INSN_WBR1U) : /* wbr1u $rt,$_index,$count */
2966 {
2967 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2968 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2969 #define FLD(f) abuf->fields.sfmt_empty.f
2970 int UNUSED written = 0;
2971 IADDR UNUSED pc = abuf->addr;
2972 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2973
2974 ((void) 0); /*nop*/
2975
2976 #undef FLD
2977 }
2978 NEXT (vpc);
2979
2980 CASE (sem, INSN_WBR30) : /* wbr30 $rt,$_index,$count */
2981 {
2982 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2983 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2984 #define FLD(f) abuf->fields.sfmt_empty.f
2985 int UNUSED written = 0;
2986 IADDR UNUSED pc = abuf->addr;
2987 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2988
2989 ((void) 0); /*nop*/
2990
2991 #undef FLD
2992 }
2993 NEXT (vpc);
2994
2995 CASE (sem, INSN_WBR30U) : /* wbr30u $rt,$_index,$count */
2996 {
2997 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2998 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2999 #define FLD(f) abuf->fields.sfmt_empty.f
3000 int UNUSED written = 0;
3001 IADDR UNUSED pc = abuf->addr;
3002 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3003
3004 ((void) 0); /*nop*/
3005
3006 #undef FLD
3007 }
3008 NEXT (vpc);
3009
3010 CASE (sem, INSN_WX) : /* wx $rd,$rt */
3011 {
3012 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3013 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3014 #define FLD(f) abuf->fields.sfmt_empty.f
3015 int UNUSED written = 0;
3016 IADDR UNUSED pc = abuf->addr;
3017 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3018
3019 ((void) 0); /*nop*/
3020
3021 #undef FLD
3022 }
3023 NEXT (vpc);
3024
3025 CASE (sem, INSN_WXU) : /* wxu $rd,$rt */
3026 {
3027 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3028 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3029 #define FLD(f) abuf->fields.sfmt_empty.f
3030 int UNUSED written = 0;
3031 IADDR UNUSED pc = abuf->addr;
3032 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3033
3034 ((void) 0); /*nop*/
3035
3036 #undef FLD
3037 }
3038 NEXT (vpc);
3039
3040 CASE (sem, INSN_WXR1) : /* wxr1 $rt,$_index,$count */
3041 {
3042 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3043 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3044 #define FLD(f) abuf->fields.sfmt_empty.f
3045 int UNUSED written = 0;
3046 IADDR UNUSED pc = abuf->addr;
3047 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3048
3049 ((void) 0); /*nop*/
3050
3051 #undef FLD
3052 }
3053 NEXT (vpc);
3054
3055 CASE (sem, INSN_WXR1U) : /* wxr1u $rt,$_index,$count */
3056 {
3057 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3058 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3059 #define FLD(f) abuf->fields.sfmt_empty.f
3060 int UNUSED written = 0;
3061 IADDR UNUSED pc = abuf->addr;
3062 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3063
3064 ((void) 0); /*nop*/
3065
3066 #undef FLD
3067 }
3068 NEXT (vpc);
3069
3070 CASE (sem, INSN_WXR30) : /* wxr30 $rt,$_index,$count */
3071 {
3072 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3073 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3074 #define FLD(f) abuf->fields.sfmt_empty.f
3075 int UNUSED written = 0;
3076 IADDR UNUSED pc = abuf->addr;
3077 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3078
3079 ((void) 0); /*nop*/
3080
3081 #undef FLD
3082 }
3083 NEXT (vpc);
3084
3085 CASE (sem, INSN_WXR30U) : /* wxr30u $rt,$_index,$count */
3086 {
3087 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3088 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3089 #define FLD(f) abuf->fields.sfmt_empty.f
3090 int UNUSED written = 0;
3091 IADDR UNUSED pc = abuf->addr;
3092 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3093
3094 ((void) 0); /*nop*/
3095
3096 #undef FLD
3097 }
3098 NEXT (vpc);
3099
3100 CASE (sem, INSN_LDW) : /* ldw $rt,$lo16($base) */
3101 {
3102 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3103 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3104 #define FLD(f) abuf->fields.sfmt_addi.f
3105 int UNUSED written = 0;
3106 IADDR UNUSED pc = abuf->addr;
3107 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3108
3109 {
3110 SI tmp_addr;
3111 tmp_addr = ANDSI (ADDSI (GET_H_GR (FLD (f_rs)), FLD (f_imm)), INVSI (3));
3112 {
3113 SI opval = GETMEMSI (current_cpu, pc, tmp_addr);
3114 SET_H_GR (ADDSI (FLD (f_rt), 1), opval);
3115 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3116 }
3117 {
3118 SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_addr, 4));
3119 SET_H_GR (FLD (f_rt), opval);
3120 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3121 }
3122 }
3123
3124 #undef FLD
3125 }
3126 NEXT (vpc);
3127
3128 CASE (sem, INSN_SDW) : /* sdw $rt,$lo16($base) */
3129 {
3130 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3131 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3132 #define FLD(f) abuf->fields.sfmt_addi.f
3133 int UNUSED written = 0;
3134 IADDR UNUSED pc = abuf->addr;
3135 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3136
3137 {
3138 SI tmp_addr;
3139 tmp_addr = ANDSI (ADDSI (GET_H_GR (FLD (f_rs)), FLD (f_imm)), INVSI (3));
3140 {
3141 SI opval = GET_H_GR (FLD (f_rt));
3142 SETMEMSI (current_cpu, pc, ADDSI (tmp_addr, 4), opval);
3143 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3144 }
3145 {
3146 SI opval = GET_H_GR (ADDSI (FLD (f_rt), 1));
3147 SETMEMSI (current_cpu, pc, tmp_addr, opval);
3148 CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3149 }
3150 }
3151
3152 #undef FLD
3153 }
3154 NEXT (vpc);
3155
3156 CASE (sem, INSN_J) : /* j $jmptarg */
3157 {
3158 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3159 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3160 #define FLD(f) abuf->fields.sfmt_j.f
3161 int UNUSED written = 0;
3162 IADDR UNUSED pc = abuf->addr;
3163 SEM_BRANCH_INIT
3164 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3165
3166 {
3167 {
3168 USI opval = FLD (i_jmptarg);
3169 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3170 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3171 }
3172 }
3173
3174 SEM_BRANCH_FINI (vpc);
3175 #undef FLD
3176 }
3177 NEXT (vpc);
3178
3179 CASE (sem, INSN_JAL) : /* jal $jmptarg */
3180 {
3181 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3182 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3183 #define FLD(f) abuf->fields.sfmt_j.f
3184 int UNUSED written = 0;
3185 IADDR UNUSED pc = abuf->addr;
3186 SEM_BRANCH_INIT
3187 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3188
3189 {
3190 {
3191 {
3192 SI opval = ADDSI (pc, 8);
3193 SET_H_GR (((UINT) 31), opval);
3194 CGEN_TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3195 }
3196 {
3197 USI opval = FLD (i_jmptarg);
3198 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3199 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3200 }
3201 }
3202 }
3203
3204 SEM_BRANCH_FINI (vpc);
3205 #undef FLD
3206 }
3207 NEXT (vpc);
3208
3209 CASE (sem, INSN_BMB) : /* bmb $rs,$rt,$offset */
3210 {
3211 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3212 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3213 #define FLD(f) abuf->fields.sfmt_bbi.f
3214 int UNUSED written = 0;
3215 IADDR UNUSED pc = abuf->addr;
3216 SEM_BRANCH_INIT
3217 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3218
3219 {
3220 BI tmp_branch_;
3221 tmp_branch_ = 0;
3222 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 255), ANDSI (GET_H_GR (FLD (f_rt)), 255))) {
3223 tmp_branch_ = 1;
3224 }
3225 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 65280), ANDSI (GET_H_GR (FLD (f_rt)), 65280))) {
3226 tmp_branch_ = 1;
3227 }
3228 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 16711680), ANDSI (GET_H_GR (FLD (f_rt)), 16711680))) {
3229 tmp_branch_ = 1;
3230 }
3231 if (EQSI (ANDSI (GET_H_GR (FLD (f_rs)), 0xff000000), ANDSI (GET_H_GR (FLD (f_rt)), 0xff000000))) {
3232 tmp_branch_ = 1;
3233 }
3234 if (tmp_branch_) {
3235 {
3236 {
3237 USI opval = FLD (i_offset);
3238 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3239 written |= (1 << 3);
3240 CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3241 }
3242 }
3243 }
3244 }
3245
3246 abuf->written = written;
3247 SEM_BRANCH_FINI (vpc);
3248 #undef FLD
3249 }
3250 NEXT (vpc);
3251
3252
3253 }
3254 ENDSWITCH (sem) /* End of semantic switch. */
3255
3256 /* At this point `vpc' contains the next insn to execute. */
3257 }
3258
3259 #undef DEFINE_SWITCH
3260 #endif /* DEFINE_SWITCH */
The GNU Binutils are a collection of binary tools.