sim/m68hc11/sim-main.h

   1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   2    Copyright (C) 1999-2019 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@nerim.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef _SIM_MAIN_H
  21 #define _SIM_MAIN_H
  22
  23 #include "sim-basics.h"
  24 #include "sim-signal.h"
  25 #include "sim-base.h"
  26
  27 #include "bfd.h"
  28
  29 #include "opcode/m68hc11.h"
  30
  31 #include "gdb/callback.h"
  32 #include "gdb/remote-sim.h"
  33 #include "opcode/m68hc11.h"
  34 #include "sim-types.h"
  35
  36 typedef unsigned8 uint8;
  37 typedef unsigned16 uint16;
  38 typedef signed16 int16;
  39 typedef unsigned32 uint32;
  40 typedef signed32 int32;
  41 typedef unsigned64 uint64;
  42 typedef signed64 int64;
  43
  44 struct _sim_cpu;
  45
  46 #include "interrupts.h"
  47 #include <setjmp.h>
  48
  49 /* Specifies the level of mapping for the IO, EEprom, nvram and external
  50    RAM.  IO registers are mapped over everything and the external RAM
  51    is last (ie, it can be hidden by everything above it in the list).  */
  52 enum m68hc11_map_level
  53 {
  54   M6811_IO_LEVEL,
  55   M6811_EEPROM_LEVEL,
  56   M6811_NVRAM_LEVEL,
  57   M6811_RAM_LEVEL
  58 };
  59
  60 enum cpu_type
  61 {
  62   CPU_M6811,
  63   CPU_M6812
  64 };
  65
  66 #define X_REGNUM        0
  67 #define D_REGNUM        1
  68 #define Y_REGNUM        2
  69 #define SP_REGNUM       3
  70 #define PC_REGNUM       4
  71 #define A_REGNUM        5
  72 #define B_REGNUM        6
  73 #define PSW_REGNUM      7
  74 #define PAGE_REGNUM     8
  75 #define Z_REGNUM        9
  76
  77 typedef struct m6811_regs {
  78     unsigned short      d;
  79     unsigned short      ix;
  80     unsigned short      iy;
  81     unsigned short      sp;
  82     unsigned short      pc;
  83     unsigned char       ccr;
  84   unsigned short      page;
  85 } m6811_regs;
  86
  87
  88 /* Description of 68HC11 IO registers.  Such description is only provided
  89    for the info command to display the current setting of IO registers
  90    from GDB.  */
  91 struct io_reg_desc
  92 {
  93   int        mask;
  94   const char *short_name;
  95   const char *long_name;
  96 };
  97 typedef struct io_reg_desc io_reg_desc;
  98
  99 extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
 100                                int mode);
 101 extern void print_io_byte (SIM_DESC sd, const char *name,
 102                            io_reg_desc *desc, uint8 val, uint16 addr);
 103 extern void print_io_word (SIM_DESC sd, const char *name,
 104                            io_reg_desc *desc, uint16 val, uint16 addr);
 105
 106
 107 /* List of special 68HC11&68HC12 instructions that are not handled by the
 108    'gencode.c' generator.  These complex instructions are implemented
 109    by 'cpu_special'.  */
 110 enum M6811_Special
 111 {
 112   /* 68HC11 instructions.  */
 113   M6811_DAA,
 114   M6811_EMUL_SYSCALL,
 115   M6811_ILLEGAL,
 116   M6811_RTI,
 117   M6811_STOP,
 118   M6811_SWI,
 119   M6811_TEST,
 120   M6811_WAI,
 121
 122   /* 68HC12 instructions.  */
 123   M6812_BGND,
 124   M6812_CALL,
 125   M6812_CALL_INDIRECT,
 126   M6812_IDIVS,
 127   M6812_EDIV,
 128   M6812_EDIVS,
 129   M6812_EMACS,
 130   M6812_EMUL,
 131   M6812_EMULS,
 132   M6812_ETBL,
 133   M6812_MEM,
 134   M6812_REV,
 135   M6812_REVW,
 136   M6812_RTC,
 137   M6812_RTI,
 138   M6812_WAV
 139 };
 140
 141 #define M6811_MAX_PORTS (0x03f+1)
 142 #define M6812_MAX_PORTS (0x3ff+1)
 143 #define MAX_PORTS       (M6812_MAX_PORTS)
 144
 145 struct _sim_cpu;
 146
 147 typedef void (* cpu_interp) (struct _sim_cpu*);
 148
 149 struct _sim_cpu {
 150   /* CPU registers.  */
 151   struct m6811_regs     cpu_regs;
 152
 153   /* CPU interrupts.  */
 154   struct interrupts     cpu_interrupts;
 155
 156   /* Pointer to the interpretor routine.  */
 157   cpu_interp            cpu_interpretor;
 158
 159   /* Pointer to the architecture currently configured in the simulator.  */
 160   const struct bfd_arch_info  *cpu_configured_arch;
 161
 162   /* CPU absolute cycle time.  The cycle time is updated after
 163      each instruction, by the number of cycles taken by the instruction.
 164      It is cleared only when reset occurs.  */
 165   signed64              cpu_absolute_cycle;
 166
 167   /* Number of cycles to increment after the current instruction.
 168      This is also the number of ticks for the generic event scheduler.  */
 169   uint8                 cpu_current_cycle;
 170   int                   cpu_emul_syscall;
 171   int                   cpu_is_initialized;
 172   int                   cpu_running;
 173   int                   cpu_check_memory;
 174   int                   cpu_stop_on_interrupt;
 175
 176   /* When this is set, start execution of program at address specified
 177      in the ELF header.  This is used for testing some programs that do not
 178      have an interrupt table linked with them.  Programs created during the
 179      GCC validation are like this. A normal 68HC11 does not behave like
 180      this (unless there is some OS or downloadable feature).  */
 181   int                   cpu_use_elf_start;
 182
 183   /* The starting address specified in ELF header.  */
 184   int                   cpu_elf_start;
 185
 186   uint16                cpu_insn_pc;
 187
 188   /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
 189      get the cycle time.  This is used for the timer rate and for the baud
 190      rate generation.  */
 191   unsigned long         cpu_frequency;
 192
 193   /* The mode in which the CPU is configured (MODA and MODB pins).  */
 194   unsigned int          cpu_mode;
 195   const char*           cpu_start_mode;
 196
 197   /* The cpu being configured.  */
 198   enum cpu_type         cpu_type;
 199
 200   /* Initial value of the CONFIG register.  */
 201   uint8                 cpu_config;
 202   uint8                 cpu_use_local_config;
 203
 204   uint8                 ios[MAX_PORTS];
 205
 206   /* Memory bank parameters which describe how the memory bank window
 207      is mapped in memory and how to convert it in virtual address.  */
 208   uint16                bank_start;
 209   uint16                bank_end;
 210   address_word          bank_virtual;
 211   unsigned              bank_shift;
 212
 213
 214   struct hw            *hw_cpu;
 215
 216   /* ... base type ... */
 217   sim_cpu_base base;
 218 };
 219
 220 /* Returns the cpu absolute cycle time (A virtual counter incremented
 221    at each 68HC11 E clock).  */
 222 #define cpu_current_cycle(cpu)    ((cpu)->cpu_absolute_cycle)
 223 #define cpu_add_cycles(cpu, T)    ((cpu)->cpu_current_cycle += (signed64) (T))
 224 #define cpu_is_running(cpu)       ((cpu)->cpu_running)
 225
 226 /* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
 227 #define cpu_get_io_base(cpu) \
 228   (((uint16)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
 229 #define cpu_get_reg_base(cpu) \
 230   (((uint16)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
 231
 232 /* Returns the different CPU registers.  */
 233 #define cpu_get_ccr(cpu)          ((cpu)->cpu_regs.ccr)
 234 #define cpu_get_pc(cpu)           ((cpu)->cpu_regs.pc)
 235 #define cpu_get_d(cpu)            ((cpu)->cpu_regs.d)
 236 #define cpu_get_x(cpu)            ((cpu)->cpu_regs.ix)
 237 #define cpu_get_y(cpu)            ((cpu)->cpu_regs.iy)
 238 #define cpu_get_sp(cpu)           ((cpu)->cpu_regs.sp)
 239 #define cpu_get_a(cpu)            (((cpu)->cpu_regs.d >> 8) & 0x0FF)
 240 #define cpu_get_b(cpu)            ((cpu)->cpu_regs.d & 0x0FF)
 241 #define cpu_get_page(cpu)         ((cpu)->cpu_regs.page)
 242
 243 /* 68HC12 specific and Motorola internal registers.  */
 244 #define cpu_get_tmp3(cpu)         (0)
 245 #define cpu_get_tmp2(cpu)         (0)
 246
 247 #define cpu_set_d(cpu, val)       ((cpu)->cpu_regs.d = (val))
 248 #define cpu_set_x(cpu, val)       ((cpu)->cpu_regs.ix = (val))
 249 #define cpu_set_y(cpu, val)       ((cpu)->cpu_regs.iy = (val))
 250 #define cpu_set_page(cpu, val)    ((cpu)->cpu_regs.page = (val))
 251
 252 /* 68HC12 specific and Motorola internal registers.  */
 253 #define cpu_set_tmp3(cpu, val)    (0)
 254 #define cpu_set_tmp2(cpu, val)    (void) (0)
 255
 256 #if 0
 257 /* This is a function in m68hc11_sim.c to keep track of the frame.  */
 258 #define cpu_set_sp(cpu, val)      ((cpu)->cpu_regs.sp = (val))
 259 #endif
 260
 261 #define cpu_set_pc(cpu, val)      ((cpu)->cpu_regs.pc = (val))
 262
 263 #define cpu_set_a(cpu, val)  \
 264   cpu_set_d(cpu, ((val) << 8) | cpu_get_b (cpu))
 265 #define cpu_set_b(cpu, val)  \
 266   cpu_set_d(cpu, ((cpu_get_a (cpu)) << 8) | ((val) & 0x0FF))
 267
 268 #define cpu_set_ccr(cpu, val)     ((cpu)->cpu_regs.ccr = (val))
 269 #define cpu_get_ccr_H(cpu)        ((cpu_get_ccr (cpu) & M6811_H_BIT) ? 1 : 0)
 270 #define cpu_get_ccr_X(cpu)        ((cpu_get_ccr (cpu) & M6811_X_BIT) ? 1 : 0)
 271 #define cpu_get_ccr_S(cpu)        ((cpu_get_ccr (cpu) & M6811_S_BIT) ? 1 : 0)
 272 #define cpu_get_ccr_N(cpu)        ((cpu_get_ccr (cpu) & M6811_N_BIT) ? 1 : 0)
 273 #define cpu_get_ccr_V(cpu)        ((cpu_get_ccr (cpu) & M6811_V_BIT) ? 1 : 0)
 274 #define cpu_get_ccr_C(cpu)        ((cpu_get_ccr (cpu) & M6811_C_BIT) ? 1 : 0)
 275 #define cpu_get_ccr_Z(cpu)        ((cpu_get_ccr (cpu) & M6811_Z_BIT) ? 1 : 0)
 276 #define cpu_get_ccr_I(cpu)        ((cpu_get_ccr (cpu) & M6811_I_BIT) ? 1 : 0)
 277
 278 #define cpu_set_ccr_flag(S, B, V) \
 279   cpu_set_ccr (S, (cpu_get_ccr (S) & ~(B)) | ((V) ? (B) : 0))
 280
 281 #define cpu_set_ccr_H(cpu, val)   cpu_set_ccr_flag (cpu, M6811_H_BIT, val)
 282 #define cpu_set_ccr_X(cpu, val)   cpu_set_ccr_flag (cpu, M6811_X_BIT, val)
 283 #define cpu_set_ccr_S(cpu, val)   cpu_set_ccr_flag (cpu, M6811_S_BIT, val)
 284 #define cpu_set_ccr_N(cpu, val)   cpu_set_ccr_flag (cpu, M6811_N_BIT, val)
 285 #define cpu_set_ccr_V(cpu, val)   cpu_set_ccr_flag (cpu, M6811_V_BIT, val)
 286 #define cpu_set_ccr_C(cpu, val)   cpu_set_ccr_flag (cpu, M6811_C_BIT, val)
 287 #define cpu_set_ccr_Z(cpu, val)   cpu_set_ccr_flag (cpu, M6811_Z_BIT, val)
 288 #define cpu_set_ccr_I(cpu, val)   cpu_set_ccr_flag (cpu, M6811_I_BIT, val)
 289
 290 extern void cpu_memory_exception (sim_cpu *cpu,
 291                                   SIM_SIGNAL excep,
 292                                   uint16 addr,
 293                                   const char *message);
 294
 295 STATIC_INLINE address_word
 296 phys_to_virt (sim_cpu *cpu, address_word addr)
 297 {
 298   if (addr >= cpu->bank_start && addr < cpu->bank_end)
 299     return ((address_word) (addr - cpu->bank_start)
 300             + (((address_word) cpu->cpu_regs.page) << cpu->bank_shift)
 301             + cpu->bank_virtual);
 302   else
 303     return (address_word) (addr);
 304 }
 305
 306 STATIC_INLINE uint8
 307 memory_read8 (sim_cpu *cpu, uint16 addr)
 308 {
 309   uint8 val;
 310
 311   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 312     {
 313       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 314                             "Read error");
 315     }
 316   return val;
 317 }
 318
 319 STATIC_INLINE void
 320 memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
 321 {
 322   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 323     {
 324       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 325                             "Write error");
 326     }
 327 }
 328
 329 STATIC_INLINE uint16
 330 memory_read16 (sim_cpu *cpu, uint16 addr)
 331 {
 332   uint8 b[2];
 333
 334   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 335     {
 336       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 337                             "Read error");
 338     }
 339   return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
 340 }
 341
 342 STATIC_INLINE void
 343 memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
 344 {
 345   uint8 b[2];
 346
 347   b[0] = val >> 8;
 348   b[1] = val;
 349   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 350     {
 351       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 352                             "Write error");
 353     }
 354 }
 355 extern void
 356 cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val);
 357
 358 STATIC_INLINE void
 359 cpu_ccr_update_tst16 (sim_cpu *cpu, uint16 val)
 360 {
 361   cpu_set_ccr_V (cpu, 0);
 362   cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
 363   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 364 }
 365
 366 STATIC_INLINE void
 367 cpu_ccr_update_shift8 (sim_cpu *cpu, uint8 val)
 368 {
 369   cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
 370   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 371   cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
 372 }
 373
 374 STATIC_INLINE void
 375 cpu_ccr_update_shift16 (sim_cpu *cpu, uint16 val)
 376 {
 377   cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
 378   cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 379   cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
 380 }
 381
 382 STATIC_INLINE void
 383 cpu_ccr_update_add8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
 384 {
 385   cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
 386   cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
 387   cpu_set_ccr_Z (cpu, r == 0);
 388   cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
 389 }
 390
 391
 392 STATIC_INLINE void
 393 cpu_ccr_update_sub8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
 394 {
 395   cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
 396   cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
 397   cpu_set_ccr_Z (cpu, r == 0);
 398   cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
 399 }
 400
 401 STATIC_INLINE void
 402 cpu_ccr_update_add16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
 403 {
 404   cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
 405   cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
 406   cpu_set_ccr_Z (cpu, r == 0);
 407   cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
 408 }
 409
 410 STATIC_INLINE void
 411 cpu_ccr_update_sub16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
 412 {
 413   cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
 414   cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
 415   cpu_set_ccr_Z (cpu, r == 0);
 416   cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
 417 }
 418
 419 /* Push and pop instructions for 68HC11 (next-available stack mode).  */
 420 STATIC_INLINE void
 421 cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8 val)
 422 {
 423   uint16 addr = cpu->cpu_regs.sp;
 424
 425   memory_write8 (cpu, addr, val);
 426   cpu->cpu_regs.sp = addr - 1;
 427 }
 428
 429 STATIC_INLINE void
 430 cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16 val)
 431 {
 432   uint16 addr = cpu->cpu_regs.sp - 1;
 433
 434   memory_write16 (cpu, addr, val);
 435   cpu->cpu_regs.sp = addr - 1;
 436 }
 437
 438 STATIC_INLINE uint8
 439 cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
 440 {
 441   uint16 addr = cpu->cpu_regs.sp;
 442   uint8 val;
 443
 444   val = memory_read8 (cpu, addr + 1);
 445   cpu->cpu_regs.sp = addr + 1;
 446   return val;
 447 }
 448
 449 STATIC_INLINE uint16
 450 cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
 451 {
 452   uint16 addr = cpu->cpu_regs.sp;
 453   uint16 val;
 454
 455   val = memory_read16 (cpu, addr + 1);
 456   cpu->cpu_regs.sp = addr + 2;
 457   return val;
 458 }
 459
 460 /* Push and pop instructions for 68HC12 (last-used stack mode).  */
 461 STATIC_INLINE void
 462 cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8 val)
 463 {
 464   uint16 addr = cpu->cpu_regs.sp;
 465
 466   addr --;
 467   memory_write8 (cpu, addr, val);
 468   cpu->cpu_regs.sp = addr;
 469 }
 470
 471 STATIC_INLINE void
 472 cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16 val)
 473 {
 474   uint16 addr = cpu->cpu_regs.sp;
 475
 476   addr -= 2;
 477   memory_write16 (cpu, addr, val);
 478   cpu->cpu_regs.sp = addr;
 479 }
 480
 481 STATIC_INLINE uint8
 482 cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
 483 {
 484   uint16 addr = cpu->cpu_regs.sp;
 485   uint8 val;
 486
 487   val = memory_read8 (cpu, addr);
 488   cpu->cpu_regs.sp = addr + 1;
 489   return val;
 490 }
 491
 492 STATIC_INLINE uint16
 493 cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
 494 {
 495   uint16 addr = cpu->cpu_regs.sp;
 496   uint16 val;
 497
 498   val = memory_read16 (cpu, addr);
 499   cpu->cpu_regs.sp = addr + 2;
 500   return val;
 501 }
 502
 503 /* Fetch a 8/16 bit value and update the PC.  */
 504 STATIC_INLINE uint8
 505 cpu_fetch8 (sim_cpu *cpu)
 506 {
 507   uint16 addr = cpu->cpu_regs.pc;
 508   uint8 val;
 509
 510   val = memory_read8 (cpu, addr);
 511   cpu->cpu_regs.pc = addr + 1;
 512   return val;
 513 }
 514
 515 STATIC_INLINE uint16
 516 cpu_fetch16 (sim_cpu *cpu)
 517 {
 518   uint16 addr = cpu->cpu_regs.pc;
 519   uint16 val;
 520
 521   val = memory_read16 (cpu, addr);
 522   cpu->cpu_regs.pc = addr + 2;
 523   return val;
 524 }
 525
 526 extern void cpu_call (sim_cpu *cpu, uint16 addr);
 527 extern void cpu_exg (sim_cpu *cpu, uint8 code);
 528 extern void cpu_dbcc (sim_cpu *cpu);
 529 extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
 530 extern void cpu_move8 (sim_cpu *cpu, uint8 op);
 531 extern void cpu_move16 (sim_cpu *cpu, uint8 op);
 532
 533 extern uint16 cpu_fetch_relbranch (sim_cpu *cpu);
 534 extern uint16 cpu_fetch_relbranch16 (sim_cpu *cpu);
 535 extern void cpu_push_all (sim_cpu *cpu);
 536 extern void cpu_single_step (sim_cpu *cpu);
 537
 538 extern void cpu_info (SIM_DESC sd, sim_cpu *cpu);
 539
 540 extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
 541
 542 /* Returns the address of a 68HC12 indexed operand.
 543    Pre and post modifications are handled on the source register.  */
 544 extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
 545
 546 extern void cpu_return (sim_cpu *cpu);
 547 extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
 548 extern int cpu_reset (sim_cpu *cpu);
 549 extern int cpu_restart (sim_cpu *cpu);
 550 extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
 551                               uint16 addr, const char *message, ...);
 552 extern void emul_os (int op, sim_cpu *cpu);
 553 extern void cpu_interp_m6811 (sim_cpu *cpu);
 554 extern void cpu_interp_m6812 (sim_cpu *cpu);
 555
 556 extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
 557                                       double ton, double toff,
 558                                       signed64 repeat);
 559 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
 560 extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
 561                                  unsigned addr, uint8 val);
 562
 563 /* The current state of the processor; registers, memory, etc.  */
 564
 565 struct sim_state {
 566   sim_cpu        *cpu[MAX_NR_PROCESSORS];
 567   sim_state_base base;
 568 };
 569
 570 extern void sim_board_reset (SIM_DESC sd);
 571
 572 #define PRINT_TIME  0x01
 573 #define PRINT_CYCLE 0x02
 574 extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);
 575
 576 #endif
 577
 578