?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Document the GDB 10.2 release in gdb/ChangeLog
[binutils-gdb.git] / gdb / i387-tdep.c
blobc17c0f30b1e6ab0a26278b5834a158903f0845d8
1 /* Intel 387 floating point stuff.
2
3 Copyright (C) 1988-2021 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #include "defs.h"
21 #include "frame.h"
22 #include "gdbcore.h"
23 #include "inferior.h"
24 #include "language.h"
25 #include "regcache.h"
26 #include "target-float.h"
27 #include "value.h"
28
29 #include "i386-tdep.h"
30 #include "i387-tdep.h"
31 #include "gdbsupport/x86-xstate.h"
32
33 /* Print the floating point number specified by RAW. */
34
35 static void
36 print_i387_value (struct gdbarch *gdbarch,
37 const gdb_byte *raw, struct ui_file *file)
38 {
39 /* We try to print 19 digits. The last digit may or may not contain
40 garbage, but we'd better print one too many. We need enough room
41 to print the value, 1 position for the sign, 1 for the decimal
42 point, 19 for the digits and 6 for the exponent adds up to 27. */
43 const struct type *type = i387_ext_type (gdbarch);
44 std::string str = target_float_to_string (raw, type, " %-+27.19g");
45 fprintf_filtered (file, "%s", str.c_str ());
46 }
47
48 /* Print the classification for the register contents RAW. */
49
50 static void
51 print_i387_ext (struct gdbarch *gdbarch,
52 const gdb_byte *raw, struct ui_file *file)
53 {
54 int sign;
55 int integer;
56 unsigned int exponent;
57 unsigned long fraction[2];
58
59 sign = raw[9] & 0x80;
60 integer = raw[7] & 0x80;
61 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
62 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
63 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
64 | (raw[5] << 8) | raw[4]);
65
66 if (exponent == 0x7fff && integer)
67 {
68 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
69 /* Infinity. */
70 fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
71 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
72 /* Real Indefinite (QNaN). */
73 fputs_unfiltered (" Real Indefinite (QNaN)", file);
74 else if (fraction[1] & 0x40000000)
75 /* QNaN. */
76 fputs_filtered (" QNaN", file);
77 else
78 /* SNaN. */
79 fputs_filtered (" SNaN", file);
80 }
81 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
82 /* Normal. */
83 print_i387_value (gdbarch, raw, file);
84 else if (exponent == 0x0000)
85 {
86 /* Denormal or zero. */
87 print_i387_value (gdbarch, raw, file);
88
89 if (integer)
90 /* Pseudo-denormal. */
91 fputs_filtered (" Pseudo-denormal", file);
92 else if (fraction[0] || fraction[1])
93 /* Denormal. */
94 fputs_filtered (" Denormal", file);
95 }
96 else
97 /* Unsupported. */
98 fputs_filtered (" Unsupported", file);
99 }
100
101 /* Print the status word STATUS. If STATUS_P is false, then STATUS
102 was unavailable. */
103
104 static void
105 print_i387_status_word (int status_p,
106 unsigned int status, struct ui_file *file)
107 {
108 fprintf_filtered (file, "Status Word: ");
109 if (!status_p)
110 {
111 fprintf_filtered (file, "%s\n", _("<unavailable>"));
112 return;
113 }
114
115 fprintf_filtered (file, "%s", hex_string_custom (status, 4));
116 fputs_filtered (" ", file);
117 fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
118 fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
119 fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
120 fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
121 fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
122 fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
123 fputs_filtered (" ", file);
124 fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
125 fputs_filtered (" ", file);
126 fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
127 fputs_filtered (" ", file);
128 fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
129 fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
130 fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
131 fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
132
133 fputs_filtered ("\n", file);
134
135 fprintf_filtered (file,
136 " TOP: %d\n", ((status >> 11) & 7));
137 }
138
139 /* Print the control word CONTROL. If CONTROL_P is false, then
140 CONTROL was unavailable. */
141
142 static void
143 print_i387_control_word (int control_p,
144 unsigned int control, struct ui_file *file)
145 {
146 fprintf_filtered (file, "Control Word: ");
147 if (!control_p)
148 {
149 fprintf_filtered (file, "%s\n", _("<unavailable>"));
150 return;
151 }
152
153 fprintf_filtered (file, "%s", hex_string_custom (control, 4));
154 fputs_filtered (" ", file);
155 fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
156 fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
157 fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
158 fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
159 fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
160 fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
161
162 fputs_filtered ("\n", file);
163
164 fputs_filtered (" PC: ", file);
165 switch ((control >> 8) & 3)
166 {
167 case 0:
168 fputs_filtered ("Single Precision (24-bits)\n", file);
169 break;
170 case 1:
171 fputs_filtered ("Reserved\n", file);
172 break;
173 case 2:
174 fputs_filtered ("Double Precision (53-bits)\n", file);
175 break;
176 case 3:
177 fputs_filtered ("Extended Precision (64-bits)\n", file);
178 break;
179 }
180
181 fputs_filtered (" RC: ", file);
182 switch ((control >> 10) & 3)
183 {
184 case 0:
185 fputs_filtered ("Round to nearest\n", file);
186 break;
187 case 1:
188 fputs_filtered ("Round down\n", file);
189 break;
190 case 2:
191 fputs_filtered ("Round up\n", file);
192 break;
193 case 3:
194 fputs_filtered ("Round toward zero\n", file);
195 break;
196 }
197 }
198
199 /* Print out the i387 floating point state. Note that we ignore FRAME
200 in the code below. That's OK since floating-point registers are
201 never saved on the stack. */
202
203 void
204 i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
205 struct frame_info *frame, const char *args)
206 {
207 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
208 ULONGEST fctrl;
209 int fctrl_p;
210 ULONGEST fstat;
211 int fstat_p;
212 ULONGEST ftag;
213 int ftag_p;
214 ULONGEST fiseg;
215 int fiseg_p;
216 ULONGEST fioff;
217 int fioff_p;
218 ULONGEST foseg;
219 int foseg_p;
220 ULONGEST fooff;
221 int fooff_p;
222 ULONGEST fop;
223 int fop_p;
224 int fpreg;
225 int top;
226
227 gdb_assert (gdbarch == get_frame_arch (frame));
228
229 fctrl_p = read_frame_register_unsigned (frame,
230 I387_FCTRL_REGNUM (tdep), &fctrl);
231 fstat_p = read_frame_register_unsigned (frame,
232 I387_FSTAT_REGNUM (tdep), &fstat);
233 ftag_p = read_frame_register_unsigned (frame,
234 I387_FTAG_REGNUM (tdep), &ftag);
235 fiseg_p = read_frame_register_unsigned (frame,
236 I387_FISEG_REGNUM (tdep), &fiseg);
237 fioff_p = read_frame_register_unsigned (frame,
238 I387_FIOFF_REGNUM (tdep), &fioff);
239 foseg_p = read_frame_register_unsigned (frame,
240 I387_FOSEG_REGNUM (tdep), &foseg);
241 fooff_p = read_frame_register_unsigned (frame,
242 I387_FOOFF_REGNUM (tdep), &fooff);
243 fop_p = read_frame_register_unsigned (frame,
244 I387_FOP_REGNUM (tdep), &fop);
245
246 if (fstat_p)
247 {
248 top = ((fstat >> 11) & 7);
249
250 for (fpreg = 7; fpreg >= 0; fpreg--)
251 {
252 struct value *regval;
253 int regnum;
254 int i;
255 int tag = -1;
256
257 fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
258
259 if (ftag_p)
260 {
261 tag = (ftag >> (fpreg * 2)) & 3;
262
263 switch (tag)
264 {
265 case 0:
266 fputs_filtered ("Valid ", file);
267 break;
268 case 1:
269 fputs_filtered ("Zero ", file);
270 break;
271 case 2:
272 fputs_filtered ("Special ", file);
273 break;
274 case 3:
275 fputs_filtered ("Empty ", file);
276 break;
277 }
278 }
279 else
280 fputs_filtered ("Unknown ", file);
281
282 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
283 regval = get_frame_register_value (frame, regnum);
284
285 if (value_entirely_available (regval))
286 {
287 const gdb_byte *raw = value_contents (regval);
288
289 fputs_filtered ("0x", file);
290 for (i = 9; i >= 0; i--)
291 fprintf_filtered (file, "%02x", raw[i]);
292
293 if (tag != -1 && tag != 3)
294 print_i387_ext (gdbarch, raw, file);
295 }
296 else
297 fprintf_filtered (file, "%s", _("<unavailable>"));
298
299 fputs_filtered ("\n", file);
300 }
301 }
302
303 fputs_filtered ("\n", file);
304 print_i387_status_word (fstat_p, fstat, file);
305 print_i387_control_word (fctrl_p, fctrl, file);
306 fprintf_filtered (file, "Tag Word: %s\n",
307 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
308 fprintf_filtered (file, "Instruction Pointer: %s:",
309 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
310 fprintf_filtered (file, "%s\n",
311 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
312 fprintf_filtered (file, "Operand Pointer: %s:",
313 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
314 fprintf_filtered (file, "%s\n",
315 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
316 fprintf_filtered (file, "Opcode: %s\n",
317 fop_p
318 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
319 : _("<unavailable>"));
320 }
321 \f
322
323 /* Return nonzero if a value of type TYPE stored in register REGNUM
324 needs any special handling. */
325
326 int
327 i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
328 struct type *type)
329 {
330 if (i386_fp_regnum_p (gdbarch, regnum))
331 {
332 /* Floating point registers must be converted unless we are
333 accessing them in their hardware type or TYPE is not float. */
334 if (type == i387_ext_type (gdbarch)
335 || type->code () != TYPE_CODE_FLT)
336 return 0;
337 else
338 return 1;
339 }
340
341 return 0;
342 }
343
344 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
345 return its contents in TO. */
346
347 int
348 i387_register_to_value (struct frame_info *frame, int regnum,
349 struct type *type, gdb_byte *to,
350 int *optimizedp, int *unavailablep)
351 {
352 struct gdbarch *gdbarch = get_frame_arch (frame);
353 gdb_byte from[I386_MAX_REGISTER_SIZE];
354
355 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
356
357 /* We only support floating-point values. */
358 if (type->code () != TYPE_CODE_FLT)
359 {
360 warning (_("Cannot convert floating-point register value "
361 "to non-floating-point type."));
362 *optimizedp = *unavailablep = 0;
363 return 0;
364 }
365
366 /* Convert to TYPE. */
367 if (!get_frame_register_bytes (frame, regnum, 0,
368 gdb::make_array_view (from,
369 register_size (gdbarch,
370 regnum)),
371 optimizedp, unavailablep))
372 return 0;
373
374 target_float_convert (from, i387_ext_type (gdbarch), to, type);
375 *optimizedp = *unavailablep = 0;
376 return 1;
377 }
378
379 /* Write the contents FROM of a value of type TYPE into register
380 REGNUM in frame FRAME. */
381
382 void
383 i387_value_to_register (struct frame_info *frame, int regnum,
384 struct type *type, const gdb_byte *from)
385 {
386 struct gdbarch *gdbarch = get_frame_arch (frame);
387 gdb_byte to[I386_MAX_REGISTER_SIZE];
388
389 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
390
391 /* We only support floating-point values. */
392 if (type->code () != TYPE_CODE_FLT)
393 {
394 warning (_("Cannot convert non-floating-point type "
395 "to floating-point register value."));
396 return;
397 }
398
399 /* Convert from TYPE. */
400 target_float_convert (from, type, to, i387_ext_type (gdbarch));
401 put_frame_register (frame, regnum, to);
402 }
403 \f
404
405 /* Handle FSAVE and FXSAVE formats. */
406
407 /* At fsave_offset[REGNUM] you'll find the offset to the location in
408 the data structure used by the "fsave" instruction where GDB
409 register REGNUM is stored. */
410
411 static int fsave_offset[] =
412 {
413 28 + 0 * 10, /* %st(0) ... */
414 28 + 1 * 10,
415 28 + 2 * 10,
416 28 + 3 * 10,
417 28 + 4 * 10,
418 28 + 5 * 10,
419 28 + 6 * 10,
420 28 + 7 * 10, /* ... %st(7). */
421 0, /* `fctrl' (16 bits). */
422 4, /* `fstat' (16 bits). */
423 8, /* `ftag' (16 bits). */
424 16, /* `fiseg' (16 bits). */
425 12, /* `fioff'. */
426 24, /* `foseg' (16 bits). */
427 20, /* `fooff'. */
428 18 /* `fop' (bottom 11 bits). */
429 };
430
431 #define FSAVE_ADDR(tdep, fsave, regnum) \
432 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
433 \f
434
435 /* Fill register REGNUM in REGCACHE with the appropriate value from
436 *FSAVE. This function masks off any of the reserved bits in
437 *FSAVE. */
438
439 void
440 i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
441 {
442 struct gdbarch *gdbarch = regcache->arch ();
443 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
444 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
445 const gdb_byte *regs = (const gdb_byte *) fsave;
446 int i;
447
448 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
449
450 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
451 if (regnum == -1 || regnum == i)
452 {
453 if (fsave == NULL)
454 {
455 regcache->raw_supply (i, NULL);
456 continue;
457 }
458
459 /* Most of the FPU control registers occupy only 16 bits in the
460 fsave area. Give those a special treatment. */
461 if (i >= I387_FCTRL_REGNUM (tdep)
462 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
463 {
464 gdb_byte val[4];
465
466 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
467 val[2] = val[3] = 0;
468 if (i == I387_FOP_REGNUM (tdep))
469 val[1] &= ((1 << 3) - 1);
470 regcache->raw_supply (i, val);
471 }
472 else
473 regcache->raw_supply (i, FSAVE_ADDR (tdep, regs, i));
474 }
475
476 /* Provide dummy values for the SSE registers. */
477 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
478 if (regnum == -1 || regnum == i)
479 regcache->raw_supply (i, NULL);
480 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
481 {
482 gdb_byte buf[4];
483
484 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL);
485 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf);
486 }
487 }
488
489 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
490 with the value from REGCACHE. If REGNUM is -1, do this for all
491 registers. This function doesn't touch any of the reserved bits in
492 *FSAVE. */
493
494 void
495 i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
496 {
497 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
498 gdb_byte *regs = (gdb_byte *) fsave;
499 int i;
500
501 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
502
503 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
504 if (regnum == -1 || regnum == i)
505 {
506 /* Most of the FPU control registers occupy only 16 bits in
507 the fsave area. Give those a special treatment. */
508 if (i >= I387_FCTRL_REGNUM (tdep)
509 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
510 {
511 gdb_byte buf[4];
512
513 regcache->raw_collect (i, buf);
514
515 if (i == I387_FOP_REGNUM (tdep))
516 {
517 /* The opcode occupies only 11 bits. Make sure we
518 don't touch the other bits. */
519 buf[1] &= ((1 << 3) - 1);
520 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
521 }
522 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
523 }
524 else
525 regcache->raw_collect (i, FSAVE_ADDR (tdep, regs, i));
526 }
527 }
528 \f
529
530 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
531 the data structure used by the "fxsave" instruction where GDB
532 register REGNUM is stored. */
533
534 static int fxsave_offset[] =
535 {
536 32, /* %st(0) through ... */
537 48,
538 64,
539 80,
540 96,
541 112,
542 128,
543 144, /* ... %st(7) (80 bits each). */
544 0, /* `fctrl' (16 bits). */
545 2, /* `fstat' (16 bits). */
546 4, /* `ftag' (16 bits). */
547 12, /* `fiseg' (16 bits). */
548 8, /* `fioff'. */
549 20, /* `foseg' (16 bits). */
550 16, /* `fooff'. */
551 6, /* `fop' (bottom 11 bits). */
552 160 + 0 * 16, /* %xmm0 through ... */
553 160 + 1 * 16,
554 160 + 2 * 16,
555 160 + 3 * 16,
556 160 + 4 * 16,
557 160 + 5 * 16,
558 160 + 6 * 16,
559 160 + 7 * 16,
560 160 + 8 * 16,
561 160 + 9 * 16,
562 160 + 10 * 16,
563 160 + 11 * 16,
564 160 + 12 * 16,
565 160 + 13 * 16,
566 160 + 14 * 16,
567 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
568 };
569
570 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
571 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
572
573 /* We made an unfortunate choice in putting %mxcsr after the SSE
574 registers %xmm0-%xmm7 instead of before, since it makes supporting
575 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
576 don't include the offset for %mxcsr here above. */
577
578 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
579
580 static int i387_tag (const gdb_byte *raw);
581 \f
582
583 /* Fill register REGNUM in REGCACHE with the appropriate
584 floating-point or SSE register value from *FXSAVE. This function
585 masks off any of the reserved bits in *FXSAVE. */
586
587 void
588 i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
589 {
590 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
591 const gdb_byte *regs = (const gdb_byte *) fxsave;
592 int i;
593
594 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
595 gdb_assert (tdep->num_xmm_regs > 0);
596
597 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
598 if (regnum == -1 || regnum == i)
599 {
600 if (regs == NULL)
601 {
602 regcache->raw_supply (i, NULL);
603 continue;
604 }
605
606 /* Most of the FPU control registers occupy only 16 bits in
607 the fxsave area. Give those a special treatment. */
608 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
609 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
610 {
611 gdb_byte val[4];
612
613 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
614 val[2] = val[3] = 0;
615 if (i == I387_FOP_REGNUM (tdep))
616 val[1] &= ((1 << 3) - 1);
617 else if (i== I387_FTAG_REGNUM (tdep))
618 {
619 /* The fxsave area contains a simplified version of
620 the tag word. We have to look at the actual 80-bit
621 FP data to recreate the traditional i387 tag word. */
622
623 unsigned long ftag = 0;
624 int fpreg;
625 int top;
626
627 top = ((FXSAVE_ADDR (tdep, regs,
628 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
629 top &= 0x7;
630
631 for (fpreg = 7; fpreg >= 0; fpreg--)
632 {
633 int tag;
634
635 if (val[0] & (1 << fpreg))
636 {
637 int thisreg = (fpreg + 8 - top) % 8
638 + I387_ST0_REGNUM (tdep);
639 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
640 }
641 else
642 tag = 3; /* Empty */
643
644 ftag |= tag << (2 * fpreg);
645 }
646 val[0] = ftag & 0xff;
647 val[1] = (ftag >> 8) & 0xff;
648 }
649 regcache->raw_supply (i, val);
650 }
651 else
652 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
653 }
654
655 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
656 {
657 if (regs == NULL)
658 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), NULL);
659 else
660 regcache->raw_supply (I387_MXCSR_REGNUM (tdep),
661 FXSAVE_MXCSR_ADDR (regs));
662 }
663 }
664
665 /* Fill register REGNUM (if it is a floating-point or SSE register) in
666 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
667 all registers. This function doesn't touch any of the reserved
668 bits in *FXSAVE. */
669
670 void
671 i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
672 {
673 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
674 gdb_byte *regs = (gdb_byte *) fxsave;
675 int i;
676
677 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
678 gdb_assert (tdep->num_xmm_regs > 0);
679
680 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
681 if (regnum == -1 || regnum == i)
682 {
683 /* Most of the FPU control registers occupy only 16 bits in
684 the fxsave area. Give those a special treatment. */
685 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
686 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
687 {
688 gdb_byte buf[4];
689
690 regcache->raw_collect (i, buf);
691
692 if (i == I387_FOP_REGNUM (tdep))
693 {
694 /* The opcode occupies only 11 bits. Make sure we
695 don't touch the other bits. */
696 buf[1] &= ((1 << 3) - 1);
697 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
698 }
699 else if (i == I387_FTAG_REGNUM (tdep))
700 {
701 /* Converting back is much easier. */
702
703 unsigned short ftag;
704 int fpreg;
705
706 ftag = (buf[1] << 8) | buf[0];
707 buf[0] = 0;
708 buf[1] = 0;
709
710 for (fpreg = 7; fpreg >= 0; fpreg--)
711 {
712 int tag = (ftag >> (fpreg * 2)) & 3;
713
714 if (tag != 3)
715 buf[0] |= (1 << fpreg);
716 }
717 }
718 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
719 }
720 else
721 regcache->raw_collect (i, FXSAVE_ADDR (tdep, regs, i));
722 }
723
724 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
725 regcache->raw_collect (I387_MXCSR_REGNUM (tdep),
726 FXSAVE_MXCSR_ADDR (regs));
727 }
728
729 /* `xstate_bv' is at byte offset 512. */
730 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
731
732 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
733 the upper 128bit of AVX register data structure used by the "xsave"
734 instruction where GDB register REGNUM is stored. */
735
736 static int xsave_avxh_offset[] =
737 {
738 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
739 576 + 1 * 16,
740 576 + 2 * 16,
741 576 + 3 * 16,
742 576 + 4 * 16,
743 576 + 5 * 16,
744 576 + 6 * 16,
745 576 + 7 * 16,
746 576 + 8 * 16,
747 576 + 9 * 16,
748 576 + 10 * 16,
749 576 + 11 * 16,
750 576 + 12 * 16,
751 576 + 13 * 16,
752 576 + 14 * 16,
753 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
754 };
755
756 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
757 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
758
759 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
760 the upper 128bit of ZMM register data structure used by the "xsave"
761 instruction where GDB register REGNUM is stored. */
762
763 static int xsave_ymm_avx512_offset[] =
764 {
765 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
766 1664 + 16 + 0 * 64, /* %ymm16 through... */
767 1664 + 16 + 1 * 64,
768 1664 + 16 + 2 * 64,
769 1664 + 16 + 3 * 64,
770 1664 + 16 + 4 * 64,
771 1664 + 16 + 5 * 64,
772 1664 + 16 + 6 * 64,
773 1664 + 16 + 7 * 64,
774 1664 + 16 + 8 * 64,
775 1664 + 16 + 9 * 64,
776 1664 + 16 + 10 * 64,
777 1664 + 16 + 11 * 64,
778 1664 + 16 + 12 * 64,
779 1664 + 16 + 13 * 64,
780 1664 + 16 + 14 * 64,
781 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
782 };
783
784 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
785 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
786
787 static int xsave_xmm_avx512_offset[] =
788 {
789 1664 + 0 * 64, /* %ymm16 through... */
790 1664 + 1 * 64,
791 1664 + 2 * 64,
792 1664 + 3 * 64,
793 1664 + 4 * 64,
794 1664 + 5 * 64,
795 1664 + 6 * 64,
796 1664 + 7 * 64,
797 1664 + 8 * 64,
798 1664 + 9 * 64,
799 1664 + 10 * 64,
800 1664 + 11 * 64,
801 1664 + 12 * 64,
802 1664 + 13 * 64,
803 1664 + 14 * 64,
804 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
805 };
806
807 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
808 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
809
810 static int xsave_mpx_offset[] = {
811 960 + 0 * 16, /* bnd0r...bnd3r registers. */
812 960 + 1 * 16,
813 960 + 2 * 16,
814 960 + 3 * 16,
815 1024 + 0 * 8, /* bndcfg ... bndstatus. */
816 1024 + 1 * 8,
817 };
818
819 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
820 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
821
822 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
823 of the AVX512 opmask register data structure used by the "xsave"
824 instruction where GDB register REGNUM is stored. */
825
826 static int xsave_avx512_k_offset[] =
827 {
828 1088 + 0 * 8, /* %k0 through... */
829 1088 + 1 * 8,
830 1088 + 2 * 8,
831 1088 + 3 * 8,
832 1088 + 4 * 8,
833 1088 + 5 * 8,
834 1088 + 6 * 8,
835 1088 + 7 * 8 /* %k7 (64 bits each). */
836 };
837
838 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
839 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
840
841 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
842 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
843 instruction where GDB register REGNUM is stored. */
844
845 static int xsave_avx512_zmm_h_offset[] =
846 {
847 1152 + 0 * 32,
848 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
849 1152 + 2 * 32,
850 1152 + 3 * 32,
851 1152 + 4 * 32,
852 1152 + 5 * 32,
853 1152 + 6 * 32,
854 1152 + 7 * 32,
855 1152 + 8 * 32,
856 1152 + 9 * 32,
857 1152 + 10 * 32,
858 1152 + 11 * 32,
859 1152 + 12 * 32,
860 1152 + 13 * 32,
861 1152 + 14 * 32,
862 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
863 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
864 1664 + 32 + 1 * 64,
865 1664 + 32 + 2 * 64,
866 1664 + 32 + 3 * 64,
867 1664 + 32 + 4 * 64,
868 1664 + 32 + 5 * 64,
869 1664 + 32 + 6 * 64,
870 1664 + 32 + 7 * 64,
871 1664 + 32 + 8 * 64,
872 1664 + 32 + 9 * 64,
873 1664 + 32 + 10 * 64,
874 1664 + 32 + 11 * 64,
875 1664 + 32 + 12 * 64,
876 1664 + 32 + 13 * 64,
877 1664 + 32 + 14 * 64,
878 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
879 };
880
881 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
882 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
883
884 /* At xsave_pkeys_offset[REGNUM] you find the offset to the location
885 of the PKRU register data structure used by the "xsave"
886 instruction where GDB register REGNUM is stored. */
887
888 static int xsave_pkeys_offset[] =
889 {
890 2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by
891 instructions and applications). */
892 };
893
894 #define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \
895 (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)])
896
897
898 /* Extract from XSAVE a bitset of the features that are available on the
899 target, but which have not yet been enabled. */
900
901 ULONGEST
902 i387_xsave_get_clear_bv (struct gdbarch *gdbarch, const void *xsave)
903 {
904 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
905 const gdb_byte *regs = (const gdb_byte *) xsave;
906 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
907
908 /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */
909 ULONGEST xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
910 8, byte_order);
911
912 /* Clear part in vector registers if its bit in xstat_bv is zero. */
913 ULONGEST clear_bv = (~(xstate_bv)) & tdep->xcr0;
914
915 return clear_bv;
916 }
917
918 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
919
920 void
921 i387_supply_xsave (struct regcache *regcache, int regnum,
922 const void *xsave)
923 {
924 struct gdbarch *gdbarch = regcache->arch ();
925 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
926 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
927 const gdb_byte *regs = (const gdb_byte *) xsave;
928 int i;
929 /* In 64-bit mode the split between "low" and "high" ZMM registers is at
930 ZMM16. Outside of 64-bit mode there are no "high" ZMM registers at all.
931 Precalculate the number to be used for the split point, with the all
932 registers in the "low" portion outside of 64-bit mode. */
933 unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep)
934 + std::min (tdep->num_zmm_regs, 16);
935 ULONGEST clear_bv;
936 static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 };
937 enum
938 {
939 none = 0x0,
940 x87 = 0x1,
941 sse = 0x2,
942 avxh = 0x4,
943 mpx = 0x8,
944 avx512_k = 0x10,
945 avx512_zmm_h = 0x20,
946 avx512_ymmh_avx512 = 0x40,
947 avx512_xmm_avx512 = 0x80,
948 pkeys = 0x100,
949 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
950 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
951 } regclass;
952
953 gdb_assert (regs != NULL);
954 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
955 gdb_assert (tdep->num_xmm_regs > 0);
956
957 if (regnum == -1)
958 regclass = all;
959 else if (regnum >= I387_PKRU_REGNUM (tdep)
960 && regnum < I387_PKEYSEND_REGNUM (tdep))
961 regclass = pkeys;
962 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
963 && regnum < I387_ZMMENDH_REGNUM (tdep))
964 regclass = avx512_zmm_h;
965 else if (regnum >= I387_K0_REGNUM (tdep)
966 && regnum < I387_KEND_REGNUM (tdep))
967 regclass = avx512_k;
968 else if (regnum >= I387_YMM16H_REGNUM (tdep)
969 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
970 regclass = avx512_ymmh_avx512;
971 else if (regnum >= I387_XMM16_REGNUM (tdep)
972 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
973 regclass = avx512_xmm_avx512;
974 else if (regnum >= I387_YMM0H_REGNUM (tdep)
975 && regnum < I387_YMMENDH_REGNUM (tdep))
976 regclass = avxh;
977 else if (regnum >= I387_BND0R_REGNUM (tdep)
978 && regnum < I387_MPXEND_REGNUM (tdep))
979 regclass = mpx;
980 else if (regnum >= I387_XMM0_REGNUM (tdep)
981 && regnum < I387_MXCSR_REGNUM (tdep))
982 regclass = sse;
983 else if (regnum >= I387_ST0_REGNUM (tdep)
984 && regnum < I387_FCTRL_REGNUM (tdep))
985 regclass = x87;
986 else
987 regclass = none;
988
989 clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave);
990
991 /* With the delayed xsave mechanism, in between the program
992 starting, and the program accessing the vector registers for the
993 first time, the register's values are invalid. The kernel
994 initializes register states to zero when they are set the first
995 time in a program. This means that from the user-space programs'
996 perspective, it's the same as if the registers have always been
997 zero from the start of the program. Therefore, the debugger
998 should provide the same illusion to the user. */
999
1000 switch (regclass)
1001 {
1002 case none:
1003 break;
1004
1005 case pkeys:
1006 if ((clear_bv & X86_XSTATE_PKRU))
1007 regcache->raw_supply (regnum, zero);
1008 else
1009 regcache->raw_supply (regnum, XSAVE_PKEYS_ADDR (tdep, regs, regnum));
1010 return;
1011
1012 case avx512_zmm_h:
1013 if ((clear_bv & (regnum < zmm_endlo_regnum ? X86_XSTATE_ZMM_H
1014 : X86_XSTATE_ZMM)))
1015 regcache->raw_supply (regnum, zero);
1016 else
1017 regcache->raw_supply (regnum,
1018 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum));
1019 return;
1020
1021 case avx512_k:
1022 if ((clear_bv & X86_XSTATE_K))
1023 regcache->raw_supply (regnum, zero);
1024 else
1025 regcache->raw_supply (regnum, XSAVE_AVX512_K_ADDR (tdep, regs, regnum));
1026 return;
1027
1028 case avx512_ymmh_avx512:
1029 if ((clear_bv & X86_XSTATE_ZMM))
1030 regcache->raw_supply (regnum, zero);
1031 else
1032 regcache->raw_supply (regnum,
1033 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum));
1034 return;
1035
1036 case avx512_xmm_avx512:
1037 if ((clear_bv & X86_XSTATE_ZMM))
1038 regcache->raw_supply (regnum, zero);
1039 else
1040 regcache->raw_supply (regnum,
1041 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum));
1042 return;
1043
1044 case avxh:
1045 if ((clear_bv & X86_XSTATE_AVX))
1046 regcache->raw_supply (regnum, zero);
1047 else
1048 regcache->raw_supply (regnum, XSAVE_AVXH_ADDR (tdep, regs, regnum));
1049 return;
1050
1051 case mpx:
1052 if ((clear_bv & X86_XSTATE_BNDREGS))
1053 regcache->raw_supply (regnum, zero);
1054 else
1055 regcache->raw_supply (regnum, XSAVE_MPX_ADDR (tdep, regs, regnum));
1056 return;
1057
1058 case sse:
1059 if ((clear_bv & X86_XSTATE_SSE))
1060 regcache->raw_supply (regnum, zero);
1061 else
1062 regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum));
1063 return;
1064
1065 case x87:
1066 if ((clear_bv & X86_XSTATE_X87))
1067 regcache->raw_supply (regnum, zero);
1068 else
1069 regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum));
1070 return;
1071
1072 case all:
1073 /* Handle PKEYS registers. */
1074 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1075 {
1076 if ((clear_bv & X86_XSTATE_PKRU))
1077 {
1078 for (i = I387_PKRU_REGNUM (tdep);
1079 i < I387_PKEYSEND_REGNUM (tdep);
1080 i++)
1081 regcache->raw_supply (i, zero);
1082 }
1083 else
1084 {
1085 for (i = I387_PKRU_REGNUM (tdep);
1086 i < I387_PKEYSEND_REGNUM (tdep);
1087 i++)
1088 regcache->raw_supply (i, XSAVE_PKEYS_ADDR (tdep, regs, i));
1089 }
1090 }
1091
1092 /* Handle the upper halves of the low 8/16 ZMM registers. */
1093 if ((tdep->xcr0 & X86_XSTATE_ZMM_H))
1094 {
1095 if ((clear_bv & X86_XSTATE_ZMM_H))
1096 {
1097 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1098 regcache->raw_supply (i, zero);
1099 }
1100 else
1101 {
1102 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1103 regcache->raw_supply (i,
1104 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i));
1105 }
1106 }
1107
1108 /* Handle AVX512 OpMask registers. */
1109 if ((tdep->xcr0 & X86_XSTATE_K))
1110 {
1111 if ((clear_bv & X86_XSTATE_K))
1112 {
1113 for (i = I387_K0_REGNUM (tdep);
1114 i < I387_KEND_REGNUM (tdep);
1115 i++)
1116 regcache->raw_supply (i, zero);
1117 }
1118 else
1119 {
1120 for (i = I387_K0_REGNUM (tdep);
1121 i < I387_KEND_REGNUM (tdep);
1122 i++)
1123 regcache->raw_supply (i, XSAVE_AVX512_K_ADDR (tdep, regs, i));
1124 }
1125 }
1126
1127 /* Handle the upper 16 ZMM/YMM/XMM registers (if any). */
1128 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1129 {
1130 if ((clear_bv & X86_XSTATE_ZMM))
1131 {
1132 for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++)
1133 regcache->raw_supply (i, zero);
1134 for (i = I387_YMM16H_REGNUM (tdep);
1135 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1136 i++)
1137 regcache->raw_supply (i, zero);
1138 for (i = I387_XMM16_REGNUM (tdep);
1139 i < I387_XMM_AVX512_END_REGNUM (tdep);
1140 i++)
1141 regcache->raw_supply (i, zero);
1142 }
1143 else
1144 {
1145 for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++)
1146 regcache->raw_supply (i,
1147 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i));
1148 for (i = I387_YMM16H_REGNUM (tdep);
1149 i < I387_YMMH_AVX512_END_REGNUM (tdep);
1150 i++)
1151 regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i));
1152 for (i = I387_XMM16_REGNUM (tdep);
1153 i < I387_XMM_AVX512_END_REGNUM (tdep);
1154 i++)
1155 regcache->raw_supply (i, XSAVE_XMM_AVX512_ADDR (tdep, regs, i));
1156 }
1157 }
1158 /* Handle the upper YMM registers. */
1159 if ((tdep->xcr0 & X86_XSTATE_AVX))
1160 {
1161 if ((clear_bv & X86_XSTATE_AVX))
1162 {
1163 for (i = I387_YMM0H_REGNUM (tdep);
1164 i < I387_YMMENDH_REGNUM (tdep);
1165 i++)
1166 regcache->raw_supply (i, zero);
1167 }
1168 else
1169 {
1170 for (i = I387_YMM0H_REGNUM (tdep);
1171 i < I387_YMMENDH_REGNUM (tdep);
1172 i++)
1173 regcache->raw_supply (i, XSAVE_AVXH_ADDR (tdep, regs, i));
1174 }
1175 }
1176
1177 /* Handle the MPX registers. */
1178 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1179 {
1180 if (clear_bv & X86_XSTATE_BNDREGS)
1181 {
1182 for (i = I387_BND0R_REGNUM (tdep);
1183 i < I387_BNDCFGU_REGNUM (tdep); i++)
1184 regcache->raw_supply (i, zero);
1185 }
1186 else
1187 {
1188 for (i = I387_BND0R_REGNUM (tdep);
1189 i < I387_BNDCFGU_REGNUM (tdep); i++)
1190 regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i));
1191 }
1192 }
1193
1194 /* Handle the MPX registers. */
1195 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1196 {
1197 if (clear_bv & X86_XSTATE_BNDCFG)
1198 {
1199 for (i = I387_BNDCFGU_REGNUM (tdep);
1200 i < I387_MPXEND_REGNUM (tdep); i++)
1201 regcache->raw_supply (i, zero);
1202 }
1203 else
1204 {
1205 for (i = I387_BNDCFGU_REGNUM (tdep);
1206 i < I387_MPXEND_REGNUM (tdep); i++)
1207 regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i));
1208 }
1209 }
1210
1211 /* Handle the XMM registers. */
1212 if ((tdep->xcr0 & X86_XSTATE_SSE))
1213 {
1214 if ((clear_bv & X86_XSTATE_SSE))
1215 {
1216 for (i = I387_XMM0_REGNUM (tdep);
1217 i < I387_MXCSR_REGNUM (tdep);
1218 i++)
1219 regcache->raw_supply (i, zero);
1220 }
1221 else
1222 {
1223 for (i = I387_XMM0_REGNUM (tdep);
1224 i < I387_MXCSR_REGNUM (tdep); i++)
1225 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1226 }
1227 }
1228
1229 /* Handle the x87 registers. */
1230 if ((tdep->xcr0 & X86_XSTATE_X87))
1231 {
1232 if ((clear_bv & X86_XSTATE_X87))
1233 {
1234 for (i = I387_ST0_REGNUM (tdep);
1235 i < I387_FCTRL_REGNUM (tdep);
1236 i++)
1237 regcache->raw_supply (i, zero);
1238 }
1239 else
1240 {
1241 for (i = I387_ST0_REGNUM (tdep);
1242 i < I387_FCTRL_REGNUM (tdep);
1243 i++)
1244 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1245 }
1246 }
1247 break;
1248 }
1249
1250 /* Only handle x87 control registers. */
1251 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1252 if (regnum == -1 || regnum == i)
1253 {
1254 if (clear_bv & X86_XSTATE_X87)
1255 {
1256 if (i == I387_FCTRL_REGNUM (tdep))
1257 {
1258 gdb_byte buf[4];
1259
1260 store_unsigned_integer (buf, 4, byte_order,
1261 I387_FCTRL_INIT_VAL);
1262 regcache->raw_supply (i, buf);
1263 }
1264 else if (i == I387_FTAG_REGNUM (tdep))
1265 {
1266 gdb_byte buf[4];
1267
1268 store_unsigned_integer (buf, 4, byte_order, 0xffff);
1269 regcache->raw_supply (i, buf);
1270 }
1271 else
1272 regcache->raw_supply (i, zero);
1273 }
1274 /* Most of the FPU control registers occupy only 16 bits in
1275 the xsave extended state. Give those a special treatment. */
1276 else if (i != I387_FIOFF_REGNUM (tdep)
1277 && i != I387_FOOFF_REGNUM (tdep))
1278 {
1279 gdb_byte val[4];
1280
1281 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
1282 val[2] = val[3] = 0;
1283 if (i == I387_FOP_REGNUM (tdep))
1284 val[1] &= ((1 << 3) - 1);
1285 else if (i == I387_FTAG_REGNUM (tdep))
1286 {
1287 /* The fxsave area contains a simplified version of
1288 the tag word. We have to look at the actual 80-bit
1289 FP data to recreate the traditional i387 tag word. */
1290
1291 unsigned long ftag = 0;
1292 int fpreg;
1293 int top;
1294
1295 top = ((FXSAVE_ADDR (tdep, regs,
1296 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
1297 top &= 0x7;
1298
1299 for (fpreg = 7; fpreg >= 0; fpreg--)
1300 {
1301 int tag;
1302
1303 if (val[0] & (1 << fpreg))
1304 {
1305 int thisreg = (fpreg + 8 - top) % 8
1306 + I387_ST0_REGNUM (tdep);
1307 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
1308 }
1309 else
1310 tag = 3; /* Empty */
1311
1312 ftag |= tag << (2 * fpreg);
1313 }
1314 val[0] = ftag & 0xff;
1315 val[1] = (ftag >> 8) & 0xff;
1316 }
1317 regcache->raw_supply (i, val);
1318 }
1319 else
1320 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i));
1321 }
1322
1323 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1324 {
1325 /* The MXCSR register is placed into the xsave buffer if either the
1326 AVX or SSE features are enabled. */
1327 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE))
1328 == (X86_XSTATE_AVX | X86_XSTATE_SSE))
1329 {
1330 gdb_byte buf[4];
1331
1332 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL);
1333 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf);
1334 }
1335 else
1336 regcache->raw_supply (I387_MXCSR_REGNUM (tdep),
1337 FXSAVE_MXCSR_ADDR (regs));
1338 }
1339 }
1340
1341 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1342
1343 void
1344 i387_collect_xsave (const struct regcache *regcache, int regnum,
1345 void *xsave, int gcore)
1346 {
1347 struct gdbarch *gdbarch = regcache->arch ();
1348 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1349 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1350 gdb_byte *p, *regs = (gdb_byte *) xsave;
1351 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1352 ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0;
1353 unsigned int i;
1354 /* See the comment in i387_supply_xsave(). */
1355 unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep)
1356 + std::min (tdep->num_zmm_regs, 16);
1357 enum
1358 {
1359 x87_ctrl_or_mxcsr = 0x1,
1360 x87 = 0x2,
1361 sse = 0x4,
1362 avxh = 0x8,
1363 mpx = 0x10,
1364 avx512_k = 0x20,
1365 avx512_zmm_h = 0x40,
1366 avx512_ymmh_avx512 = 0x80,
1367 avx512_xmm_avx512 = 0x100,
1368 pkeys = 0x200,
1369 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h
1370 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys
1371 } regclass;
1372
1373 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
1374 gdb_assert (tdep->num_xmm_regs > 0);
1375
1376 if (regnum == -1)
1377 regclass = all;
1378 else if (regnum >= I387_PKRU_REGNUM (tdep)
1379 && regnum < I387_PKEYSEND_REGNUM (tdep))
1380 regclass = pkeys;
1381 else if (regnum >= I387_ZMM0H_REGNUM (tdep)
1382 && regnum < I387_ZMMENDH_REGNUM (tdep))
1383 regclass = avx512_zmm_h;
1384 else if (regnum >= I387_K0_REGNUM (tdep)
1385 && regnum < I387_KEND_REGNUM (tdep))
1386 regclass = avx512_k;
1387 else if (regnum >= I387_YMM16H_REGNUM (tdep)
1388 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep))
1389 regclass = avx512_ymmh_avx512;
1390 else if (regnum >= I387_XMM16_REGNUM (tdep)
1391 && regnum < I387_XMM_AVX512_END_REGNUM (tdep))
1392 regclass = avx512_xmm_avx512;
1393 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1394 && regnum < I387_YMMENDH_REGNUM (tdep))
1395 regclass = avxh;
1396 else if (regnum >= I387_BND0R_REGNUM (tdep)
1397 && regnum < I387_MPXEND_REGNUM (tdep))
1398 regclass = mpx;
1399 else if (regnum >= I387_XMM0_REGNUM (tdep)
1400 && regnum < I387_MXCSR_REGNUM (tdep))
1401 regclass = sse;
1402 else if (regnum >= I387_ST0_REGNUM (tdep)
1403 && regnum < I387_FCTRL_REGNUM (tdep))
1404 regclass = x87;
1405 else if ((regnum >= I387_FCTRL_REGNUM (tdep)
1406 && regnum < I387_XMM0_REGNUM (tdep))
1407 || regnum == I387_MXCSR_REGNUM (tdep))
1408 regclass = x87_ctrl_or_mxcsr;
1409 else
1410 internal_error (__FILE__, __LINE__, _("invalid i387 regnum %d"), regnum);
1411
1412 if (gcore)
1413 {
1414 /* Clear XSAVE extended state. */
1415 memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0));
1416
1417 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1418 if (tdep->xsave_xcr0_offset != -1)
1419 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1420 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1421 }
1422
1423 /* The supported bits in `xstat_bv' are 8 bytes. */
1424 initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1425 8, byte_order);
1426 clear_bv = (~(initial_xstate_bv)) & tdep->xcr0;
1427
1428 /* The XSAVE buffer was filled lazily by the kernel. Only those
1429 features that are enabled were written into the buffer, disabled
1430 features left the buffer uninitialised. In order to identify if any
1431 registers have changed we will be comparing the register cache
1432 version to the version in the XSAVE buffer, it is important then that
1433 at this point we initialise to the default values any features in
1434 XSAVE that are not yet initialised.
1435
1436 This could be made more efficient, we know which features (from
1437 REGNUM) we will be potentially updating, and could limit ourselves to
1438 only clearing that feature. However, the extra complexity does not
1439 seem justified at this point. */
1440 if (clear_bv)
1441 {
1442 if ((clear_bv & X86_XSTATE_PKRU))
1443 for (i = I387_PKRU_REGNUM (tdep);
1444 i < I387_PKEYSEND_REGNUM (tdep); i++)
1445 memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4);
1446
1447 if ((clear_bv & X86_XSTATE_BNDREGS))
1448 for (i = I387_BND0R_REGNUM (tdep);
1449 i < I387_BNDCFGU_REGNUM (tdep); i++)
1450 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16);
1451
1452 if ((clear_bv & X86_XSTATE_BNDCFG))
1453 for (i = I387_BNDCFGU_REGNUM (tdep);
1454 i < I387_MPXEND_REGNUM (tdep); i++)
1455 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8);
1456
1457 if ((clear_bv & X86_XSTATE_ZMM_H))
1458 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++)
1459 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32);
1460
1461 if ((clear_bv & X86_XSTATE_K))
1462 for (i = I387_K0_REGNUM (tdep);
1463 i < I387_KEND_REGNUM (tdep); i++)
1464 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8);
1465
1466 if ((clear_bv & X86_XSTATE_ZMM))
1467 {
1468 for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++)
1469 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32);
1470 for (i = I387_YMM16H_REGNUM (tdep);
1471 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1472 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1473 for (i = I387_XMM16_REGNUM (tdep);
1474 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1475 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16);
1476 }
1477
1478 if ((clear_bv & X86_XSTATE_AVX))
1479 for (i = I387_YMM0H_REGNUM (tdep);
1480 i < I387_YMMENDH_REGNUM (tdep); i++)
1481 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1482
1483 if ((clear_bv & X86_XSTATE_SSE))
1484 for (i = I387_XMM0_REGNUM (tdep);
1485 i < I387_MXCSR_REGNUM (tdep); i++)
1486 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1487
1488 /* The mxcsr register is written into the xsave buffer if either AVX
1489 or SSE is enabled, so only clear it if both of those features
1490 require clearing. */
1491 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE))
1492 == (X86_XSTATE_AVX | X86_XSTATE_SSE))
1493 store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs), 2, byte_order,
1494 I387_MXCSR_INIT_VAL);
1495
1496 if ((clear_bv & X86_XSTATE_X87))
1497 {
1498 for (i = I387_ST0_REGNUM (tdep);
1499 i < I387_FCTRL_REGNUM (tdep); i++)
1500 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1501
1502 for (i = I387_FCTRL_REGNUM (tdep);
1503 i < I387_XMM0_REGNUM (tdep); i++)
1504 {
1505 if (i == I387_FCTRL_REGNUM (tdep))
1506 store_unsigned_integer (FXSAVE_ADDR (tdep, regs, i), 2,
1507 byte_order, I387_FCTRL_INIT_VAL);
1508 else
1509 memset (FXSAVE_ADDR (tdep, regs, i), 0,
1510 regcache_register_size (regcache, i));
1511 }
1512 }
1513 }
1514
1515 if (regclass == all)
1516 {
1517 /* Check if any PKEYS registers are changed. */
1518 if ((tdep->xcr0 & X86_XSTATE_PKRU))
1519 for (i = I387_PKRU_REGNUM (tdep);
1520 i < I387_PKEYSEND_REGNUM (tdep); i++)
1521 {
1522 regcache->raw_collect (i, raw);
1523 p = XSAVE_PKEYS_ADDR (tdep, regs, i);
1524 if (memcmp (raw, p, 4) != 0)
1525 {
1526 xstate_bv |= X86_XSTATE_PKRU;
1527 memcpy (p, raw, 4);
1528 }
1529 }
1530
1531 /* Check if any ZMMH registers are changed. */
1532 if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM)))
1533 for (i = I387_ZMM0H_REGNUM (tdep);
1534 i < I387_ZMMENDH_REGNUM (tdep); i++)
1535 {
1536 regcache->raw_collect (i, raw);
1537 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i);
1538 if (memcmp (raw, p, 32) != 0)
1539 {
1540 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
1541 memcpy (p, raw, 32);
1542 }
1543 }
1544
1545 /* Check if any K registers are changed. */
1546 if ((tdep->xcr0 & X86_XSTATE_K))
1547 for (i = I387_K0_REGNUM (tdep);
1548 i < I387_KEND_REGNUM (tdep); i++)
1549 {
1550 regcache->raw_collect (i, raw);
1551 p = XSAVE_AVX512_K_ADDR (tdep, regs, i);
1552 if (memcmp (raw, p, 8) != 0)
1553 {
1554 xstate_bv |= X86_XSTATE_K;
1555 memcpy (p, raw, 8);
1556 }
1557 }
1558
1559 /* Check if any XMM or upper YMM registers are changed. */
1560 if ((tdep->xcr0 & X86_XSTATE_ZMM))
1561 {
1562 for (i = I387_YMM16H_REGNUM (tdep);
1563 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++)
1564 {
1565 regcache->raw_collect (i, raw);
1566 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i);
1567 if (memcmp (raw, p, 16) != 0)
1568 {
1569 xstate_bv |= X86_XSTATE_ZMM;
1570 memcpy (p, raw, 16);
1571 }
1572 }
1573 for (i = I387_XMM16_REGNUM (tdep);
1574 i < I387_XMM_AVX512_END_REGNUM (tdep); i++)
1575 {
1576 regcache->raw_collect (i, raw);
1577 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i);
1578 if (memcmp (raw, p, 16) != 0)
1579 {
1580 xstate_bv |= X86_XSTATE_ZMM;
1581 memcpy (p, raw, 16);
1582 }
1583 }
1584 }
1585
1586 /* Check if any upper MPX registers are changed. */
1587 if ((tdep->xcr0 & X86_XSTATE_BNDREGS))
1588 for (i = I387_BND0R_REGNUM (tdep);
1589 i < I387_BNDCFGU_REGNUM (tdep); i++)
1590 {
1591 regcache->raw_collect (i, raw);
1592 p = XSAVE_MPX_ADDR (tdep, regs, i);
1593 if (memcmp (raw, p, 16))
1594 {
1595 xstate_bv |= X86_XSTATE_BNDREGS;
1596 memcpy (p, raw, 16);
1597 }
1598 }
1599
1600 /* Check if any upper MPX registers are changed. */
1601 if ((tdep->xcr0 & X86_XSTATE_BNDCFG))
1602 for (i = I387_BNDCFGU_REGNUM (tdep);
1603 i < I387_MPXEND_REGNUM (tdep); i++)
1604 {
1605 regcache->raw_collect (i, raw);
1606 p = XSAVE_MPX_ADDR (tdep, regs, i);
1607 if (memcmp (raw, p, 8))
1608 {
1609 xstate_bv |= X86_XSTATE_BNDCFG;
1610 memcpy (p, raw, 8);
1611 }
1612 }
1613
1614 /* Check if any upper YMM registers are changed. */
1615 if ((tdep->xcr0 & X86_XSTATE_AVX))
1616 for (i = I387_YMM0H_REGNUM (tdep);
1617 i < I387_YMMENDH_REGNUM (tdep); i++)
1618 {
1619 regcache->raw_collect (i, raw);
1620 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1621 if (memcmp (raw, p, 16))
1622 {
1623 xstate_bv |= X86_XSTATE_AVX;
1624 memcpy (p, raw, 16);
1625 }
1626 }
1627
1628 /* Check if any SSE registers are changed. */
1629 if ((tdep->xcr0 & X86_XSTATE_SSE))
1630 for (i = I387_XMM0_REGNUM (tdep);
1631 i < I387_MXCSR_REGNUM (tdep); i++)
1632 {
1633 regcache->raw_collect (i, raw);
1634 p = FXSAVE_ADDR (tdep, regs, i);
1635 if (memcmp (raw, p, 16))
1636 {
1637 xstate_bv |= X86_XSTATE_SSE;
1638 memcpy (p, raw, 16);
1639 }
1640 }
1641
1642 if ((tdep->xcr0 & X86_XSTATE_AVX) || (tdep->xcr0 & X86_XSTATE_SSE))
1643 {
1644 i = I387_MXCSR_REGNUM (tdep);
1645 regcache->raw_collect (i, raw);
1646 p = FXSAVE_MXCSR_ADDR (regs);
1647 if (memcmp (raw, p, 4))
1648 {
1649 /* Now, we need to mark one of either SSE of AVX as enabled.
1650 We could pick either. What we do is check to see if one
1651 of the features is already enabled, if it is then we leave
1652 it at that, otherwise we pick SSE. */
1653 if ((xstate_bv & (X86_XSTATE_SSE | X86_XSTATE_AVX)) == 0)
1654 xstate_bv |= X86_XSTATE_SSE;
1655 memcpy (p, raw, 4);
1656 }
1657 }
1658
1659 /* Check if any X87 registers are changed. Only the non-control
1660 registers are handled here, the control registers are all handled
1661 later on in this function. */
1662 if ((tdep->xcr0 & X86_XSTATE_X87))
1663 for (i = I387_ST0_REGNUM (tdep);
1664 i < I387_FCTRL_REGNUM (tdep); i++)
1665 {
1666 regcache->raw_collect (i, raw);
1667 p = FXSAVE_ADDR (tdep, regs, i);
1668 if (memcmp (raw, p, 10))
1669 {
1670 xstate_bv |= X86_XSTATE_X87;
1671 memcpy (p, raw, 10);
1672 }
1673 }
1674 }
1675 else
1676 {
1677 /* Check if REGNUM is changed. */
1678 regcache->raw_collect (regnum, raw);
1679
1680 switch (regclass)
1681 {
1682 default:
1683 internal_error (__FILE__, __LINE__,
1684 _("invalid i387 regclass"));
1685
1686 case pkeys:
1687 /* This is a PKEYS register. */
1688 p = XSAVE_PKEYS_ADDR (tdep, regs, regnum);
1689 if (memcmp (raw, p, 4) != 0)
1690 {
1691 xstate_bv |= X86_XSTATE_PKRU;
1692 memcpy (p, raw, 4);
1693 }
1694 break;
1695
1696 case avx512_zmm_h:
1697 /* This is a ZMM register. */
1698 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum);
1699 if (memcmp (raw, p, 32) != 0)
1700 {
1701 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM);
1702 memcpy (p, raw, 32);
1703 }
1704 break;
1705 case avx512_k:
1706 /* This is a AVX512 mask register. */
1707 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum);
1708 if (memcmp (raw, p, 8) != 0)
1709 {
1710 xstate_bv |= X86_XSTATE_K;
1711 memcpy (p, raw, 8);
1712 }
1713 break;
1714
1715 case avx512_ymmh_avx512:
1716 /* This is an upper YMM16-31 register. */
1717 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum);
1718 if (memcmp (raw, p, 16) != 0)
1719 {
1720 xstate_bv |= X86_XSTATE_ZMM;
1721 memcpy (p, raw, 16);
1722 }
1723 break;
1724
1725 case avx512_xmm_avx512:
1726 /* This is an upper XMM16-31 register. */
1727 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum);
1728 if (memcmp (raw, p, 16) != 0)
1729 {
1730 xstate_bv |= X86_XSTATE_ZMM;
1731 memcpy (p, raw, 16);
1732 }
1733 break;
1734
1735 case avxh:
1736 /* This is an upper YMM register. */
1737 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1738 if (memcmp (raw, p, 16))
1739 {
1740 xstate_bv |= X86_XSTATE_AVX;
1741 memcpy (p, raw, 16);
1742 }
1743 break;
1744
1745 case mpx:
1746 if (regnum < I387_BNDCFGU_REGNUM (tdep))
1747 {
1748 regcache->raw_collect (regnum, raw);
1749 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1750 if (memcmp (raw, p, 16))
1751 {
1752 xstate_bv |= X86_XSTATE_BNDREGS;
1753 memcpy (p, raw, 16);
1754 }
1755 }
1756 else
1757 {
1758 p = XSAVE_MPX_ADDR (tdep, regs, regnum);
1759 xstate_bv |= X86_XSTATE_BNDCFG;
1760 memcpy (p, raw, 8);
1761 }
1762 break;
1763
1764 case sse:
1765 /* This is an SSE register. */
1766 p = FXSAVE_ADDR (tdep, regs, regnum);
1767 if (memcmp (raw, p, 16))
1768 {
1769 xstate_bv |= X86_XSTATE_SSE;
1770 memcpy (p, raw, 16);
1771 }
1772 break;
1773
1774 case x87:
1775 /* This is an x87 register. */
1776 p = FXSAVE_ADDR (tdep, regs, regnum);
1777 if (memcmp (raw, p, 10))
1778 {
1779 xstate_bv |= X86_XSTATE_X87;
1780 memcpy (p, raw, 10);
1781 }
1782 break;
1783
1784 case x87_ctrl_or_mxcsr:
1785 /* We only handle MXCSR here. All other x87 control registers
1786 are handled separately below. */
1787 if (regnum == I387_MXCSR_REGNUM (tdep))
1788 {
1789 p = FXSAVE_MXCSR_ADDR (regs);
1790 if (memcmp (raw, p, 2))
1791 {
1792 /* We're only setting MXCSR, so check the initial state
1793 to see if either of AVX or SSE are already enabled.
1794 If they are then we'll attribute this changed MXCSR to
1795 that feature. If neither feature is enabled, then
1796 we'll attribute this change to the SSE feature. */
1797 xstate_bv |= (initial_xstate_bv
1798 & (X86_XSTATE_AVX | X86_XSTATE_SSE));
1799 if ((xstate_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) == 0)
1800 xstate_bv |= X86_XSTATE_SSE;
1801 memcpy (p, raw, 2);
1802 }
1803 }
1804 }
1805 }
1806
1807 /* Only handle x87 control registers. */
1808 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1809 if (regnum == -1 || regnum == i)
1810 {
1811 /* Most of the FPU control registers occupy only 16 bits in
1812 the xsave extended state. Give those a special treatment. */
1813 if (i != I387_FIOFF_REGNUM (tdep)
1814 && i != I387_FOOFF_REGNUM (tdep))
1815 {
1816 gdb_byte buf[4];
1817
1818 regcache->raw_collect (i, buf);
1819
1820 if (i == I387_FOP_REGNUM (tdep))
1821 {
1822 /* The opcode occupies only 11 bits. Make sure we
1823 don't touch the other bits. */
1824 buf[1] &= ((1 << 3) - 1);
1825 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
1826 }
1827 else if (i == I387_FTAG_REGNUM (tdep))
1828 {
1829 /* Converting back is much easier. */
1830
1831 unsigned short ftag;
1832 int fpreg;
1833
1834 ftag = (buf[1] << 8) | buf[0];
1835 buf[0] = 0;
1836 buf[1] = 0;
1837
1838 for (fpreg = 7; fpreg >= 0; fpreg--)
1839 {
1840 int tag = (ftag >> (fpreg * 2)) & 3;
1841
1842 if (tag != 3)
1843 buf[0] |= (1 << fpreg);
1844 }
1845 }
1846 p = FXSAVE_ADDR (tdep, regs, i);
1847 if (memcmp (p, buf, 2))
1848 {
1849 xstate_bv |= X86_XSTATE_X87;
1850 memcpy (p, buf, 2);
1851 }
1852 }
1853 else
1854 {
1855 int regsize;
1856
1857 regcache->raw_collect (i, raw);
1858 regsize = regcache_register_size (regcache, i);
1859 p = FXSAVE_ADDR (tdep, regs, i);
1860 if (memcmp (raw, p, regsize))
1861 {
1862 xstate_bv |= X86_XSTATE_X87;
1863 memcpy (p, raw, regsize);
1864 }
1865 }
1866 }
1867
1868 /* Update the corresponding bits in `xstate_bv' if any
1869 registers are changed. */
1870 if (xstate_bv)
1871 {
1872 /* The supported bits in `xstat_bv' are 8 bytes. */
1873 initial_xstate_bv |= xstate_bv;
1874 store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs),
1875 8, byte_order,
1876 initial_xstate_bv);
1877 }
1878 }
1879
1880 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1881 *RAW. */
1882
1883 static int
1884 i387_tag (const gdb_byte *raw)
1885 {
1886 int integer;
1887 unsigned int exponent;
1888 unsigned long fraction[2];
1889
1890 integer = raw[7] & 0x80;
1891 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1892 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1893 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1894 | (raw[5] << 8) | raw[4]);
1895
1896 if (exponent == 0x7fff)
1897 {
1898 /* Special. */
1899 return (2);
1900 }
1901 else if (exponent == 0x0000)
1902 {
1903 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1904 {
1905 /* Zero. */
1906 return (1);
1907 }
1908 else
1909 {
1910 /* Special. */
1911 return (2);
1912 }
1913 }
1914 else
1915 {
1916 if (integer)
1917 {
1918 /* Valid. */
1919 return (0);
1920 }
1921 else
1922 {
1923 /* Special. */
1924 return (2);
1925 }
1926 }
1927 }
1928
1929 /* Prepare the FPU stack in REGCACHE for a function return. */
1930
1931 void
1932 i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1933 {
1934 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1935 ULONGEST fstat;
1936
1937 /* Set the top of the floating-point register stack to 7. The
1938 actual value doesn't really matter, but 7 is what a normal
1939 function return would end up with if the program started out with
1940 a freshly initialized FPU. */
1941 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1942 fstat |= (7 << 11);
1943 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1944
1945 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1946 floating-point register stack to 7, the appropriate value for the
1947 tag word is 0x3fff. */
1948 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1949
1950 }
1951
1952 /* See i387-tdep.h. */
1953
1954 void
1955 i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache)
1956 {
1957 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1958
1959 if (I387_BND0R_REGNUM (tdep) > 0)
1960 {
1961 gdb_byte bnd_buf[16];
1962
1963 memset (bnd_buf, 0, 16);
1964 for (int i = 0; i < I387_NUM_BND_REGS; i++)
1965 regcache->raw_write (I387_BND0R_REGNUM (tdep) + i, bnd_buf);
1966 }
1967 }
The GNU Binutils are a collection of binary tools.