3 { VEX_W_TABLE (EVEX_W_0F5B_P_0
) },
4 { "%XEvcvttp%XS2dq", { XM
, EXx
, EXxEVexS
}, 0 },
5 { "%XEvcvtp%XS2dq", { XM
, EXx
, EXxEVexR
}, 0 },
10 { VEX_W_TABLE (EVEX_W_0F6F_P_1
) },
11 { VEX_W_TABLE (EVEX_W_0F6F_P_2
) },
12 { VEX_W_TABLE (EVEX_W_0F6F_P_3
) },
14 /* PREFIX_EVEX_0F70 */
17 { "%XEvpshufhw", { XM
, EXx
, Ib
}, 0 },
18 { VEX_W_TABLE (EVEX_W_0F70_P_2
) },
19 { "%XEvpshuflw", { XM
, EXx
, Ib
}, 0 },
21 /* PREFIX_EVEX_0F78 */
23 { VEX_W_TABLE (EVEX_W_0F78_P_0
) },
24 { "vcvttss2usi", { Gdq
, EXd
, EXxEVexS
}, 0 },
25 { VEX_W_TABLE (EVEX_W_0F78_P_2
) },
26 { "vcvttsd2usi", { Gdq
, EXq
, EXxEVexS
}, 0 },
28 /* PREFIX_EVEX_0F79 */
30 { VEX_W_TABLE (EVEX_W_0F79_P_0
) },
31 { "vcvtss2usi", { Gdq
, EXd
, EXxEVexR
}, 0 },
32 { VEX_W_TABLE (EVEX_W_0F79_P_2
) },
33 { "vcvtsd2usi", { Gdq
, EXq
, EXxEVexR
}, 0 },
35 /* PREFIX_EVEX_0F7A */
38 { VEX_W_TABLE (EVEX_W_0F7A_P_1
) },
39 { VEX_W_TABLE (EVEX_W_0F7A_P_2
) },
40 { VEX_W_TABLE (EVEX_W_0F7A_P_3
) },
42 /* PREFIX_EVEX_0F7B */
45 { "vcvtusi2ssY{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
46 { VEX_W_TABLE (EVEX_W_0F7B_P_2
) },
47 { "vcvtusi2sdY{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR64
, Edq
}, 0 },
49 /* PREFIX_EVEX_0F7E */
52 { VEX_W_TABLE (EVEX_W_0F7E_P_1
) },
53 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
55 /* PREFIX_EVEX_0F7F */
58 { VEX_W_TABLE (EVEX_W_0F7F_P_1
) },
59 { VEX_W_TABLE (EVEX_W_0F7F_P_2
) },
60 { VEX_W_TABLE (EVEX_W_0F7F_P_3
) },
62 /* PREFIX_EVEX_0FC2 */
64 { "vcmppX", { MaskG
, Vex
, EXx
, EXxEVexS
, CMP
}, PREFIX_OPCODE
},
65 { "vcmps%XS", { MaskG
, VexScalar
, EXd
, EXxEVexS
, CMP
}, 0 },
66 { "vcmppX", { MaskG
, Vex
, EXx
, EXxEVexS
, CMP
}, PREFIX_OPCODE
},
67 { "vcmps%XD", { MaskG
, VexScalar
, EXq
, EXxEVexS
, CMP
}, 0 },
69 /* PREFIX_EVEX_0FE6 */
72 { VEX_W_TABLE (EVEX_W_0FE6_P_1
) },
73 { "%XEvcvttp%XD2dq%XY", { XMxmmq
, EXx
, EXxEVexS
}, 0 },
74 { "%XEvcvtp%XD2dq%XY", { XMxmmq
, EXx
, EXxEVexR
}, 0 },
76 /* PREFIX_EVEX_0F3810 */
79 { VEX_W_TABLE (EVEX_W_0F3810_P_1
) },
80 { VEX_W_TABLE (EVEX_W_0F3810_P_2
) },
82 /* PREFIX_EVEX_0F3811 */
85 { VEX_W_TABLE (EVEX_W_0F3811_P_1
) },
86 { VEX_W_TABLE (EVEX_W_0F3811_P_2
) },
88 /* PREFIX_EVEX_0F3812 */
91 { VEX_W_TABLE (EVEX_W_0F3812_P_1
) },
92 { VEX_W_TABLE (EVEX_W_0F3812_P_2
) },
94 /* PREFIX_EVEX_0F3813 */
97 { VEX_W_TABLE (EVEX_W_0F3813_P_1
) },
98 { "%XEvcvtph2p%XS", { XM
, EXxmmq
, EXxEVexS
}, 0 },
100 /* PREFIX_EVEX_0F3814 */
103 { VEX_W_TABLE (EVEX_W_0F3814_P_1
) },
104 { "vprorv%DQ", { XM
, Vex
, EXx
}, 0 },
106 /* PREFIX_EVEX_0F3815 */
109 { VEX_W_TABLE (EVEX_W_0F3815_P_1
) },
110 { "vprolv%DQ", { XM
, Vex
, EXx
}, 0 },
112 /* PREFIX_EVEX_0F3820 */
115 { VEX_W_TABLE (EVEX_W_0F3820_P_1
) },
116 { "%XEvpmovsxbw", { XM
, EXxmmq
}, 0 },
118 /* PREFIX_EVEX_0F3821 */
121 { VEX_W_TABLE (EVEX_W_0F3821_P_1
) },
122 { "%XEvpmovsxbd", { XM
, EXxmmqd
}, 0 },
124 /* PREFIX_EVEX_0F3822 */
127 { VEX_W_TABLE (EVEX_W_0F3822_P_1
) },
128 { "%XEvpmovsxbq", { XM
, EXxmmdw
}, 0 },
130 /* PREFIX_EVEX_0F3823 */
133 { VEX_W_TABLE (EVEX_W_0F3823_P_1
) },
134 { "%XEvpmovsxwd", { XM
, EXxmmq
}, 0 },
136 /* PREFIX_EVEX_0F3824 */
139 { VEX_W_TABLE (EVEX_W_0F3824_P_1
) },
140 { "%XEvpmovsxwq", { XM
, EXxmmqd
}, 0 },
142 /* PREFIX_EVEX_0F3825 */
145 { VEX_W_TABLE (EVEX_W_0F3825_P_1
) },
146 { VEX_W_TABLE (EVEX_W_0F3825_P_2
) },
148 /* PREFIX_EVEX_0F3826 */
151 { "vptestnm%BW", { MaskG
, Vex
, EXx
}, 0 },
152 { "vptestm%BW", { MaskG
, Vex
, EXx
}, 0 },
154 /* PREFIX_EVEX_0F3827 */
157 { "vptestnm%DQ", { MaskG
, Vex
, EXx
}, 0 },
158 { "vptestm%DQ", { MaskG
, Vex
, EXx
}, 0 },
160 /* PREFIX_EVEX_0F3828 */
163 { "vpmovm2Y%BW", { XM
, MaskR
}, 0 },
164 { VEX_W_TABLE (EVEX_W_0F3828_P_2
) },
166 /* PREFIX_EVEX_0F3829 */
169 { "vpmov%BW2mY", { MaskG
, Ux
}, 0 },
170 { VEX_W_TABLE (EVEX_W_0F3829_P_2
) },
172 /* PREFIX_EVEX_0F382A */
175 { VEX_W_TABLE (EVEX_W_0F382A_P_1
) },
176 { VEX_W_TABLE (EVEX_W_0F382A_P_2
) },
178 /* PREFIX_EVEX_0F3830 */
181 { VEX_W_TABLE (EVEX_W_0F3830_P_1
) },
182 { "%XEvpmovzxbw", { XM
, EXxmmq
}, 0 },
184 /* PREFIX_EVEX_0F3831 */
187 { VEX_W_TABLE (EVEX_W_0F3831_P_1
) },
188 { "%XEvpmovzxbd", { XM
, EXxmmqd
}, 0 },
190 /* PREFIX_EVEX_0F3832 */
193 { VEX_W_TABLE (EVEX_W_0F3832_P_1
) },
194 { "%XEvpmovzxbq", { XM
, EXxmmdw
}, 0 },
196 /* PREFIX_EVEX_0F3833 */
199 { VEX_W_TABLE (EVEX_W_0F3833_P_1
) },
200 { "%XEvpmovzxwd", { XM
, EXxmmq
}, 0 },
202 /* PREFIX_EVEX_0F3834 */
205 { VEX_W_TABLE (EVEX_W_0F3834_P_1
) },
206 { "%XEvpmovzxwq", { XM
, EXxmmqd
}, 0 },
208 /* PREFIX_EVEX_0F3835 */
211 { VEX_W_TABLE (EVEX_W_0F3835_P_1
) },
212 { VEX_W_TABLE (EVEX_W_0F3835_P_2
) },
214 /* PREFIX_EVEX_0F3838 */
217 { "vpmovm2Y%DQ", { XM
, MaskR
}, 0 },
218 { "%XEvpminsb", { XM
, Vex
, EXx
}, 0 },
220 /* PREFIX_EVEX_0F3839 */
223 { "vpmov%DQ2mY", { MaskG
, Ux
}, 0 },
224 { "%XEvpmins%DQ", { XM
, Vex
, EXx
}, 0 },
226 /* PREFIX_EVEX_0F383A */
229 { VEX_W_TABLE (EVEX_W_0F383A_P_1
) },
230 { "%XEvpminuw", { XM
, Vex
, EXx
}, 0 },
232 /* PREFIX_EVEX_0F3852 */
235 { "vdpbf16p%XS", { XM
, Vex
, EXx
}, 0 },
236 { VEX_W_TABLE (VEX_W_0F3852
) },
237 { "vp4dpws%XSd", { XM
, Vex
, Mxmm
}, 0 },
239 /* PREFIX_EVEX_0F3853 */
243 { VEX_W_TABLE (VEX_W_0F3853
) },
244 { "vp4dpws%XSds", { XM
, Vex
, Mxmm
}, 0 },
246 /* PREFIX_EVEX_0F3868 */
251 { "vp2intersectY%DQ", { MaskG
, Vex
, EXx
, EXxEVexS
}, 0 },
253 /* PREFIX_EVEX_0F3872 */
256 { "vcvtnep%XS2bf16%XY", { XMxmmq
, EXx
}, 0 },
257 { VEX_W_TABLE (EVEX_W_0F3872_P_2
) },
258 { "vcvtne2p%XS2bf16", { XM
, Vex
, EXx
}, 0 },
260 /* PREFIX_EVEX_0F389A */
264 { "%XEvfmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
265 { "v4fmaddp%XS", { XM
, Vex
, Mxmm
}, 0 },
267 /* PREFIX_EVEX_0F389B */
271 { "%XEvfmsub132s%XW", { XMScalar
, VexScalar
, EXdq
, EXxEVexR
}, 0 },
272 { "v4fmadds%XS", { XMScalar
, VexScalar
, Mxmm
}, 0 },
274 /* PREFIX_EVEX_0F38AA */
278 { "%XEvfmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
279 { "v4fnmaddp%XS", { XM
, Vex
, Mxmm
}, 0 },
281 /* PREFIX_EVEX_0F38AB */
285 { "%XEvfmsub213s%XW", { XMScalar
, VexScalar
, EXdq
, EXxEVexR
}, 0 },
286 { "v4fnmadds%XS", { XMScalar
, VexScalar
, Mxmm
}, 0 },
288 /* PREFIX_EVEX_0F3A08 */
290 { "vrndscalep%XH", { XM
, EXxh
, EXxEVexS
, Ib
}, 0 },
292 { "vrndscalep%XS", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
294 /* PREFIX_EVEX_0F3A0A */
296 { "vrndscales%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexS
, Ib
}, 0 },
298 { "vrndscales%XS", { XMScalar
, VexScalar
, EXd
, EXxEVexS
, Ib
}, 0 },
300 /* PREFIX_EVEX_0F3A26 */
302 { "vgetmantp%XH", { XM
, EXxh
, EXxEVexS
, Ib
}, 0 },
304 { "vgetmantp%XW", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
306 /* PREFIX_EVEX_0F3A27 */
308 { "vgetmants%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexS
, Ib
}, 0 },
310 { "vgetmants%XW", { XMScalar
, VexScalar
, EXdq
, EXxEVexS
, Ib
}, 0 },
312 /* PREFIX_EVEX_0F3A56 */
314 { "vreducep%XH", { XM
, EXxh
, EXxEVexS
, Ib
}, 0 },
316 { "vreducep%XW", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
318 /* PREFIX_EVEX_0F3A57 */
320 { "vreduces%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexS
, Ib
}, 0 },
322 { "vreduces%XW", { XMScalar
, VexScalar
, EXdq
, EXxEVexS
, Ib
}, 0 },
324 /* PREFIX_EVEX_0F3A66 */
326 { "vfpclassp%XH%XZ", { MaskG
, EXxh
, Ib
}, 0 },
328 { "vfpclassp%XW%XZ", { MaskG
, EXx
, Ib
}, 0 },
330 /* PREFIX_EVEX_0F3A67 */
332 { "vfpclasss%XH", { MaskG
, EXw
, Ib
}, 0 },
334 { "vfpclasss%XW", { MaskG
, EXdq
, Ib
}, 0 },
336 /* PREFIX_EVEX_0F3AC2 */
338 { "vcmpp%XH", { MaskG
, Vex
, EXxh
, EXxEVexS
, CMP
}, 0 },
339 { "vcmps%XH", { MaskG
, VexScalar
, EXw
, EXxEVexS
, CMP
}, 0 },
341 /* PREFIX_EVEX_MAP4_4x */
343 { "%CFcmov%CCS", { VexGv
, { CFCMOV_Fixup
, 0 }, { CFCMOV_Fixup
, 1 } }, 0 },
345 { "%CFcmov%CCS", { VexGv
, { CFCMOV_Fixup
, 0 }, { CFCMOV_Fixup
, 1 } }, 0 },
346 { "set%ZU%CC", { Eb
}, 0 },
348 /* PREFIX_EVEX_MAP4_F0 */
350 { "crc32A", { Gdq
, Eb
}, 0 },
351 { "invept", { Gm
, Mo
}, 0 },
353 /* PREFIX_EVEX_MAP4_F1 */
355 { "crc32Q", { Gdq
, Ev
}, 0 },
356 { "invvpid", { Gm
, Mo
}, 0 },
357 { "crc32Q", { Gdq
, Ev
}, 0 },
359 /* PREFIX_EVEX_MAP4_F2 */
362 { "invpcid", { Gm
, M
}, 0 },
364 /* PREFIX_EVEX_MAP4_F8 */
367 { MOD_TABLE (MOD_EVEX_MAP4_F8_P_1
) },
368 { "movdir64b", { Gva
, M
}, 0 },
369 { MOD_TABLE (MOD_EVEX_MAP4_F8_P_3
) },
371 /* PREFIX_EVEX_MAP5_10 */
374 { "vmovs%XH", { XMScalar
, VexScalarR
, EXw
}, 0 },
376 /* PREFIX_EVEX_MAP5_11 */
379 { "vmovs%XH", { EXwS
, VexScalarR
, XMScalar
}, 0 },
381 /* PREFIX_EVEX_MAP5_1D */
383 { "vcvtss2s%XH", { XMScalar
, VexScalar
, EXd
, EXxEVexR
}, 0 },
385 { "vcvtps2p%XHx%XY", { XMxmmq
, EXx
, EXxEVexR
}, 0 },
387 /* PREFIX_EVEX_MAP5_2A */
390 { "vcvtsi2shY{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
392 /* PREFIX_EVEX_MAP5_2C */
395 { "vcvttsh2si", { Gdq
, EXw
, EXxEVexS
}, 0 },
397 /* PREFIX_EVEX_MAP5_2D */
400 { "vcvtsh2si", { Gdq
, EXw
, EXxEVexR
}, 0 },
402 /* PREFIX_EVEX_MAP5_2E */
404 { "vucomisY%XH", { XMScalar
, EXw
, EXxEVexS
}, 0 },
406 /* PREFIX_EVEX_MAP5_2F */
408 { "vcomisY%XH", { XMScalar
, EXw
, EXxEVexS
}, 0 },
410 /* PREFIX_EVEX_MAP5_51 */
412 { "vsqrtp%XH", { XM
, EXxh
, EXxEVexR
}, 0 },
413 { "vsqrts%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexR
}, 0 },
415 /* PREFIX_EVEX_MAP5_58 */
417 { "vaddp%XH", { XM
, Vex
, EXxh
, EXxEVexR
}, 0 },
418 { "vadds%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexR
}, 0 },
420 /* PREFIX_EVEX_MAP5_59 */
422 { "vmulp%XH", { XM
, Vex
, EXxh
, EXxEVexR
}, 0 },
423 { "vmuls%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexR
}, 0 },
425 /* PREFIX_EVEX_MAP5_5A */
427 { "vcvtp%XH2pd", { XM
, EXxmmqdh
, EXxEVexS
}, 0 },
428 { "vcvts%XH2sd", { XMScalar
, VexScalar
, EXw
, EXxEVexS
}, 0 },
429 { "vcvtp%XD2ph%XZ", { XMM
, EXx
, EXxEVexR
}, 0 },
430 { "vcvts%XD2sh", { XMScalar
, VexScalar
, EXq
, EXxEVexR
}, 0 },
432 /* PREFIX_EVEX_MAP5_5B */
434 { VEX_W_TABLE (EVEX_W_MAP5_5B_P_0
) },
435 { "vcvttp%XH2dq", { XM
, EXxmmqh
, EXxEVexS
}, 0 },
436 { "vcvtp%XH2dq", { XM
, EXxmmqh
, EXxEVexR
}, 0 },
438 /* PREFIX_EVEX_MAP5_5C */
440 { "vsubp%XH", { XM
, Vex
, EXxh
, EXxEVexR
}, 0 },
441 { "vsubs%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexR
}, 0 },
443 /* PREFIX_EVEX_MAP5_5D */
445 { "vminp%XH", { XM
, Vex
, EXxh
, EXxEVexS
}, 0 },
446 { "vmins%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexS
}, 0 },
448 /* PREFIX_EVEX_MAP5_5E */
450 { "vdivp%XH", { XM
, Vex
, EXxh
, EXxEVexR
}, 0 },
451 { "vdivs%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexR
}, 0 },
453 /* PREFIX_EVEX_MAP5_5F */
455 { "vmaxp%XH", { XM
, Vex
, EXxh
, EXxEVexS
}, 0 },
456 { "vmaxs%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexS
}, 0 },
458 /* PREFIX_EVEX_MAP5_78 */
460 { "vcvttp%XH2udq", { XM
, EXxmmqh
, EXxEVexS
}, 0 },
461 { "vcvttsh2usi", { Gdq
, EXw
, EXxEVexS
}, 0 },
462 { "vcvttp%XH2uqq", { XM
, EXxmmqdh
, EXxEVexS
}, 0 },
464 /* PREFIX_EVEX_MAP5_79 */
466 { "vcvtp%XH2udq", { XM
, EXxmmqh
, EXxEVexR
}, 0 },
467 { "vcvtsh2usi", { Gdq
, EXw
, EXxEVexR
}, 0 },
468 { "vcvtp%XH2uqq", { XM
, EXxmmqdh
, EXxEVexR
}, 0 },
470 /* PREFIX_EVEX_MAP5_7A */
474 { "vcvttp%XH2qq", { XM
, EXxmmqdh
, EXxEVexS
}, 0 },
475 { VEX_W_TABLE (EVEX_W_MAP5_7A_P_3
) },
477 /* PREFIX_EVEX_MAP5_7B */
480 { "vcvtusi2shY{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
481 { "vcvtp%XH2qq", { XM
, EXxmmqdh
, EXxEVexR
}, 0 },
483 /* PREFIX_EVEX_MAP5_7C */
485 { "vcvttp%XH2uw", { XM
, EXxh
, EXxEVexS
}, 0 },
487 { "vcvttp%XH2w", { XM
, EXxh
, EXxEVexS
}, 0 },
489 /* PREFIX_EVEX_MAP5_7D */
491 { "vcvtp%XH2uw", { XM
, EXxh
, EXxEVexR
}, 0 },
492 { "vcvtw2p%XH", { XM
, EXxh
, EXxEVexR
}, 0 },
493 { "vcvtp%XH2w", { XM
, EXxh
, EXxEVexR
}, 0 },
494 { "vcvtuw2p%XH", { XM
, EXxh
, EXxEVexR
}, 0 },
496 /* PREFIX_EVEX_MAP6_13 */
498 { "vcvts%XH2ss", { XMScalar
, VexScalar
, EXw
, EXxEVexS
}, 0 },
500 { "vcvtp%XH2psx", { XM
, EXxmmqh
, EXxEVexS
}, 0 },
502 /* PREFIX_EVEX_MAP6_56 */
505 { "vfmaddcp%XH", { { DistinctDest_Fixup
, 0 }, Vex
, EXx
, EXxEVexR
}, 0 },
507 { "vfcmaddcp%XH", { { DistinctDest_Fixup
, 0 }, Vex
, EXx
, EXxEVexR
}, 0 },
509 /* PREFIX_EVEX_MAP6_57 */
512 { "vfmaddcs%XH", { { DistinctDest_Fixup
, scalar_mode
}, VexScalar
, EXd
, EXxEVexR
}, 0 },
514 { "vfcmaddcs%XH", { { DistinctDest_Fixup
, scalar_mode
}, VexScalar
, EXd
, EXxEVexR
}, 0 },
516 /* PREFIX_EVEX_MAP6_D6 */
519 { "vfmulcp%XH", { { DistinctDest_Fixup
, 0 }, Vex
, EXx
, EXxEVexR
}, 0 },
521 { "vfcmulcp%XH", { { DistinctDest_Fixup
, 0 }, Vex
, EXx
, EXxEVexR
}, 0 },
523 /* PREFIX_EVEX_MAP6_D7 */
526 { "vfmulcs%XH", { { DistinctDest_Fixup
, scalar_mode
}, VexScalar
, EXd
, EXxEVexR
}, 0 },
528 { "vfcmulcs%XH", { { DistinctDest_Fixup
, scalar_mode
}, VexScalar
, EXd
, EXxEVexR
}, 0 },