opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2024 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep this sorted alphanumerically and synced with the fields array
  29    in aarch64-opc.c.  */
  30 enum aarch64_field_kind
  31 {
  32   FLD_NIL,
  33   FLD_CRm,
  34   FLD_CRm_dsb_nxs,
  35   FLD_CRn,
  36   FLD_CSSC_imm8,
  37   FLD_H,
  38   FLD_L,
  39   FLD_LSE128_Rt,
  40   FLD_LSE128_Rt2,
  41   FLD_M,
  42   FLD_N,
  43   FLD_Q,
  44   FLD_Ra,
  45   FLD_Rd,
  46   FLD_Rm,
  47   FLD_Rn,
  48   FLD_Rs,
  49   FLD_Rt,
  50   FLD_Rt2,
  51   FLD_S,
  52   FLD_SM3_imm2,
  53   FLD_SME_Pdx2,
  54   FLD_SME_Pm,
  55   FLD_SME_PNd3,
  56   FLD_SME_PNn3,
  57   FLD_SME_Q,
  58   FLD_SME_Rm,
  59   FLD_SME_Rv,
  60   FLD_SME_V,
  61   FLD_SME_VL_10,
  62   FLD_SME_VL_13,
  63   FLD_SME_ZAda_1b,
  64   FLD_SME_ZAda_2b,
  65   FLD_SME_ZAda_3b,
  66   FLD_SME_ZdnT,
  67   FLD_SME_Zdn2,
  68   FLD_SME_Zdn2_0,
  69   FLD_SME_Zdn4,
  70   FLD_SME_Zm,
  71   FLD_SME_Zm2,
  72   FLD_SME_Zm4,
  73   FLD_SME_Zn2,
  74   FLD_SME_Zn4,
  75   FLD_SME_ZtT,
  76   FLD_SME_Zt3,
  77   FLD_SME_Zt2,
  78   FLD_SME_i1,
  79   FLD_SME_size_12,
  80   FLD_SME_size_22,
  81   FLD_SME_sz_23,
  82   FLD_SME_tszh,
  83   FLD_SME_tszl,
  84   FLD_SME_zero_mask,
  85   FLD_SVE_M_4,
  86   FLD_SVE_M_14,
  87   FLD_SVE_M_16,
  88   FLD_SVE_N,
  89   FLD_SVE_Pd,
  90   FLD_SVE_Pg3,
  91   FLD_SVE_Pg4_5,
  92   FLD_SVE_Pg4_10,
  93   FLD_SVE_Pg4_16,
  94   FLD_SVE_Pm,
  95   FLD_SVE_Pn,
  96   FLD_SVE_Pt,
  97   FLD_SVE_Rm,
  98   FLD_SVE_Rn,
  99   FLD_SVE_Vd,
 100   FLD_SVE_Vm,
 101   FLD_SVE_Vn,
 102   FLD_SVE_Za_5,
 103   FLD_SVE_Za_16,
 104   FLD_SVE_Zd,
 105   FLD_SVE_Zm_5,
 106   FLD_SVE_Zm_16,
 107   FLD_SVE_Zn,
 108   FLD_SVE_Zt,
 109   FLD_SVE_i1,
 110   FLD_SVE_i1_23,
 111   FLD_SVE_i2,
 112   FLD_SVE_i2h,
 113   FLD_SVE_i3h,
 114   FLD_SVE_i3h2,
 115   FLD_SVE_i3h3,
 116   FLD_SVE_i3l,
 117   FLD_SVE_i3l2,
 118   FLD_SVE_i4l2,
 119   FLD_SVE_imm3,
 120   FLD_SVE_imm4,
 121   FLD_SVE_imm5,
 122   FLD_SVE_imm5b,
 123   FLD_SVE_imm6,
 124   FLD_SVE_imm7,
 125   FLD_SVE_imm8,
 126   FLD_SVE_imm9,
 127   FLD_SVE_immr,
 128   FLD_SVE_imms,
 129   FLD_SVE_msz,
 130   FLD_SVE_pattern,
 131   FLD_SVE_prfop,
 132   FLD_SVE_rot1,
 133   FLD_SVE_rot2,
 134   FLD_SVE_rot3,
 135   FLD_SVE_size,
 136   FLD_SVE_sz,
 137   FLD_SVE_sz2,
 138   FLD_SVE_tsz,
 139   FLD_SVE_tszh,
 140   FLD_SVE_tszl_8,
 141   FLD_SVE_tszl_19,
 142   FLD_SVE_xs_14,
 143   FLD_SVE_xs_22,
 144   FLD_S_imm10,
 145   FLD_abc,
 146   FLD_asisdlso_opcode,
 147   FLD_b40,
 148   FLD_b5,
 149   FLD_cmode,
 150   FLD_cond,
 151   FLD_cond2,
 152   FLD_defgh,
 153   FLD_hw,
 154   FLD_imm1_0,
 155   FLD_imm1_2,
 156   FLD_imm1_3,
 157   FLD_imm1_8,
 158   FLD_imm1_10,
 159   FLD_imm1_14,
 160   FLD_imm1_15,
 161   FLD_imm1_16,
 162   FLD_imm2_0,
 163   FLD_imm2_1,
 164   FLD_imm2_2,
 165   FLD_imm2_8,
 166   FLD_imm2_10,
 167   FLD_imm2_12,
 168   FLD_imm2_13,
 169   FLD_imm2_15,
 170   FLD_imm2_16,
 171   FLD_imm2_19,
 172   FLD_imm3_0,
 173   FLD_imm3_5,
 174   FLD_imm3_10,
 175   FLD_imm3_12,
 176   FLD_imm3_14,
 177   FLD_imm3_15,
 178   FLD_imm3_19,
 179   FLD_imm4_0,
 180   FLD_imm4_5,
 181   FLD_imm4_10,
 182   FLD_imm4_11,
 183   FLD_imm4_14,
 184   FLD_imm5,
 185   FLD_imm6_10,
 186   FLD_imm6_15,
 187   FLD_imm7,
 188   FLD_imm8,
 189   FLD_imm9,
 190   FLD_imm12,
 191   FLD_imm14,
 192   FLD_imm16_0,
 193   FLD_imm16_5,
 194   FLD_imm17_1,
 195   FLD_imm17_2,
 196   FLD_imm19,
 197   FLD_imm26,
 198   FLD_immb,
 199   FLD_immh,
 200   FLD_immhi,
 201   FLD_immlo,
 202   FLD_immr,
 203   FLD_imms,
 204   FLD_index,
 205   FLD_index2,
 206   FLD_ldst_size,
 207   FLD_len,
 208   FLD_lse_sz,
 209   FLD_nzcv,
 210   FLD_op,
 211   FLD_op0,
 212   FLD_op1,
 213   FLD_op2,
 214   FLD_opc,
 215   FLD_opc1,
 216   FLD_opcode,
 217   FLD_option,
 218   FLD_rotate1,
 219   FLD_rotate2,
 220   FLD_rotate3,
 221   FLD_scale,
 222   FLD_sf,
 223   FLD_shift,
 224   FLD_size,
 225   FLD_sz,
 226   FLD_type,
 227   FLD_vldst_size,
 228   FLD_off3,
 229   FLD_off2,
 230   FLD_ZAn_1,
 231   FLD_ol,
 232   FLD_ZAn_2,
 233   FLD_ZAn_3,
 234   FLD_ZAn,
 235   FLD_opc2,
 236   FLD_rcpc3_size,
 237   FLD_brbop,
 238   FLD_ZA8_1,
 239   FLD_ZA7_2,
 240   FLD_ZA6_3,
 241   FLD_ZA5_4,
 242 };
 243
 244 /* Field description.  */
 245 struct aarch64_field
 246 {
 247   int lsb;
 248   int width;
 249 };
 250
 251 typedef struct aarch64_field aarch64_field;
 252
 253 extern const aarch64_field fields[];
 254 \f
 255 /* Operand description.  */
 256
 257 struct aarch64_operand
 258 {
 259   enum aarch64_operand_class op_class;
 260
 261   /* Name of the operand code; used mainly for the purpose of internal
 262      debugging.  */
 263   const char *name;
 264
 265   unsigned int flags;
 266
 267   /* The associated instruction bit-fields; no operand has more than 4
 268      bit-fields */
 269   enum aarch64_field_kind fields[5];
 270
 271   /* Brief description */
 272   const char *desc;
 273 };
 274
 275 typedef struct aarch64_operand aarch64_operand;
 276
 277 extern const aarch64_operand aarch64_operands[];
 278
 279 enum err_type
 280 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 281                     bool, aarch64_operand_error *, aarch64_instr_sequence*);
 282
 283 /* Operand flags.  */
 284
 285 #define OPD_F_HAS_INSERTER      0x00000001
 286 #define OPD_F_HAS_EXTRACTOR     0x00000002
 287 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 288 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 289                                                    value by 2 to get the value
 290                                                    of an immediate operand.  */
 291 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 292 #define OPD_F_OD_MASK           0x000001e0      /* Operand-dependent data.  */
 293 #define OPD_F_OD_LSB            5
 294 #define OPD_F_NO_ZR             0x00000200      /* ZR index not allowed.  */
 295 #define OPD_F_SHIFT_BY_3        0x00000400      /* Need to left shift the field
 296                                                    value by 3 to get the value
 297                                                    of an immediate operand.  */
 298 #define OPD_F_SHIFT_BY_4        0x00000800      /* Need to left shift the field
 299                                                    value by 4 to get the value
 300                                                    of an immediate operand.  */
 301
 302
 303 /* Register flags.  */
 304
 305 #undef F_DEPRECATED
 306 #define F_DEPRECATED    (1 << 0)  /* Deprecated system register.  */
 307
 308 #undef F_ARCHEXT
 309 #define F_ARCHEXT       (1 << 1)  /* Architecture dependent system register.  */
 310
 311 #undef F_HASXT
 312 #define F_HASXT         (1 << 2)  /* System instruction register <Xt>
 313                                      operand.  */
 314
 315 #undef F_REG_READ
 316 #define F_REG_READ      (1 << 3)  /* Register can only be used to read values
 317                                      out of.  */
 318
 319 #undef F_REG_WRITE
 320 #define F_REG_WRITE     (1 << 4)  /* Register can only be written to but not
 321                                      read from.  */
 322
 323 #undef F_REG_IN_CRM
 324 #define F_REG_IN_CRM    (1 << 5)  /* Register extra encoding in CRm.  */
 325
 326 #undef F_REG_ALIAS
 327 #define F_REG_ALIAS     (1 << 6)  /* Register name aliases another.  */
 328
 329 #undef F_REG_128
 330 #define F_REG_128       (1 << 7) /* System regsister implementable as 128-bit wide.  */
 331
 332
 333 /* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
 334    Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
 335    In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below
 336    macros to encode and decode CRm encoding.
 337 */
 338 #define PSTATE_ENCODE_CRM(val) (val << 6)
 339 #define PSTATE_DECODE_CRM(flags) ((flags >> 6) & 0x0f)
 340
 341 #undef F_IMM_IN_CRM
 342 #define F_IMM_IN_CRM    (1 << 10)  /* Immediate extra encoding in CRm.  */
 343
 344 /* Also CRm may contain, in addition to <pstatefield> immediate.
 345    E.g. CRm[0] <imm1> at bit 0 for SME. Use below macros to encode and decode
 346    immediate mask.
 347 */
 348 #define PSTATE_ENCODE_CRM_IMM(mask) (mask << 11)
 349 #define PSTATE_DECODE_CRM_IMM(mask) ((mask >> 11) & 0x0f)
 350
 351 /* Helper macro to ENCODE CRm and its immediate.  */
 352 #define PSTATE_ENCODE_CRM_AND_IMM(CVAL,IMASK) \
 353         (F_REG_IN_CRM | PSTATE_ENCODE_CRM(CVAL) \
 354          | F_IMM_IN_CRM | PSTATE_ENCODE_CRM_IMM(IMASK))
 355
 356 /* Bits [15, 18] contain the maximum value for an immediate MSR.  */
 357 #define F_REG_MAX_VALUE(X) ((X) << 15)
 358 #define F_GET_REG_MAX_VALUE(X) (((X) >> 15) & 0x0f)
 359
 360 /* HINT operand flags.  */
 361 #define HINT_OPD_F_NOPRINT      (1 << 0)  /* Should not be printed.  */
 362
 363 /* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
 364 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
 365 #define HINT_FLAG(val) (val >> 8)
 366 #define HINT_VAL(val) (val & 0xff)
 367
 368 static inline bool
 369 operand_has_inserter (const aarch64_operand *operand)
 370 {
 371   return (operand->flags & OPD_F_HAS_INSERTER) != 0;
 372 }
 373
 374 static inline bool
 375 operand_has_extractor (const aarch64_operand *operand)
 376 {
 377   return (operand->flags & OPD_F_HAS_EXTRACTOR) != 0;
 378 }
 379
 380 static inline bool
 381 operand_need_sign_extension (const aarch64_operand *operand)
 382 {
 383   return (operand->flags & OPD_F_SEXT) != 0;
 384 }
 385
 386 static inline bool
 387 operand_need_shift_by_two (const aarch64_operand *operand)
 388 {
 389   return (operand->flags & OPD_F_SHIFT_BY_2) != 0;
 390 }
 391
 392 static inline bool
 393 operand_need_shift_by_three (const aarch64_operand *operand)
 394 {
 395   return (operand->flags & OPD_F_SHIFT_BY_3) != 0;
 396 }
 397
 398 static inline bool
 399 operand_need_shift_by_four (const aarch64_operand *operand)
 400 {
 401   return (operand->flags & OPD_F_SHIFT_BY_4) != 0;
 402 }
 403
 404 static inline bool
 405 operand_maybe_stack_pointer (const aarch64_operand *operand)
 406 {
 407   return (operand->flags & OPD_F_MAYBE_SP) != 0;
 408 }
 409
 410 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 411 static inline unsigned int
 412 get_operand_specific_data (const aarch64_operand *operand)
 413 {
 414   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 415 }
 416
 417 /* Return the width of field number N of operand *OPERAND.  */
 418 static inline unsigned
 419 get_operand_field_width (const aarch64_operand *operand, unsigned n)
 420 {
 421   assert (operand->fields[n] != FLD_NIL);
 422   return fields[operand->fields[n]].width;
 423 }
 424
 425 /* Return the total width of the operand *OPERAND.  */
 426 static inline unsigned
 427 get_operand_fields_width (const aarch64_operand *operand)
 428 {
 429   int i = 0;
 430   unsigned width = 0;
 431   while (operand->fields[i] != FLD_NIL)
 432     width += fields[operand->fields[i++]].width;
 433   assert (width > 0 && width < 32);
 434   return width;
 435 }
 436
 437 static inline const aarch64_operand *
 438 get_operand_from_code (enum aarch64_opnd code)
 439 {
 440   return aarch64_operands + code;
 441 }
 442 \f
 443 /* Operand qualifier and operand constraint checking.  */
 444
 445 int aarch64_match_operands_constraint (aarch64_inst *,
 446                                        aarch64_operand_error *);
 447
 448 /* Operand qualifier related functions.  */
 449 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 450 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 451 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 452 int aarch64_find_best_match (const aarch64_inst *,
 453                              const aarch64_opnd_qualifier_seq_t *,
 454                              int, aarch64_opnd_qualifier_t *, int *);
 455
 456 static inline void
 457 reset_operand_qualifier (aarch64_inst *inst, int idx)
 458 {
 459   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 460   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 461 }
 462 \f
 463 /* Inline functions operating on instruction bit-field(s).  */
 464
 465 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 466
 467 static inline aarch64_insn
 468 gen_mask (int width)
 469 {
 470   return ((aarch64_insn) 1 << width) - 1;
 471 }
 472
 473 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 474 static inline int
 475 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 476 {
 477   const aarch64_field *field = &fields[kind];
 478   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 479     return 0;
 480   ret->lsb = field->lsb + lsb_rel;
 481   ret->width = width;
 482   return 1;
 483 }
 484
 485 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 486    of the opcode.  */
 487
 488 static inline void
 489 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 490                 aarch64_insn value, aarch64_insn mask)
 491 {
 492   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 493           && field->lsb + field->width <= 32);
 494   value &= gen_mask (field->width);
 495   value <<= field->lsb;
 496   /* In some opcodes, field can be part of the base opcode, e.g. the size
 497      field in FADD.  The following helps avoid corrupt the base opcode.  */
 498   value &= ~mask;
 499   *code |= value;
 500 }
 501
 502 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 503    mask of the opcode.  */
 504
 505 static inline aarch64_insn
 506 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 507                  aarch64_insn mask)
 508 {
 509   aarch64_insn value;
 510   /* Clear any bit that is a part of the base opcode.  */
 511   code &= ~mask;
 512   value = (code >> field->lsb) & gen_mask (field->width);
 513   return value;
 514 }
 515
 516 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 517    of the opcode.  */
 518
 519 static inline void
 520 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 521               aarch64_insn value, aarch64_insn mask)
 522 {
 523   insert_field_2 (&fields[kind], code, value, mask);
 524 }
 525
 526 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 527    base mask of the opcode.  */
 528
 529 static inline aarch64_insn
 530 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 531                aarch64_insn mask)
 532 {
 533   return extract_field_2 (&fields[kind], code, mask);
 534 }
 535
 536 extern aarch64_insn
 537 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 538 \f
 539 /* Inline functions selecting operand to do the encoding/decoding for a
 540    certain instruction bit-field.  */
 541
 542 /* Select the operand to do the encoding/decoding of the 'sf' field.
 543    The heuristic-based rule is that the result operand is respected more.  */
 544
 545 static inline int
 546 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 547 {
 548   int idx = -1;
 549   if (aarch64_get_operand_class (opcode->operands[0])
 550       == AARCH64_OPND_CLASS_INT_REG)
 551     /* normal case.  */
 552     idx = 0;
 553   else if (aarch64_get_operand_class (opcode->operands[1])
 554            == AARCH64_OPND_CLASS_INT_REG)
 555     /* e.g. float2fix.  */
 556     idx = 1;
 557   else
 558     { assert (0); abort (); }
 559   return idx;
 560 }
 561
 562 /* Select the operand to do the encoding/decoding of the 'type' field in
 563    the floating-point instructions.
 564    The heuristic-based rule is that the source operand is respected more.  */
 565
 566 static inline int
 567 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 568 {
 569   int idx;
 570   if (aarch64_get_operand_class (opcode->operands[1])
 571       == AARCH64_OPND_CLASS_FP_REG)
 572     /* normal case.  */
 573     idx = 1;
 574   else if (aarch64_get_operand_class (opcode->operands[0])
 575            == AARCH64_OPND_CLASS_FP_REG)
 576     /* e.g. float2fix.  */
 577     idx = 0;
 578   else
 579     { assert (0); abort (); }
 580   return idx;
 581 }
 582
 583 /* Select the operand to do the encoding/decoding of the 'size' field in
 584    the AdvSIMD scalar instructions.
 585    The heuristic-based rule is that the destination operand is respected
 586    more.  */
 587
 588 static inline int
 589 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 590 {
 591   int src_size = 0, dst_size = 0;
 592   if (aarch64_get_operand_class (opcode->operands[0])
 593       == AARCH64_OPND_CLASS_SISD_REG)
 594     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 595   if (aarch64_get_operand_class (opcode->operands[1])
 596       == AARCH64_OPND_CLASS_SISD_REG)
 597     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 598   if (src_size == dst_size && src_size == 0)
 599     { assert (0); abort (); }
 600   /* When the result is not a sisd register or it is a long operantion.  */
 601   if (dst_size == 0 || dst_size == src_size << 1)
 602     return 1;
 603   else
 604     return 0;
 605 }
 606
 607 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 608    the AdvSIMD instructions.  */
 609
 610 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 611 \f
 612 /* Miscellaneous.  */
 613
 614 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 615 enum aarch64_modifier_kind
 616 aarch64_get_operand_modifier_from_value (aarch64_insn, bool);
 617
 618
 619 bool aarch64_wide_constant_p (uint64_t, int, unsigned int *);
 620 bool aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 621 int aarch64_shrink_expanded_imm8 (uint64_t);
 622
 623 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 624 static inline void
 625 copy_operand_info (aarch64_inst *inst, int dst, int src)
 626 {
 627   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 628           && src < AARCH64_MAX_OPND_NUM);
 629   memcpy (&inst->operands[dst], &inst->operands[src],
 630           sizeof (aarch64_opnd_info));
 631   inst->operands[dst].idx = dst;
 632 }
 633
 634 /* A primitive log caculator.  */
 635
 636 static inline unsigned int
 637 get_logsz (unsigned int size)
 638 {
 639   const unsigned char ls[16] =
 640     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 641   if (size > 16)
 642     {
 643       assert (0);
 644       return -1;
 645     }
 646   assert (ls[size - 1] != (unsigned char)-1);
 647   return ls[size - 1];
 648 }
 649
 650 #endif /* OPCODES_AARCH64_OPC_H */