| blob | a001424241eca13cb7a4e752fc8704f1874e4fec |
1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
71 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
72 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
73 #define ST0_FR (1 << 26)
75 /* The sizes of floating point registers. */
77 enum
78 {
81 };
83 enum
84 {
87 };
99 NULL
100 };
102 /* For backwards compatibility we default to MIPS16. This flag is
103 overridden as soon as unambiguous ELF file flags tell us the
104 compressed ISA encoding used. */
108 {
109 mips_compression_mips16,
110 mips_compression_micromips,
111 NULL
112 };
116 /* The standard register names, and all the valid aliases for them. */
117 struct register_alias
118 {
121 };
123 /* Aliases for o32 and most other ABIs. */
129 };
131 /* Aliases for n32 and n64. */
137 };
139 /* Aliases for ABI-independent registers. */
141 /* The architecture manuals specify these ABI-independent names for
142 the GPRs. */
148 #undef R
150 /* k0 and k1 are sometimes called these instead (for "kernel
151 temp"). */
155 /* This is the traditional GDB name for the CP0 status register. */
158 /* This is the traditional GDB name for the CP0 BadVAddr register. */
161 /* This is the traditional GDB name for the FCSR. */
163 };
166 #define R(n) { #n, n }
171 #undef R
172 };
174 #ifndef MIPS_DEFAULT_FPU_TYPE
175 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
176 #endif
182 /* Properties (for struct target_desc) describing the g/G packet
183 layout. */
192 {
194 }
196 static int
198 {
200 }
202 /* Return 1 if REGNUM refers to a floating-point general register, raw
203 or cooked. Otherwise return 0. */
205 static int
207 {
212 }
214 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
215 == MIPS_ABI_EABI32 \
216 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
218 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
219 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
221 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
222 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
224 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
226 /* Return the MIPS ABI associated with GDBARCH. */
227 enum mips_abi
229 {
231 }
233 int
235 {
238 /* If we know how big the registers are, use that size. */
242 /* Fall back to the previous behavior. */
245 }
247 /* Return the currently configured (or set) saved register size. */
249 unsigned int
251 {
253 {
266 }
267 }
269 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
270 are some functions to handle addresses associated with compressed
271 code including but not limited to testing, setting, or clearing
272 bit 0 of such addresses. */
274 /* Return one iff compressed code is the MIPS16 instruction set. */
276 static int
278 {
280 }
282 /* Return one iff compressed code is the microMIPS instruction set. */
284 static int
286 {
288 }
290 /* Return one iff ADDR denotes compressed code. */
292 static int
294 {
296 }
298 /* Return one iff ADDR denotes standard ISA code. */
300 static int
302 {
304 }
306 /* Return one iff ADDR denotes MIPS16 code. */
308 static int
310 {
312 }
314 /* Return one iff ADDR denotes microMIPS code. */
316 static int
318 {
320 }
322 /* Strip the ISA (compression) bit off from ADDR. */
324 static CORE_ADDR
326 {
328 }
330 /* Add the ISA (compression) bit to ADDR. */
332 static CORE_ADDR
334 {
336 }
338 /* Functions for setting and testing a bit in a minimal symbol that
339 marks it as MIPS16 or microMIPS function. The MSB of the minimal
340 symbol's "info" field is used for this purpose.
342 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
343 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
344 one of the "special" bits in a minimal symbol to mark it accordingly.
345 The test checks an ELF-private flag that is valid for true function
346 symbols only; in particular synthetic symbols such as for PLT stubs
347 have no ELF-private part at all.
349 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
350 in a minimal symbol. */
352 static void
354 {
364 }
366 /* Return one iff MSYM refers to standard ISA code. */
368 static int
370 {
372 }
374 /* Return one iff MSYM refers to MIPS16 code. */
376 static int
378 {
380 }
382 /* Return one iff MSYM refers to microMIPS code. */
384 static int
386 {
388 }
390 /* XFER a value from the big/little/left end of the register.
391 Depending on the size of the value it might occupy the entire
392 register or just part of it. Make an allowance for this, aligning
393 things accordingly. */
395 static void
400 {
404 /* Need to transfer the left or right part of the register, based on
405 the targets byte order. */
407 {
419 }
425 {
430 }
438 {
443 }
446 }
448 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
449 compatiblity mode. A return value of 1 means that we have
450 physical 64-bit registers, but should treat them as 32-bit registers. */
452 static int
454 {
456 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
457 meaningful. */
461 #if 0
462 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
463 in all the places we deal with FP registers. PR gdb/413. */
464 /* Otherwise check the FR bit in the status register - it controls
465 the FP compatiblity mode. If it is clear we are in compatibility
466 mode. */
469 #endif
472 }
474 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
480 /* The list of available "set mips " and "show mips " commands. */
485 /* Integer registers 0 thru 31 are handled explicitly by
486 mips_register_name(). Processor specific registers 32 and above
487 are listed in the following tables. */
489 enum
492 /* Generic MIPS. */
501 };
503 /* Names of IDT R3041 registers. */
514 };
516 /* Names of tx39 registers. */
527 };
529 /* Names of IRIX registers. */
536 };
538 /* Names of registers with Linux kernels. */
546 };
549 /* Return the name of the register corresponding to REGNO. */
552 {
554 /* GPR names for all ABIs other than n32/n64. */
560 };
562 /* GPR names for n32 and n64 ABIs. */
568 };
572 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
573 but then don't make the raw register names visible. This (upper)
574 range of user visible register numbers are the pseudo-registers.
576 This approach was adopted accommodate the following scenario:
577 It is possible to debug a 64-bit device using a 32-bit
578 programming model. In such instances, the raw registers are
579 configured to be 64-bits wide, while the pseudo registers are
580 configured to be 32-bits wide. The registers that the user
581 sees - the pseudo registers - match the users expectations
582 given the programming model being used. */
587 /* The MIPS integer registers are always mapped from 0 to 31. The
588 names of the registers (which reflects the conventions regarding
589 register use) vary depending on the ABI. */
591 {
594 else
596 }
600 {
605 }
606 else
609 }
611 /* Return the groups that a MIPS register can be categorised into. */
613 static int
616 {
626 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
627 (gdbarch), as not all architectures are multi-arch. */
638 /* Save the pseudo registers. Need to make certain that any code
639 extracting register values from a saved register cache also uses
640 pseudo registers. */
643 /* Restore the same pseudo register. */
647 }
649 /* Return the groups that a MIPS register can be categorised into.
650 This version is only used if we have a target description which
651 describes real registers (and their groups). */
653 static int
656 {
661 /* Only save, restore, and display the pseudo registers. Need to
662 make certain that any code extracting register values from a
663 saved register cache also uses pseudo registers.
665 Note: saving and restoring the pseudo registers is slightly
666 strange; if we have 64 bits, we should save and restore all
667 64 bits. But this is hard and has little benefit. */
676 }
678 /* Map the symbol table registers which live in the range [1 *
679 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
680 registers. Take care of alignment and size problems. */
682 static enum register_status
685 {
693 {
696 else
697 {
699 LONGEST regval;
706 }
707 }
708 else
710 }
712 static void
716 {
724 {
727 else
728 {
729 /* Sign extend the shortened version of the register prior
730 to placing it in the raw register. This is required for
731 some mips64 parts in order to avoid unpredictable behavior. */
735 }
736 }
737 else
739 }
741 static int
744 {
752 }
754 static int
757 {
762 {
766 {
769 {
772 }
775 }
776 }
777 else
781 }
783 /* Table to translate 3-bit register field to actual register number. */
786 /* Heuristic_proc_start may hunt through the text section for a long
787 time across a 2400 baud serial line. Allows the user to limit this
788 search. */
792 /* Number of bytes of storage in the actual machine representation for
793 register N. NOTE: This defines the pseudo register type so need to
794 rebuild the architecture vector. */
798 static void
801 {
804 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
805 instead of relying on globals. Doing that would let generic code
806 handle the search for this specific architecture. */
808 {
811 }
812 }
814 /* Convert to/from a register and the corresponding memory value. */
816 /* This predicate tests for the case of an 8 byte floating point
817 value that is being transferred to or from a pair of floating point
818 registers each of which are (or are considered to be) only 4 bytes
819 wide. */
820 static int
823 {
828 }
830 /* This predicate tests for the case of a value of less than 8
831 bytes in width that is being transfered to or from an 8 byte
832 general purpose register. */
833 static int
836 {
842 }
844 static int
847 {
850 }
852 static int
856 {
860 {
873 }
875 {
877 CORE_ADDR offset;
886 }
887 else
888 {
891 }
892 }
894 static void
897 {
901 {
904 }
906 {
910 /* Sign extend values, irrespective of type, that are stored to
911 a 64-bit general purpose register. (32-bit unsigned values
912 are stored as signed quantities within a 64-bit register.
913 When performing an operation, in compiled code, that combines
914 a 32-bit unsigned value with a signed 64-bit value, a type
915 conversion is first performed that zeroes out the high 32 bits.) */
917 {
920 else
924 }
925 else
926 {
929 else
933 }
934 }
935 else
936 {
939 }
940 }
942 /* Return the GDB type object for the "standard" data type of data in
943 register REG. */
947 {
950 {
951 /* The floating-point registers raw, or cooked, always match
952 mips_isa_regsize(), and also map 1:1, byte for byte. */
955 else
957 }
959 {
960 /* The raw or ISA registers. These are all sized according to
961 the ISA regsize. */
964 else
966 }
967 else
968 {
971 /* The cooked or ABI registers. These are sized according to
972 the ABI (with a few complications). */
980 /* The pseudo/cooked view of the embedded registers is always
981 32-bit. The raw view is handled below. */
984 /* The target, while possibly using a 64-bit register buffer,
985 is only transfering 32-bits of each integer register.
986 Reflect this in the cooked/pseudo (ABI) register value. */
989 /* The ABI is restricted to 32-bit registers (the ISA could be
990 32- or 64-bit). */
992 else
993 /* 64-bit ABI. */
995 }
996 }
998 /* Return the GDB type for the pseudo register REGNUM, which is the
999 ABI-level view. This function is only called if there is a target
1000 description which includes registers, so we know precisely the
1001 types of hardware registers. */
1005 {
1012 /* Absent registers are still absent. */
1018 /* Present the floating point registers however the hardware did;
1019 do not try to convert between FPU layouts. */
1022 /* Use pointer types for registers if we can. For n32 we can not,
1023 since we do not have a 64-bit pointer type. */
1026 {
1032 }
1050 {
1051 /* The pseudo/cooked view of embedded registers is always
1052 32-bit, even if the target transfers 64-bit values for them.
1053 New targets relying on XML descriptions should only transfer
1054 the necessary 32 bits, but older versions of GDB expected 64,
1055 so allow the target to provide 64 bits without interfering
1056 with the displayed type. */
1058 }
1060 /* For all other registers, pass through the hardware type. */
1062 }
1064 /* Should the upper word of 64-bit addresses be zeroed? */
1067 static int
1069 {
1071 {
1083 }
1084 }
1086 static void
1089 {
1094 {
1102 printf_filtered
1109 }
1110 }
1112 /* Tell if the program counter value in MEMADDR is in a standard ISA
1113 function. */
1115 int
1117 {
1120 /* Flags indicating that this is a MIPS16 or microMIPS function is
1121 stored by elfread.c in the high bit of the info field. Use this
1122 to decide if the function is standard MIPS. Otherwise if bit 0
1123 of the address is clear, then this is a standard MIPS function. */
1127 else
1129 }
1131 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1133 int
1135 {
1138 /* A flag indicating that this is a MIPS16 function is stored by
1139 elfread.c in the high bit of the info field. Use this to decide
1140 if the function is MIPS16. Otherwise if bit 0 of the address is
1141 set, then ELF file flags will tell if this is a MIPS16 function. */
1145 else
1147 }
1149 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1151 int
1153 {
1156 /* A flag indicating that this is a microMIPS function is stored by
1157 elfread.c in the high bit of the info field. Use this to decide
1158 if the function is microMIPS. Otherwise if bit 0 of the address
1159 is set, then ELF file flags will tell if this is a microMIPS
1160 function. */
1164 else
1166 }
1168 /* Tell the ISA type of the function the program counter value in MEMADDR
1169 is in. */
1171 static enum mips_isa
1173 {
1176 /* A flag indicating that this is a MIPS16 or a microMIPS function
1177 is stored by elfread.c in the high bit of the info field. Use
1178 this to decide if the function is MIPS16 or microMIPS or normal
1179 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1180 flags will tell if this is a MIPS16 or a microMIPS function. */
1183 {
1188 else
1190 }
1191 else
1192 {
1197 else
1199 }
1200 }
1202 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1210 /* This is used as a PIC thunk prefix. */
1214 /* Return non-zero if the PC is inside a call thunk (aka stub or
1215 trampoline) that should be treated as a temporary frame. */
1217 static int
1219 {
1220 CORE_ADDR start_addr;
1223 /* Find the starting address of the function containing the PC. */
1227 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1231 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1234 /* If the PC is in __fn_stub_*, this is a call stub. */
1239 }
1241 /* MIPS believes that the PC has a sign extended value. Perhaps the
1242 all registers should be sign extended for simplicity? */
1244 static CORE_ADDR
1246 {
1248 ULONGEST pc;
1254 }
1256 static CORE_ADDR
1258 {
1259 CORE_ADDR pc;
1264 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1265 intermediate frames. In this case we can get the caller's address
1266 from $ra, or if $ra contains an address within a thunk as well, then
1267 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1268 and thus the caller's address is in $s2. */
1270 {
1271 pc = frame_unwind_register_signed
1276 {
1277 pc = frame_unwind_register_signed
1281 }
1282 }
1284 }
1286 static CORE_ADDR
1288 {
1289 return frame_unwind_register_signed
1291 }
1293 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1294 dummy frame. The frame ID's base needs to match the TOS value
1295 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1296 breakpoint. */
1298 static struct frame_id
1300 {
1301 return frame_id_build
1306 }
1308 /* Implement the "write_pc" gdbarch method. */
1310 void
1312 {
1317 else
1319 }
1321 /* Fetch and return instruction from the specified location. Handle
1322 MIPS16/microMIPS as appropriate. */
1324 static ULONGEST
1327 {
1334 {
1346 }
1351 {
1355 }
1357 }
1359 /* These are the fields of 32 bit mips instructions. */
1360 #define mips32_op(x) (x >> 26)
1361 #define itype_op(x) (x >> 26)
1362 #define itype_rs(x) ((x >> 21) & 0x1f)
1363 #define itype_rt(x) ((x >> 16) & 0x1f)
1364 #define itype_immediate(x) (x & 0xffff)
1366 #define jtype_op(x) (x >> 26)
1367 #define jtype_target(x) (x & 0x03ffffff)
1369 #define rtype_op(x) (x >> 26)
1370 #define rtype_rs(x) ((x >> 21) & 0x1f)
1371 #define rtype_rt(x) ((x >> 16) & 0x1f)
1372 #define rtype_rd(x) ((x >> 11) & 0x1f)
1373 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1374 #define rtype_funct(x) (x & 0x3f)
1376 /* MicroMIPS instruction fields. */
1377 #define micromips_op(x) ((x) >> 10)
1379 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1380 bit and the size respectively of the field extracted. */
1381 #define b0s4_imm(x) ((x) & 0xf)
1382 #define b0s5_imm(x) ((x) & 0x1f)
1383 #define b0s5_reg(x) ((x) & 0x1f)
1384 #define b0s7_imm(x) ((x) & 0x7f)
1385 #define b0s10_imm(x) ((x) & 0x3ff)
1386 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1387 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1388 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1389 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1390 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1391 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1392 #define b6s4_op(x) (((x) >> 6) & 0xf)
1393 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1395 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1396 respectively of the field extracted. */
1397 #define b0s6_op(x) ((x) & 0x3f)
1398 #define b0s11_op(x) ((x) & 0x7ff)
1399 #define b0s12_imm(x) ((x) & 0xfff)
1400 #define b0s16_imm(x) ((x) & 0xffff)
1401 #define b0s26_imm(x) ((x) & 0x3ffffff)
1402 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1403 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1404 #define b12s4_op(x) (((x) >> 12) & 0xf)
1406 /* Return the size in bytes of the instruction INSN encoded in the ISA
1407 instruction set. */
1409 static int
1411 {
1413 {
1420 else
1425 else
1429 }
1431 }
1433 static LONGEST
1435 {
1437 }
1439 /* Determine the address of the next instruction executed after the INST
1440 floating condition branch instruction at PC. COUNT specifies the
1441 number of the floating condition bits tested by the branch. */
1443 static CORE_ADDR
1446 {
1451 ULONGEST fcs;
1455 /* No way to handle; it'll most likely trap anyway. */
1463 else
1467 }
1469 /* Determine where to set a single step breakpoint while considering
1470 branch prediction. */
1471 static CORE_ADDR
1473 {
1479 instruction. */
1480 {
1482 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1483 {
1486 {
1497 }
1498 }
1500 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1504 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1508 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1511 /* JALX: 011101 */
1512 /* The new PC will be alternate mode. */
1513 {
1517 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1519 }
1520 else
1522 }
1523 else
1526 /* Further subdivide into SPECIAL, REGIMM and other. */
1528 {
1532 {
1535 /* Set PC to that address. */
1539 {
1545 else
1547 }
1551 }
1555 {
1558 {
1563 less_branch:
1566 else
1575 else
1582 {
1587 /* No way to handle; it'll most likely trap anyway. */
1593 else
1595 }
1597 /* All of the other instructions in the REGIMM category */
1600 }
1601 }
1605 {
1608 /* Upper four bits get never changed... */
1610 }
1613 equal_branch:
1617 else
1621 neq_branch:
1625 else
1631 else
1639 else
1647 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1648 INSN. */
1650 static LONGEST
1652 {
1654 }
1656 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1657 INSN. */
1659 static LONGEST
1661 {
1663 }
1665 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1666 INSN. */
1668 static LONGEST
1670 {
1672 }
1674 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1676 static int
1678 {
1679 ULONGEST insn;
1683 }
1685 /* Calculate the address of the next microMIPS instruction to execute
1686 after the INSN coprocessor 1 conditional branch instruction at the
1687 address PC. COUNT denotes the number of coprocessor condition bits
1688 examined by the branch. */
1690 static CORE_ADDR
1693 {
1698 ULONGEST fcs;
1702 /* No way to handle; it'll most likely trap anyway. */
1710 else
1714 }
1716 /* Calculate the address of the next microMIPS instruction to execute
1717 after the instruction at the address PC. */
1719 static CORE_ADDR
1721 {
1723 ULONGEST insn;
1728 {
1729 /* 48-bit instructions. */
1731 /* No branch or jump instructions in this category. */
1735 /* 32-bit instructions. */
1741 {
1744 /* POOL32Axf: bits 000000 ... 111100 */
1746 /* JALR, JALR.HB: 000000 000x111100 111100 */
1747 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1753 {
1760 else
1770 else
1778 else
1792 else
1805 /* BC2F, BC2T: don't know how to handle these. */
1811 {
1816 /* No way to handle; it'll most likely trap anyway. */
1822 else
1824 }
1828 /* BC1ANY2F: bits 010000 11100 xxx01 */
1830 /* BC1ANY2T: bits 010000 11101 xxx01 */
1841 }
1854 else
1862 else
1869 }
1872 /* 16-bit instructions. */
1875 {
1878 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1881 /* JRADDIUSP: bits 010001 11000 */
1886 {
1891 else
1893 }
1897 {
1902 else
1904 }
1910 }
1912 }
1915 }
1917 /* Decoding the next place to set a breakpoint is irregular for the
1918 mips 16 variant, but fortunately, there fewer instructions. We have
1919 to cope ith extensions for 16 bit instructions and a pair of actual
1920 32 bit instructions. We dont want to set a single step instruction
1921 on the extend instruction either. */
1923 /* Lots of mips16 instruction formats */
1924 /* Predicting jumps requires itype,ritype,i8type
1925 and their extensions extItype,extritype,extI8type. */
1926 enum mips16_inst_fmts
1927 {
1949 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1950 };
1951 /* I am heaping all the fields of the formats into one structure and
1952 then, only the fields which are involved in instruction extension. */
1953 struct upk_mips16
1954 {
1955 CORE_ADDR offset;
1958 };
1961 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1962 for the bits which make up the immediate extension. */
1964 static CORE_ADDR
1966 {
1967 CORE_ADDR value;
1976 }
1978 /* Only call this function if you know that this is an extendable
1979 instruction. It won't malfunction, but why make excess remote memory
1980 references? If the immediate operands get sign extended or something,
1981 do it after the extension is performed. */
1982 /* FIXME: Every one of these cases needs to worry about sign extension
1983 when the offset is to be used in relative addressing. */
1985 static unsigned int
1987 {
1993 }
1995 static void
2000 {
2001 CORE_ADDR offset;
2005 {
2007 {
2008 CORE_ADDR value;
2010 {
2013 }
2014 else
2015 {
2018 }
2022 }
2027 /* Most of the fields are the same as I type but the
2028 immediate value is of a different length. */
2029 CORE_ADDR value;
2031 {
2034 }
2035 else
2036 {
2039 }
2044 }
2046 {
2052 /* Low bit still set. */
2058 }
2061 }
2065 }
2068 static CORE_ADDR
2070 {
2072 }
2074 static CORE_ADDR
2077 {
2081 {
2083 {
2088 }
2090 instructions. */
2091 {
2097 else
2100 }
2102 {
2109 else
2112 }
2114 {
2121 else
2124 }
2126 {
2130 /* upk.regx contains the opcode */
2134 /* pc = add_offset_16(pc,upk.offset) ; */
2136 else
2139 }
2141 {
2143 /* upk.fmt = rrtype; */
2146 {
2152 else
2155 }
2156 else
2159 }
2161 /* This is an instruction extension. Fetch the real instruction
2162 (which follows the extension) and decode things based on
2163 that. */
2164 {
2169 }
2171 {
2174 }
2175 }
2177 }
2179 static CORE_ADDR
2181 {
2185 }
2187 /* The mips_next_pc function supports single_step when the remote
2188 target monitor or stub is not developed enough to do a single_step.
2189 It works by decoding the current instruction and predicting where a
2190 branch will go. This isnt hard because all the data is available.
2191 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2192 static CORE_ADDR
2194 {
2201 else
2203 }
2205 struct mips_frame_cache
2206 {
2207 CORE_ADDR base;
2209 };
2211 /* Set a register's saved stack address in temp_saved_regs. If an
2212 address has already been set for this register, do nothing; this
2213 way we will only recognize the first save of a given register in a
2214 function prologue.
2216 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2217 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2218 Strictly speaking, only the second range is used as it is only second
2219 range (the ABI instead of ISA registers) that comes into play when finding
2220 saved registers in a frame. */
2222 static void
2225 {
2228 {
2233 }
2234 }
2237 /* Fetch the immediate value from a MIPS16 instruction.
2238 If the previous instruction was an EXTEND, use it to extend
2239 the upper bits of the immediate value. This is a helper function
2240 for mips16_scan_prologue. */
2242 static int
2248 {
2252 {
2257 }
2258 else
2259 {
2268 }
2269 }
2272 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2273 the associated FRAME_CACHE if not null.
2274 Return the address of the first instruction past the prologue. */
2276 static CORE_ADDR
2281 {
2282 CORE_ADDR cur_pc;
2284 CORE_ADDR sp;
2298 /* Can be called when there's no process, and hence when there's no
2299 THIS_FRAME. */
2304 else
2311 {
2312 /* Save the previous instruction. If it's an EXTEND, we'll extract
2313 the immediate offset extension from it in mips16_get_imm. */
2316 /* Fetch and decode the instruction. */
2320 /* Normally we ignore extend instructions. However, if it is
2321 not followed by a valid prologue instruction, then this
2322 instruction is not part of the prologue either. We must
2323 remember in this case to adjust the end_prologue_addr back
2324 over the extend. */
2326 {
2329 }
2336 {
2340 else
2341 /* Exit loop if a positive stack adjustment is found, which
2342 usually means that the stack cleanup code in the function
2343 epilogue is reached. */
2345 }
2347 {
2351 }
2353 {
2357 }
2359 {
2362 }
2364 {
2367 }
2369 {
2372 }
2374 {
2379 }
2381 {
2385 }
2387 {
2391 }
2396 {
2400 }
2404 {
2405 /* This instruction is part of the prologue, but we don't
2406 need to do anything special to handle it. */
2407 }
2408 else
2409 {
2410 /* This instruction is not an instruction typically found
2411 in a prologue, so we must have reached the end of the
2412 prologue. */
2415 }
2416 }
2418 /* The entry instruction is typically the first instruction in a function,
2419 and it stores registers at offsets relative to the value of the old SP
2420 (before the prologue). But the value of the sp parameter to this
2421 function is the new SP (after the prologue has been executed). So we
2422 can't calculate those offsets until we've seen the entire prologue,
2423 and can calculate what the old SP must have been. */
2425 {
2429 /* The entry instruction always subtracts 32 from the SP. */
2432 /* Now we can calculate what the SP must have been at the
2433 start of the function prologue. */
2436 /* Check if a0-a3 were saved in the caller's argument save area. */
2438 {
2441 }
2443 /* Check if the ra register was pushed on the stack. */
2446 {
2449 }
2451 /* Check if the s0 and s1 registers were pushed on the stack. */
2453 {
2456 }
2457 }
2459 /* The SAVE instruction is similar to ENTRY, except that defined by the
2460 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2461 size of the frame is specified as an immediate field of instruction
2462 and an extended variation exists which lets additional registers and
2463 frame space to be specified. The instruction always treats registers
2464 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2466 {
2470 };
2474 };
2482 {
2485 }
2487 {
2490 }
2492 /* For standard SAVE the frame size of 0 means 128. */
2499 /* Now we can calculate what the SP must have been at the
2500 start of the function prologue. */
2503 /* Check if A0-A3 were saved in the caller's argument save area. */
2505 {
2508 }
2512 /* Check if the RA register was pushed on the stack. */
2514 {
2517 }
2519 /* Check if the S8 register was pushed on the stack. */
2521 {
2524 xsregs--;
2525 }
2526 /* Check if S2-S7 were pushed on the stack. */
2528 {
2531 }
2533 /* Check if the S1 register was pushed on the stack. */
2535 {
2538 }
2539 /* Check if the S0 register was pushed on the stack. */
2541 {
2544 }
2546 /* Check if A0-A3 were pushed on the stack. */
2548 {
2551 }
2552 }
2555 {
2560 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2561 be able to get rid of the assignment below, evetually. But it's
2562 still needed for now. */
2566 }
2568 /* If we didn't reach the end of the prologue when scanning the function
2569 instructions, then set end_prologue_addr to the address of the
2570 instruction immediately after the last one we scanned. */
2575 }
2577 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2578 Procedures that use the 32-bit instruction set are handled by the
2579 mips_insn32 unwinder. */
2583 {
2593 /* Analyze the function prologue. */
2594 {
2596 CORE_ADDR start_addr;
2601 /* We can't analyze the prologue if we couldn't find the begining
2602 of the function. */
2607 }
2609 /* gdbarch_sp_regnum contains the value and not the address. */
2615 }
2617 static void
2620 {
2622 this_cache);
2623 /* This marks the outermost frame. */
2627 }
2632 {
2634 this_cache);
2636 }
2638 static int
2641 {
2647 }
2650 {
2651 NORMAL_FRAME,
2652 default_frame_unwind_stop_reason,
2653 mips_insn16_frame_this_id,
2654 mips_insn16_frame_prev_register,
2655 NULL,
2656 mips_insn16_frame_sniffer
2657 };
2659 static CORE_ADDR
2662 {
2664 this_cache);
2666 }
2669 {
2671 mips_insn16_frame_base_address,
2672 mips_insn16_frame_base_address,
2673 mips_insn16_frame_base_address
2674 };
2678 {
2683 else
2685 }
2687 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2688 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2689 interpreted directly, and then multiplied by 4. */
2691 static int
2693 {
2698 }
2700 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2701 the address of the first instruction past the prologue. */
2703 static CORE_ADDR
2708 {
2717 CORE_ADDR prev_pc;
2718 CORE_ADDR cur_pc;
2720 CORE_ADDR sp;
2734 /* Can be called when there's no process, and hence when there's no
2735 THIS_FRAME. */
2740 else
2747 /* Permit at most one non-prologue non-control-transfer instruction
2748 in the middle which may have been reordered by the compiler for
2749 optimisation. */
2751 {
2758 {
2759 /* 48-bit instructions. */
2761 /* No prologue instructions in this category. */
2766 /* 32-bit instructions. */
2773 {
2774 /* Record $sp/$fp adjustment. */
2775 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2783 /* SUBU: bits 000000 00111010000 */
2784 /* DSUBU: bits 010110 00111010000 */
2787 /* (D)SUBU $sp, $v1 */
2790 /* ADDU: bits 000000 00101010000 */
2791 /* DADDU: bits 010110 00101010000 */
2802 /* SWP: bits 001000 1001 */
2803 /* SDP: bits 001000 1100 */
2805 /* S[DW]P reg,offset($sp) */
2806 {
2812 }
2814 /* SWM: bits 001000 1101 */
2815 /* SDM: bits 001000 1111 */
2817 /* SWM reglist,offset($sp) */
2820 {
2831 }
2832 else
2836 /* Record $sp/$fp adjustment. */
2837 /* Discard (D)ADDIU $gp used for PIC code. */
2844 /* (D)ADDIU $sp, imm */
2847 /* (D)ADDIU $fp, $sp, imm */
2848 {
2852 }
2854 /* (D)ADDIU $gp, imm */
2858 /* LUI $v1 is used for larger $sp adjustments. */
2859 /* Discard LUI $gp is used for PIC code. */
2862 /* LUI: bits 010000 001101 */
2864 /* LUI $v1, imm */
2867 /* LUI: bits 010000 001101 */
2869 /* LUI $gp, imm */
2873 /* ORI $v1 is used for larger $sp adjustments. */
2878 /* ORI $v1, imm */
2880 else
2888 /* S[DW]C1 reg,offset($sp) */
2898 /* S[DW] reg,offset($sp) */
2900 else
2907 }
2910 /* 16-bit instructions. */
2913 {
2918 /* MOVE $fp, $sp */
2919 {
2922 }
2924 /* MOVE reg, $a0-$a3 */
2930 /* SWM: bits 010001 0101 */
2931 {
2938 }
2939 else
2945 /* ADDIUSP: bits 010011 1 */
2948 /* ADDIUS5: bits 010011 0 */
2949 /* ADDIUS5 $sp, imm */
2951 else
2964 }
2966 }
2971 /* Enough non-prologue insns seen or positive stack adjustment? */
2973 {
2976 }
2979 }
2982 {
2987 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2988 be able to get rid of the assignment below, evetually. But it's
2989 still needed for now. */
2993 }
2995 /* If we didn't reach the end of the prologue when scanning the function
2996 instructions, then set end_prologue_addr to the address of the
2997 instruction immediately after the last one we scanned. Unless the
2998 last one looked like a non-prologue instruction (and we looked ahead),
2999 in which case use its address instead. */
3004 }
3006 /* Heuristic unwinder for procedures using microMIPS instructions.
3007 Procedures that use the 32-bit instruction set are handled by the
3008 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3012 {
3023 /* Analyze the function prologue. */
3024 {
3026 CORE_ADDR start_addr;
3031 /* We can't analyze the prologue if we couldn't find the begining
3032 of the function. */
3037 }
3039 /* gdbarch_sp_regnum contains the value and not the address. */
3045 }
3047 static void
3050 {
3052 this_cache);
3053 /* This marks the outermost frame. */
3057 }
3062 {
3064 this_cache);
3066 }
3068 static int
3071 {
3078 }
3081 {
3082 NORMAL_FRAME,
3083 default_frame_unwind_stop_reason,
3084 mips_micro_frame_this_id,
3085 mips_micro_frame_prev_register,
3086 NULL,
3087 mips_micro_frame_sniffer
3088 };
3090 static CORE_ADDR
3093 {
3095 this_cache);
3097 }
3100 {
3102 mips_micro_frame_base_address,
3103 mips_micro_frame_base_address,
3104 mips_micro_frame_base_address
3105 };
3109 {
3115 else
3117 }
3119 /* Mark all the registers as unset in the saved_regs array
3120 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3122 static void
3124 {
3128 {
3133 {
3135 }
3136 }
3137 }
3139 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3140 the associated FRAME_CACHE if not null.
3141 Return the address of the first instruction past the prologue. */
3143 static CORE_ADDR
3148 {
3149 CORE_ADDR cur_pc;
3151 frame-pointer. */
3152 CORE_ADDR sp;
3162 /* Can be called when there's no process, and hence when there's no
3163 THIS_FRAME. */
3168 else
3174 restart:
3178 {
3182 /* Fetch the instruction. */
3186 /* Save some code by pre-extracting some useful fields. */
3194 {
3197 else
3198 /* Exit loop if a positive stack adjustment is found, which
3199 usually means that the stack cleanup code in the function
3200 epilogue is reached. */
3203 }
3206 {
3208 }
3211 {
3212 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3214 }
3216 {
3217 /* Old gcc frame, r30 is virtual frame pointer. */
3221 {
3225 frame_addr = get_frame_register_signed
3230 {
3231 /* FP > SP + frame_size. This may be because of
3232 an alloca or somethings similar. Fix sp to
3233 "pre-alloca" value, and try again. */
3235 /* Need to reset the status of all registers. Otherwise,
3236 we will hit a guard that prevents the new address
3237 for each register to be recomputed during the second
3238 pass. */
3241 }
3242 }
3243 }
3244 /* move $30,$sp. With different versions of gas this will be either
3245 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3246 Accept any one of these. */
3248 {
3249 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3251 {
3255 frame_addr = get_frame_register_signed
3260 {
3261 /* FP > SP + frame_size. This may be because of
3262 an alloca or somethings similar. Fix sp to
3263 "pre-alloca" value, and try again. */
3265 /* Need to reset the status of all registers. Otherwise,
3266 we will hit a guard that prevents the new address
3267 for each register to be recomputed during the second
3268 pass. */
3271 }
3272 }
3273 }
3276 {
3278 }
3286 )
3287 {
3288 /* These instructions are part of the prologue, but we don't
3289 need to do anything special to handle them. */
3290 }
3291 /* The instructions below load $at or $t0 with an immediate
3292 value in preparation for a stack adjustment via
3293 subu $sp,$sp,[$at,$t0]. These instructions could also
3294 initialize a local variable, so we accept them only before
3295 a stack adjustment instruction was seen. */
3303 ))
3304 {
3307 }
3308 else
3309 {
3310 /* This instruction is not an instruction typically found
3311 in a prologue, so we must have reached the end of the
3312 prologue. */
3313 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
3314 loop now? Why would we need to continue scanning the function
3315 instructions? */
3319 /* Check for branches and jumps. For now, only jump to
3320 register are caught (i.e. returns). */
3323 }
3325 /* If the previous instruction was a jump, we must have reached
3326 the end of the prologue by now. Stop scanning so that we do
3327 not go past the function return. */
3330 }
3333 {
3338 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3339 this assignment below, eventually. But it's still needed
3340 for now. */
3345 }
3347 /* If we didn't reach the end of the prologue when scanning the function
3348 instructions, then set end_prologue_addr to the address of the
3349 instruction immediately after the last one we scanned. */
3350 /* brobecker/2004-10-10: I don't think this would ever happen, but
3351 we may as well be careful and do our best if we have a null
3352 end_prologue_addr. */
3356 /* In a frameless function, we might have incorrectly
3357 skipped some load immediate instructions. Undo the skipping
3358 if the load immediate was not followed by a stack adjustment. */
3363 }
3365 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3366 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3367 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3368 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3372 {
3383 /* Analyze the function prologue. */
3384 {
3386 CORE_ADDR start_addr;
3391 /* We can't analyze the prologue if we couldn't find the begining
3392 of the function. */
3397 }
3399 /* gdbarch_sp_regnum contains the value and not the address. */
3405 }
3407 static void
3410 {
3412 this_cache);
3413 /* This marks the outermost frame. */
3417 }
3422 {
3424 this_cache);
3426 }
3428 static int
3431 {
3436 }
3439 {
3440 NORMAL_FRAME,
3441 default_frame_unwind_stop_reason,
3442 mips_insn32_frame_this_id,
3443 mips_insn32_frame_prev_register,
3444 NULL,
3445 mips_insn32_frame_sniffer
3446 };
3448 static CORE_ADDR
3451 {
3453 this_cache);
3455 }
3458 {
3460 mips_insn32_frame_base_address,
3461 mips_insn32_frame_base_address,
3462 mips_insn32_frame_base_address
3463 };
3467 {
3471 else
3473 }
3477 {
3478 CORE_ADDR pc;
3479 CORE_ADDR start_addr;
3480 CORE_ADDR stack_addr;
3490 /* The return address is in the link register. */
3495 /* Frame ID, since it's a frameless / stackless function, no stack
3496 space is allocated and SP on entry is the current SP. */
3503 /* Assume that the frame's base is the same as the
3504 stack-pointer. */
3508 }
3510 static void
3513 {
3517 }
3522 {
3526 }
3528 static int
3531 {
3537 /* Use the stub unwinder for unreadable code. */
3544 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
3552 /* Calling a PIC function from a non-PIC function passes through a
3553 stub. The stub for foo is named ".pic.foo". */
3561 }
3564 {
3565 NORMAL_FRAME,
3566 default_frame_unwind_stop_reason,
3567 mips_stub_frame_this_id,
3568 mips_stub_frame_prev_register,
3569 NULL,
3570 mips_stub_frame_sniffer
3571 };
3573 static CORE_ADDR
3576 {
3580 }
3583 {
3585 mips_stub_frame_base_address,
3586 mips_stub_frame_base_address,
3587 mips_stub_frame_base_address
3588 };
3592 {
3595 else
3597 }
3599 /* mips_addr_bits_remove - remove useless address bits */
3601 static CORE_ADDR
3603 {
3610 /* This hack is a work-around for existing boards using PMON, the
3611 simulator, and any other 64-bit targets that doesn't have true
3612 64-bit addressing. On these targets, the upper 32 bits of
3613 addresses are ignored by the hardware. Thus, the PC or SP are
3614 likely to have been sign extended to all 1s by instruction
3615 sequences that load 32-bit addresses. For example, a typical
3616 piece of code that loads an address is this:
3618 lui $r2, <upper 16 bits>
3619 ori $r2, <lower 16 bits>
3621 But the lui sign-extends the value such that the upper 32 bits
3622 may be all 1s. The workaround is simply to mask off these
3623 bits. In the future, gcc may be changed to support true 64-bit
3624 addressing, and this masking will have to be disabled. */
3626 else
3628 }
3631 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3632 instruction and ending with a SC/SCD instruction. If such a sequence
3633 is found, attempt to step through it. A breakpoint is placed at the end of
3634 the sequence. */
3636 /* Instructions used during single-stepping of atomic sequences, standard
3637 ISA version. */
3638 #define LL_OPCODE 0x30
3639 #define LLD_OPCODE 0x34
3640 #define SC_OPCODE 0x38
3641 #define SCD_OPCODE 0x3c
3643 static int
3646 {
3650 ULONGEST insn;
3657 /* Assume all atomic sequences start with a ll/lld instruction. */
3661 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3662 instructions. */
3664 {
3669 /* Assume that there is at most one branch in the atomic
3670 sequence. If a branch is found, put a breakpoint in its
3671 destination address. */
3673 {
3701 /* Fall through. */
3706 }
3708 {
3712 standard single-step code. */
3714 last_breakpoint++;
3715 }
3719 }
3721 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3727 /* Insert a breakpoint right after the end of the atomic sequence. */
3730 /* Check for duplicated breakpoints. Check also for a breakpoint
3731 placed (branch instruction's destination) in the atomic sequence. */
3735 /* Effectively inserts the breakpoints. */
3740 }
3742 static int
3745 CORE_ADDR pc)
3746 {
3753 ULONGEST insn;
3757 /* Assume all atomic sequences start with a ll/lld instruction. */
3768 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3769 that no atomic sequence is longer than "atomic_sequence_length"
3770 instructions. */
3774 {
3780 /* Assume that there is at most one conditional branch in the
3781 atomic sequence. If a branch is found, put a breakpoint in
3782 its destination address. */
3784 {
3785 /* 48-bit instructions. */
3790 /* 32-bit instructions. */
3793 {
3796 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3797 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3799 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3802 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3804 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3807 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3810 /* BC1ANY*: bits 010000 111xx xxx01 */
3812 /* Fall through. */
3829 /* POOL32Axf: bits 000000 ... 111100 */
3831 /* JALR, JALR.HB: 000000 000x111100 111100 */
3832 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3834 /* Fall through. */
3844 /* SC, SCD: bits 011000 1x11 */
3847 }
3851 /* 16-bit instructions. */
3854 {
3863 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
3865 /* JRADDIUSP: bits 010001 11000 */
3871 }
3873 }
3875 {
3878 standard single-step code. */
3880 last_breakpoint++;
3881 }
3882 }
3886 /* Insert a breakpoint right after the end of the atomic sequence. */
3889 /* Check for duplicated breakpoints. Check also for a breakpoint
3890 placed (branch instruction's destination) in the atomic sequence */
3894 /* Effectively inserts the breakpoints. */
3899 }
3901 static int
3904 {
3909 else
3911 }
3913 /* mips_software_single_step() is called just before we want to resume
3914 the inferior, if we want to single-step it but there is no hardware
3915 or kernel single-step support (MIPS on GNU/Linux for example). We find
3916 the target of the coming instruction and breakpoint it. */
3918 int
3920 {
3933 }
3935 /* Test whether the PC points to the return instruction at the
3936 end of a function. */
3938 static int
3940 {
3941 ULONGEST insn;
3942 ULONGEST hint;
3944 /* This used to check for MIPS16, but this piece of code is never
3945 called for MIPS16 functions. And likewise microMIPS ones. */
3951 }
3954 /* This fencepost looks highly suspicious to me. Removing it also
3955 seems suspicious as it could affect remote debugging across serial
3956 lines. */
3958 static CORE_ADDR
3960 {
3961 CORE_ADDR start_pc;
3962 CORE_ADDR fence;
3980 /* Search back for previous return. */
3983 {
3984 /* It's not clear to me why we reach this point when
3985 stop_soon, but with this test, at least we
3986 don't print out warnings for every child forked (eg, on
3987 decstation). 22apr93 rich@cygnus.com. */
3989 {
3996 {
3997 /* This actually happens frequently in embedded
3998 development, when you first connect to a board
3999 and your stack pointer and pc are nowhere in
4000 particular. This message needs to give people
4001 in that situation enough information to
4002 determine that it's no big deal. */
4016 }
4017 }
4020 }
4022 {
4025 /* On MIPS16, any one of the following is likely to be the
4026 start of a function:
4027 extend save
4028 save
4029 entry
4030 addiu sp,-n
4031 daddiu sp,-n
4032 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4035 {
4037 {
4042 }
4044 }
4054 else
4056 }
4058 {
4059 ULONGEST insn;
4065 /* On microMIPS, any one of the following is likely to be the
4066 start of a function:
4067 ADDIUSP -imm
4068 (D)ADDIU $sp, -imm
4069 LUI $gp, imm */
4072 {
4082 /* (D)ADDIU $sp, imm */
4089 /* LUI: bits 010000 001101 */
4091 /* LUI $gp, imm */
4097 /* ADDIUSP: bits 010011 1 */
4098 {
4101 /* ADDIUSP -imm */
4103 }
4104 else
4105 /* ADDIUS5: bits 010011 0 */
4106 {
4110 /* ADDIUS5 $sp, -imm */
4112 }
4114 }
4117 }
4119 {
4120 /* Skip return and its delay slot. */
4123 }
4126 }
4128 struct mips_objfile_private
4129 {
4130 bfd_size_type size;
4132 };
4134 /* According to the current ABI, should the type be passed in a
4135 floating-point register (assuming that there is space)? When there
4136 is no FPU, FP are not even considered as possible candidates for
4137 FP registers and, consequently this returns false - forces FP
4138 arguments into integer registers. */
4140 static int
4143 {
4152 }
4154 /* On o32, argument passing in GPRs depends on the alignment of the type being
4155 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4157 static int
4159 {
4165 {
4169 }
4171 {
4179 }
4181 }
4183 /* Adjust the address downward (direction of stack growth) so that it
4184 is correctly aligned for a new stack frame. */
4185 static CORE_ADDR
4187 {
4189 }
4191 /* Implement the "push_dummy_code" gdbarch method. */
4193 static CORE_ADDR
4199 {
4201 CORE_ADDR nop_addr;
4202 CORE_ADDR bp_slot;
4204 /* Reserve enough room on the stack for our breakpoint instruction. */
4207 /* Return to microMIPS mode if calling microMIPS code to avoid
4208 triggering an address error exception on processors that only
4209 support microMIPS execution. */
4213 /* The breakpoint layer automatically adjusts the address of
4214 breakpoints inserted in a branch delay slot. With enough
4215 bad luck, the 4 bytes located just before our breakpoint
4216 instruction could look like a branch instruction, and thus
4217 trigger the adjustement, and break the function call entirely.
4218 So, we reserve those 4 bytes and write a nop instruction
4219 to prevent that from happening. */
4224 /* Inferior resumes at the function entry point. */
4228 }
4230 static CORE_ADDR
4235 {
4245 /* For shared libraries, "t9" needs to point at the function
4246 address. */
4249 /* Set the return address register to point to the entry point of
4250 the program, where a breakpoint lies in wait. */
4253 /* First ensure that the stack and structure return address (if any)
4254 are properly aligned. The stack has to be at least 64-bit
4255 aligned even on 32-bit machines, because doubles must be 64-bit
4256 aligned. For n32 and n64, stack frames need to be 128-bit
4257 aligned, so we round to this widest known alignment. */
4262 /* Now make space on the stack for the args. We allocate more
4263 than necessary for EABI, because the first few arguments are
4264 passed in registers, but that's OK. */
4274 /* Initialize the integer and float register pointers. */
4278 /* The struct_return pointer occupies the first parameter-passing reg. */
4280 {
4283 "mips_eabi_push_dummy_call: "
4287 }
4289 /* Now load as many as possible of the first arguments into
4290 registers, and push the rest onto the stack. Loop thru args
4291 from first to last. */
4293 {
4306 /* Function pointer arguments to mips16 code need to be made into
4307 mips16 pointers. */
4310 {
4315 else
4316 {
4320 }
4321 }
4322 /* The EABI passes structures that do not fit in a register by
4323 reference. */
4326 {
4334 }
4335 else
4338 /* 32-bit ABIs always start floating point arguments in an
4339 even-numbered floating point register. Round the FP register
4340 up before the check to see if there are any FP registers
4341 left. Non MIPS_EABI targets also pass the FP in the integer
4342 registers so also round up normal registers. */
4344 {
4346 float_argreg++;
4347 }
4349 /* Floating point arguments passed in registers have to be
4350 treated specially. On 32-bit architectures, doubles
4351 are passed in register pairs; the even register gets
4352 the low word, and the odd register gets the high word.
4353 On non-EABI processors, the first two floating point arguments are
4354 also copied to general registers, because MIPS16 functions
4355 don't use float registers for arguments. This duplication of
4356 arguments in general registers can't hurt non-MIPS16 functions
4357 because those registers are normally skipped. */
4358 /* MIPS_EABI squeezes a struct that contains a single floating
4359 point value into an FP register instead of pushing it onto the
4360 stack. */
4363 {
4364 /* EABI32 will pass doubles in consecutive registers, even on
4365 64-bit cores. At one time, we used to check the size of
4366 `float_argreg' to determine whether or not to pass doubles
4367 in consecutive registers, but this is not sufficient for
4368 making the ABI determination. */
4370 {
4375 /* Write the low word of the double to the even register(s). */
4383 /* Write the high word of the double to the odd register(s). */
4390 }
4391 else
4392 {
4393 /* This is a floating point value that fits entirely
4394 in a single register. */
4395 /* On 32 bit ABI's the float_argreg is further adjusted
4396 above to ensure that it is even register aligned. */
4402 }
4403 }
4404 else
4405 {
4406 /* Copy the argument to general registers or the stack in
4407 register-sized pieces. Large arguments are split between
4408 registers and stack. */
4409 /* Note: structs whose size is not a multiple of regsize
4410 are treated specially: Irix cc passes
4411 them in registers where gcc sometimes puts them on the
4412 stack. For maximum compatibility, we will put them in
4413 both places. */
4416 /* Note: Floating-point values that didn't fit into an FP
4417 register are only written to memory. */
4419 {
4420 /* Remember if the argument was written to the stack. */
4426 partial_len);
4428 /* Write this portion of the argument to the stack. */
4430 || odd_sized_struct
4432 {
4433 /* Should shorter than int integer values be
4434 promoted to int before being stored? */
4436 CORE_ADDR addr;
4439 {
4449 }
4452 {
4457 }
4462 {
4467 {
4470 }
4471 }
4473 }
4475 /* Note!!! This is NOT an else clause. Odd sized
4476 structs may go thru BOTH paths. Floating point
4477 arguments will not. */
4478 /* Write this portion of the argument to a general
4479 purpose register. */
4482 {
4483 LONGEST regval =
4488 argreg,
4491 argreg++;
4492 }
4497 /* Compute the offset into the stack at which we will
4498 copy the next parameter.
4500 In the new EABI (and the NABI32), the stack_offset
4501 only needs to be adjusted when it has been used. */
4505 }
4506 }
4509 }
4513 /* Return adjusted stack pointer. */
4515 }
4517 /* Determine the return value convention being used. */
4519 static enum return_value_convention
4523 {
4531 /* Floating point type? */
4533 {
4536 /* Structs with a single field of float type
4537 are returned in a floating point register. */
4541 {
4546 }
4547 }
4550 {
4551 /* A floating-point value belongs in the least significant part
4552 of FP0/FP1. */
4556 }
4557 else
4558 {
4559 /* An integer value goes in V0/V1. */
4563 }
4567 {
4574 offset);
4575 }
4578 }
4581 /* N32/N64 ABI stuff. */
4583 /* Search for a naturally aligned double at OFFSET inside a struct
4584 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4585 registers. */
4587 static int
4590 {
4603 {
4607 /* We're only looking at normal fields. */
4612 /* If we have gone past the offset, there is no double to pass. */
4619 /* If this field is entirely before the requested offset, go
4620 on to the next one. */
4624 /* If this is our special aligned double, we can stop. */
4629 /* This field starts at or before the requested offset, and
4630 overlaps it. If it is a structure, recurse inwards. */
4632 }
4635 }
4637 static CORE_ADDR
4642 {
4651 /* For shared libraries, "t9" needs to point at the function
4652 address. */
4655 /* Set the return address register to point to the entry point of
4656 the program, where a breakpoint lies in wait. */
4659 /* First ensure that the stack and structure return address (if any)
4660 are properly aligned. The stack has to be at least 64-bit
4661 aligned even on 32-bit machines, because doubles must be 64-bit
4662 aligned. For n32 and n64, stack frames need to be 128-bit
4663 aligned, so we round to this widest known alignment. */
4668 /* Now make space on the stack for the args. */
4678 /* Initialize the integer and float register pointers. */
4682 /* The struct_return pointer occupies the first parameter-passing reg. */
4684 {
4687 "mips_n32n64_push_dummy_call: "
4691 }
4693 /* Now load as many as possible of the first arguments into
4694 registers, and push the rest onto the stack. Loop thru args
4695 from first to last. */
4697 {
4711 /* A 128-bit long double value requires an even-odd pair of
4712 floating-point registers. */
4716 {
4717 float_argreg++;
4718 argreg++;
4719 }
4723 {
4724 /* This is a floating point value that fits entirely
4725 in a single register or a pair of registers. */
4737 float_argreg++;
4738 argreg++;
4740 {
4752 float_argreg++;
4753 argreg++;
4754 }
4755 }
4756 else
4757 {
4758 /* Copy the argument to general registers or the stack in
4759 register-sized pieces. Large arguments are split between
4760 registers and stack. */
4761 /* For N32/N64, structs, unions, or other composite types are
4762 treated as a sequence of doublewords, and are passed in integer
4763 or floating point registers as though they were simple scalar
4764 parameters to the extent that they fit, with any excess on the
4765 stack packed according to the normal memory layout of the
4766 object.
4767 The caller does not reserve space for the register arguments;
4768 the callee is responsible for reserving it if required. */
4769 /* Note: Floating-point values that didn't fit into an FP
4770 register are only written to memory. */
4772 {
4773 /* Remember if the argument was written to the stack. */
4779 partial_len);
4784 /* Write this portion of the argument to the stack. */
4786 {
4787 /* Should shorter than int integer values be
4788 promoted to int before being stored? */
4790 CORE_ADDR addr;
4793 {
4798 }
4801 {
4806 }
4811 {
4816 {
4819 }
4820 }
4822 }
4824 /* Note!!! This is NOT an else clause. Odd sized
4825 structs may go thru BOTH paths. */
4826 /* Write this portion of the argument to a general
4827 purpose register. */
4829 {
4830 LONGEST regval;
4832 /* Sign extend pointers, 32-bit integers and signed
4833 16-bit and 8-bit integers; everything else is taken
4834 as is. */
4843 byte_order);
4844 else
4846 byte_order);
4848 /* A non-floating-point argument being passed in a
4849 general register. If a struct or union, and if
4850 the remaining length is smaller than the register
4851 size, we have to adjust the register value on
4852 big endian targets.
4854 It does not seem to be necessary to do the
4855 same for integral types. */
4866 argreg,
4872 {
4875 float_argreg,
4878 regval);
4879 }
4881 float_argreg++;
4882 argreg++;
4883 }
4888 /* Compute the offset into the stack at which we will
4889 copy the next parameter.
4891 In N32 (N64?), the stack_offset only needs to be
4892 adjusted when it has been used. */
4896 }
4897 }
4900 }
4904 /* Return adjusted stack pointer. */
4906 }
4908 static enum return_value_convention
4912 {
4915 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
4917 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
4918 if needed), as appropriate for the type. Composite results (struct,
4919 union, or array) are returned in $2/$f0 and $3/$f2 according to the
4920 following rules:
4922 * A struct with only one or two floating point fields is returned in $f0
4923 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
4924 case.
4926 * Any other composite results of at most 128 bits are returned in
4927 $2 (first 64 bits) and $3 (remainder, if necessary).
4929 * Larger composite results are handled by converting the function to a
4930 procedure with an implicit first parameter, which is a pointer to an area
4931 reserved by the caller to receive the result. [The o32-bit ABI requires
4932 that all composite results be handled by conversion to implicit first
4933 parameters. The MIPS/SGI Fortran implementation has always made a
4934 specific exception to return COMPLEX results in the floating point
4935 registers.] */
4942 {
4943 /* A 128-bit floating-point value fills both $f0 and $f2. The
4944 two registers are used in the same as memory order, so the
4945 eight bytes with the lower memory address are in $f0. */
4960 }
4963 {
4964 /* A single or double floating-point value that fits in FP0. */
4974 }
4986 {
4987 /* A struct that contains one or two floats. Each value is part
4988 in the least significant part of their floating point
4989 register (or GPR, for soft float). */
4996 {
5001 offset);
5003 {
5004 /* A 16-byte long double field goes in two consecutive
5005 registers. */
5016 }
5017 else
5023 }
5025 }
5029 {
5030 /* A composite type. Extract the left justified value,
5031 regardless of the byte order. I.e. DO NOT USE
5032 mips_xfer_lower. */
5038 {
5048 offset);
5049 }
5051 }
5052 else
5053 {
5054 /* A scalar extract each part but least-significant-byte
5055 justified. */
5061 {
5072 }
5074 }
5075 }
5077 /* Which registers to use for passing floating-point values between
5078 function calls, one of floating-point, general and both kinds of
5079 registers. O32 and O64 use different register kinds for standard
5080 MIPS and MIPS16 code; to make the handling of cases where we may
5081 not know what kind of code is being used (e.g. no debug information)
5082 easier we sometimes use both kinds. */
5084 enum mips_fval_reg
5085 {
5086 mips_fval_fpr,
5087 mips_fval_gpr,
5088 mips_fval_both
5089 };
5091 /* O32 ABI stuff. */
5093 static CORE_ADDR
5098 {
5107 /* For shared libraries, "t9" needs to point at the function
5108 address. */
5111 /* Set the return address register to point to the entry point of
5112 the program, where a breakpoint lies in wait. */
5115 /* First ensure that the stack and structure return address (if any)
5116 are properly aligned. The stack has to be at least 64-bit
5117 aligned even on 32-bit machines, because doubles must be 64-bit
5118 aligned. For n32 and n64, stack frames need to be 128-bit
5119 aligned, so we round to this widest known alignment. */
5124 /* Now make space on the stack for the args. */
5126 {
5130 /* Align to double-word if necessary. */
5133 /* Allocate space on the stack. */
5135 }
5143 /* Initialize the integer and float register pointers. */
5147 /* The struct_return pointer occupies the first parameter-passing reg. */
5149 {
5152 "mips_o32_push_dummy_call: "
5157 }
5159 /* Now load as many as possible of the first arguments into
5160 registers, and push the rest onto the stack. Loop thru args
5161 from first to last. */
5163 {
5177 /* 32-bit ABIs always start floating point arguments in an
5178 even-numbered floating point register. Round the FP register
5179 up before the check to see if there are any FP registers
5180 left. O32 targets also pass the FP in the integer registers
5181 so also round up normal registers. */
5183 {
5185 float_argreg++;
5186 }
5188 /* Floating point arguments passed in registers have to be
5189 treated specially. On 32-bit architectures, doubles are
5190 passed in register pairs; the even FP register gets the
5191 low word, and the odd FP register gets the high word.
5192 On O32, the first two floating point arguments are also
5193 copied to general registers, following their memory order,
5194 because MIPS16 functions don't use float registers for
5195 arguments. This duplication of arguments in general
5196 registers can't hurt non-MIPS16 functions, because those
5197 registers are normally skipped. */
5201 {
5203 {
5208 /* First word. */
5216 regval);
5222 /* Second word. */
5230 regval);
5235 }
5236 else
5237 {
5238 /* This is a floating point value that fits entirely
5239 in a single register. */
5240 /* On 32 bit ABI's the float_argreg is further adjusted
5241 above to ensure that it is even register aligned. */
5248 /* Although two FP registers are reserved for each
5249 argument, only one corresponding integer register is
5250 reserved. */
5255 }
5256 /* Reserve space for the FP register. */
5258 }
5259 else
5260 {
5261 /* Copy the argument to general registers or the stack in
5262 register-sized pieces. Large arguments are split between
5263 registers and stack. */
5264 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5265 are treated specially: Irix cc passes
5266 them in registers where gcc sometimes puts them on the
5267 stack. For maximum compatibility, we will put them in
5268 both places. */
5271 /* Structures should be aligned to eight bytes (even arg registers)
5272 on MIPS_ABI_O32, if their first member has double precision. */
5274 {
5276 {
5277 argreg++;
5279 }
5280 }
5282 {
5283 /* Remember if the argument was written to the stack. */
5289 partial_len);
5291 /* Write this portion of the argument to the stack. */
5294 {
5295 /* Should shorter than int integer values be
5296 promoted to int before being stored? */
5298 CORE_ADDR addr;
5302 {
5307 }
5312 {
5317 {
5320 }
5321 }
5323 }
5325 /* Note!!! This is NOT an else clause. Odd sized
5326 structs may go thru BOTH paths. */
5327 /* Write this portion of the argument to a general
5328 purpose register. */
5330 {
5332 byte_order);
5333 /* Value may need to be sign extended, because
5334 mips_isa_regsize() != mips_abi_regsize(). */
5336 /* A non-floating-point argument being passed in a
5337 general register. If a struct or union, and if
5338 the remaining length is smaller than the register
5339 size, we have to adjust the register value on
5340 big endian targets.
5342 It does not seem to be necessary to do the
5343 same for integral types.
5345 Also don't do this adjustment on O64 binaries.
5347 cagney/2001-07-23: gdb/179: Also, GCC, when
5348 outputting LE O32 with sizeof (struct) <
5349 mips_abi_regsize(), generates a left shift
5350 as part of storing the argument in a register
5351 (the left shift isn't generated when
5352 sizeof (struct) >= mips_abi_regsize()). Since
5353 it is quite possible that this is GCC
5354 contradicting the LE/O32 ABI, GDB has not been
5355 adjusted to accommodate this. Either someone
5356 needs to demonstrate that the LE/O32 ABI
5357 specifies such a left shift OR this new ABI gets
5358 identified as such and GDB gets tweaked
5359 accordingly. */
5370 argreg,
5373 argreg++;
5375 /* Prevent subsequent floating point arguments from
5376 being passed in floating point registers. */
5378 }
5383 /* Compute the offset into the stack at which we will
5384 copy the next parameter.
5386 In older ABIs, the caller reserved space for
5387 registers that contained arguments. This was loosely
5388 refered to as their "home". Consequently, space is
5389 always allocated. */
5392 }
5393 }
5396 }
5400 /* Return adjusted stack pointer. */
5402 }
5404 static enum return_value_convention
5408 {
5421 {
5422 /* A single-precision floating-point value. If reading in or copying,
5423 then we get it from/put it to FP0 for standard MIPS code or GPR2
5424 for MIPS16 code. If writing out only, then we put it to both FP0
5425 and GPR2. We do not support reading in with no function known, if
5426 this safety check ever triggers, then we'll have to try harder. */
5430 {
5440 }
5455 }
5458 {
5459 /* A double-precision floating-point value. If reading in or copying,
5460 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5461 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5462 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5463 no function known, if this safety check ever triggers, then we'll
5464 have to try harder. */
5468 {
5479 }
5481 {
5482 /* The most significant part goes in FP1, and the least significant
5483 in FP0. */
5485 {
5512 }
5513 }
5515 {
5516 /* The two 32-bit parts are always placed in GPR2 and GPR3
5517 following these registers' memory order. */
5526 }
5528 }
5529 #if 0
5542 {
5543 /* A struct that contains one or two floats. Each value is part
5544 in the least significant part of their floating point
5545 register.. */
5551 {
5556 offset);
5562 }
5564 }
5565 #endif
5566 #if 0
5569 {
5570 /* A structure or union. Extract the left justified value,
5571 regardless of the byte order. I.e. DO NOT USE
5572 mips_xfer_lower. */
5578 {
5588 }
5590 }
5591 #endif
5592 else
5593 {
5594 /* A scalar extract each part but least-significant-byte
5595 justified. o32 thinks registers are 4 byte, regardless of
5596 the ISA. */
5602 {
5613 }
5615 }
5616 }
5618 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5619 ABI. */
5621 static CORE_ADDR
5627 {
5636 /* For shared libraries, "t9" needs to point at the function
5637 address. */
5640 /* Set the return address register to point to the entry point of
5641 the program, where a breakpoint lies in wait. */
5644 /* First ensure that the stack and structure return address (if any)
5645 are properly aligned. The stack has to be at least 64-bit
5646 aligned even on 32-bit machines, because doubles must be 64-bit
5647 aligned. For n32 and n64, stack frames need to be 128-bit
5648 aligned, so we round to this widest known alignment. */
5653 /* Now make space on the stack for the args. */
5655 {
5659 /* Allocate space on the stack. */
5661 }
5669 /* Initialize the integer and float register pointers. */
5673 /* The struct_return pointer occupies the first parameter-passing reg. */
5675 {
5678 "mips_o64_push_dummy_call: "
5683 }
5685 /* Now load as many as possible of the first arguments into
5686 registers, and push the rest onto the stack. Loop thru args
5687 from first to last. */
5689 {
5704 /* Function pointer arguments to mips16 code need to be made into
5705 mips16 pointers. */
5708 {
5712 {
5716 }
5717 }
5719 /* Floating point arguments passed in registers have to be
5720 treated specially. On 32-bit architectures, doubles are
5721 passed in register pairs; the even FP register gets the
5722 low word, and the odd FP register gets the high word.
5723 On O64, the first two floating point arguments are also
5724 copied to general registers, because MIPS16 functions
5725 don't use float registers for arguments. This duplication
5726 of arguments in general registers can't hurt non-MIPS16
5727 functions because those registers are normally skipped. */
5731 {
5741 argreg++;
5742 /* Reserve space for the FP register. */
5744 }
5745 else
5746 {
5747 /* Copy the argument to general registers or the stack in
5748 register-sized pieces. Large arguments are split between
5749 registers and stack. */
5750 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5751 are treated specially: Irix cc passes them in registers
5752 where gcc sometimes puts them on the stack. For maximum
5753 compatibility, we will put them in both places. */
5757 {
5758 /* Remember if the argument was written to the stack. */
5764 partial_len);
5766 /* Write this portion of the argument to the stack. */
5769 {
5770 /* Should shorter than int integer values be
5771 promoted to int before being stored? */
5773 CORE_ADDR addr;
5776 {
5782 }
5785 {
5790 }
5795 {
5800 {
5803 }
5804 }
5806 }
5808 /* Note!!! This is NOT an else clause. Odd sized
5809 structs may go thru BOTH paths. */
5810 /* Write this portion of the argument to a general
5811 purpose register. */
5813 {
5815 byte_order);
5816 /* Value may need to be sign extended, because
5817 mips_isa_regsize() != mips_abi_regsize(). */
5819 /* A non-floating-point argument being passed in a
5820 general register. If a struct or union, and if
5821 the remaining length is smaller than the register
5822 size, we have to adjust the register value on
5823 big endian targets.
5825 It does not seem to be necessary to do the
5826 same for integral types. */
5837 argreg,
5840 argreg++;
5842 /* Prevent subsequent floating point arguments from
5843 being passed in floating point registers. */
5845 }
5850 /* Compute the offset into the stack at which we will
5851 copy the next parameter.
5853 In older ABIs, the caller reserved space for
5854 registers that contained arguments. This was loosely
5855 refered to as their "home". Consequently, space is
5856 always allocated. */
5859 }
5860 }
5863 }
5867 /* Return adjusted stack pointer. */
5869 }
5871 static enum return_value_convention
5875 {
5887 {
5888 /* A floating-point value. If reading in or copying, then we get it
5889 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
5890 If writing out only, then we put it to both FP0 and GPR2. We do
5891 not support reading in with no function known, if this safety
5892 check ever triggers, then we'll have to try harder. */
5896 {
5906 }
5921 }
5922 else
5923 {
5924 /* A scalar extract each part but least-significant-byte
5925 justified. */
5931 {
5942 }
5944 }
5945 }
5947 /* Floating point register management.
5949 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
5950 64bit operations, these early MIPS cpus treat fp register pairs
5951 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
5952 registers and offer a compatibility mode that emulates the MIPS2 fp
5953 model. When operating in MIPS2 fp compat mode, later cpu's split
5954 double precision floats into two 32-bit chunks and store them in
5955 consecutive fp regs. To display 64-bit floats stored in this
5956 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
5957 Throw in user-configurable endianness and you have a real mess.
5959 The way this works is:
5960 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
5961 double-precision value will be split across two logical registers.
5962 The lower-numbered logical register will hold the low-order bits,
5963 regardless of the processor's endianness.
5964 - If we are on a 64-bit processor, and we are looking for a
5965 single-precision value, it will be in the low ordered bits
5966 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
5967 save slot in memory.
5968 - If we are in 64-bit mode, everything is straightforward.
5970 Note that this code only deals with "live" registers at the top of the
5971 stack. We will attempt to deal with saved registers later, when
5972 the raw/cooked register interface is in place. (We need a general
5973 interface that can deal with dynamic saved register sizes -- fp
5974 regs could be 32 bits wide in one frame and 64 on the frame above
5975 and below). */
5977 /* Copy a 32-bit single-precision value from the current frame
5978 into rare_buffer. */
5980 static void
5983 {
5992 {
5993 /* We have a 64-bit value for this register. Find the low-order
5994 32 bits. */
5999 else
6003 }
6004 else
6005 {
6007 }
6008 }
6010 /* Copy a 64-bit double-precision value from the current frame into
6011 rare_buffer. This may include getting half of it from the next
6012 register. */
6014 static void
6017 {
6022 {
6023 /* We have a 64-bit value for this register, and we should use
6024 all 64 bits. */
6028 }
6029 else
6030 {
6038 /* mips_read_fp_register_single will find the correct 32 bits from
6039 each register. */
6041 {
6044 }
6045 else
6046 {
6049 }
6050 }
6051 }
6053 static void
6071 {
6074 /* 4-byte registers: Print hex and floating. Also print even
6075 numbered registers as doubles. */
6088 else
6092 {
6100 else
6102 }
6103 }
6104 else
6105 {
6108 /* Eight byte registers: print each one as hex, float and double. */
6125 else
6131 else
6133 }
6134 }
6136 static void
6139 {
6145 {
6148 }
6152 {
6156 }
6160 /* The problem with printing numeric register names (r26, etc.) is that
6161 the user can't use them on input. Probably the best solution is to
6162 fix it so that either the numeric or the funky (a2, etc.) names
6163 are accepted on input. */
6166 else
6173 val,
6175 }
6177 /* Replacement for generic do_registers_info.
6178 Print regs in pretty columns. */
6180 static int
6183 {
6188 }
6191 /* Print a row's worth of GP (int) registers, with name labels above. */
6193 static int
6196 {
6198 /* Do values for GP (int) regs. */
6201 per row. */
6205 /* For GP registers, we print a separate row of names above the vals. */
6209 regnum++)
6210 {
6215 /* Large registers are handled separately. */
6217 {
6221 /* Print this register on a row by itself. */
6225 }
6231 col++;
6232 }
6237 /* Print the R0 to R31 names. */
6241 else
6244 /* Now print the values in hex, 4 or 8 to the row. */
6248 regnum++)
6249 {
6257 /* OK: get the data in raw format. */
6261 /* pad small registers */
6266 /* Now print the register value in hex, endian order. */
6272 else
6277 col++;
6278 }
6283 }
6285 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6287 static void
6290 {
6292 {
6299 }
6300 else
6301 /* Do all (or most) registers. */
6302 {
6306 {
6308 {
6311 else
6313 }
6314 else
6316 }
6317 }
6318 }
6320 static int
6323 {
6328 ULONGEST insn;
6341 /* _has_delay_slot above will have validated the read. */
6346 }
6348 /* To skip prologues, I use this predicate. Returns either PC itself
6349 if the code at PC does not look like a function prologue; otherwise
6350 returns an address that (if we're lucky) follows the prologue. If
6351 LENIENT, then we must skip everything which is involved in setting
6352 up the frame (it's OK to skip more, just so long as we don't skip
6353 anything which might clobber the registers which are being saved.
6354 We must skip more in the case where part of the prologue is in the
6355 delay slot of a non-prologue instruction). */
6357 static CORE_ADDR
6359 {
6360 CORE_ADDR limit_pc;
6361 CORE_ADDR func_addr;
6363 /* See if we can determine the end of the prologue via the symbol table.
6364 If so, then return either PC, or the PC after the prologue, whichever
6365 is greater. */
6367 {
6368 CORE_ADDR post_prologue_pc
6372 }
6374 /* Can't determine prologue from the symbol table, need to examine
6375 instructions. */
6377 /* Find an upper limit on the function prologue using the debug
6378 information. If the debug information could not be used to provide
6379 that bound, then use an arbitrary large number as the upper bound. */
6388 else
6390 }
6392 /* Check whether the PC is in a function epilogue (32-bit version).
6393 This is a helper function for mips_in_function_epilogue_p. */
6394 static int
6396 {
6400 {
6401 /* The MIPS epilogue is max. 12 bytes long. */
6410 {
6422 }
6425 }
6428 }
6430 /* Check whether the PC is in a function epilogue (microMIPS version).
6431 This is a helper function for mips_in_function_epilogue_p. */
6433 static int
6435 {
6438 CORE_ADDR addr;
6439 ULONGEST insn;
6448 /* The microMIPS epilogue is max. 12 bytes long. */
6457 {
6462 {
6463 /* 48-bit instructions. */
6465 /* No epilogue instructions in this category. */
6468 /* 32-bit instructions. */
6475 {
6482 /* (D)ADDIU $sp, imm */
6489 }
6492 /* 16-bit instructions. */
6495 {
6500 /* MOVE $zero, $zero aka NOP */
6506 /* JRADDIUSP: bits 010011 11000 */
6508 /* JRC: bits 010011 01101 */
6510 /* JRC $ra */
6517 /* ADDIUSP: bits 010011 1 */
6524 }
6525 }
6526 }
6529 }
6531 /* Check whether the PC is in a function epilogue (16-bit version).
6532 This is a helper function for mips_in_function_epilogue_p. */
6533 static int
6535 {
6539 {
6540 /* The MIPS epilogue is max. 12 bytes long. */
6549 {
6563 }
6566 }
6569 }
6571 /* The epilogue is defined here as the area at the end of a function,
6572 after an instruction which destroys the function's stack frame. */
6573 static int
6575 {
6580 else
6582 }
6584 /* Root of all "set mips "/"show mips " commands. This will eventually be
6585 used for all MIPS-specific commands. */
6587 static void
6589 {
6591 }
6593 static void
6595 {
6596 printf_unfiltered
6599 }
6601 /* Commands to show/set the MIPS FPU type. */
6603 static void
6605 {
6609 {
6610 printf_unfiltered
6614 }
6617 {
6629 }
6633 fpu);
6634 else
6635 printf_unfiltered
6637 }
6640 static void
6642 {
6646 }
6648 static void
6650 {
6655 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6656 instead of relying on globals. Doing that would let generic code
6657 handle the search for this specific architecture. */
6660 }
6662 static void
6664 {
6669 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6670 instead of relying on globals. Doing that would let generic code
6671 handle the search for this specific architecture. */
6674 }
6676 static void
6678 {
6683 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6684 instead of relying on globals. Doing that would let generic code
6685 handle the search for this specific architecture. */
6688 }
6690 static void
6692 {
6694 }
6696 /* Attempt to identify the particular processor model by reading the
6697 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6698 the relevant processor still exists (it dates back to '94) and
6699 secondly this is not the way to do this. The processor type should
6700 be set by forcing an architecture change. */
6702 void
6704 {
6708 ULONGEST prid;
6713 }
6715 /* Just like reinit_frame_cache, but with the right arguments to be
6716 callable as an sfunc. */
6718 static void
6721 {
6723 }
6725 static int
6727 {
6730 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6731 disassembler needs to be able to locally determine the ISA, and
6732 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6733 work. */
6739 /* Round down the instruction address to the appropriate boundary. */
6743 /* Set the disassembler options. */
6745 /* This string is not recognized explicitly by the disassembler,
6746 but it tells the disassembler to not try to guess the ABI from
6747 the bfd elf headers, such that, if the user overrides the ABI
6748 of a program linked as NewABI, the disassembly will follow the
6749 register naming conventions specified by the user. */
6752 /* Call the appropriate disassembler based on the target endian-ness. */
6755 else
6757 }
6759 static int
6761 {
6762 /* Set up the disassembler info, so that we get the right
6763 register names from libopcodes. */
6768 }
6770 static int
6772 {
6773 /* Set up the disassembler info, so that we get the right
6774 register names from libopcodes. */
6779 }
6781 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6782 program counter value to determine whether a 16- or 32-bit breakpoint
6783 should be used. It returns a pointer to a string of bytes that encode a
6784 breakpoint instruction, stores the length of the string to *lenptr, and
6785 adjusts pc (if necessary) to point to the actual memory location where
6786 the breakpoint should be inserted. */
6791 {
6795 {
6797 {
6802 }
6804 {
6807 ULONGEST insn;
6818 }
6819 else
6820 {
6821 /* The IDT board uses an unusual breakpoint value, and
6822 sometimes gets confused when it sees the usual MIPS
6823 breakpoint instruction. */
6827 /* Likewise, IRIX appears to expect a different breakpoint,
6828 although this is not apparent until you try to use pthreads. */
6841 else
6843 }
6844 }
6845 else
6846 {
6848 {
6853 }
6855 {
6858 ULONGEST insn;
6869 }
6870 else
6871 {
6884 else
6886 }
6887 }
6888 }
6890 /* Determine the remote breakpoint kind suitable for the PC. The following
6891 kinds are used:
6893 * 2 -- 16-bit MIPS16 mode breakpoint,
6895 * 3 -- 16-bit microMIPS mode breakpoint,
6897 * 4 -- 32-bit standard MIPS mode breakpoint,
6899 * 5 -- 32-bit microMIPS mode breakpoint. */
6901 static void
6904 {
6908 {
6911 }
6913 {
6914 ULONGEST insn;
6922 }
6923 else
6925 }
6927 /* Return non-zero if the ADDR instruction has a branch delay slot
6928 (i.e. it is a jump or branch instruction). This function is based
6929 on mips32_next_pc. */
6931 static int
6933 {
6946 {
6953 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
6955 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
6957 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
6958 }
6959 else
6961 {
6971 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
6972 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
6974 /* BPOSGE32, BPOSGE64: bits 1110x */
6979 }
6980 }
6982 /* Return non-zero if the ADDR instruction, which must be a 32-bit
6983 instruction if MUSTBE32 is set or can be any instruction otherwise,
6984 has a branch delay slot (i.e. it is a non-compact jump instruction). */
6986 static int
6989 {
6990 ULONGEST insn;
6999 /* POOL16C: bits 010001 */
7001 /* JR16: bits 010001 01100 */
7003 /* JALR16, JALRS16: bits 010001 0111x */
7005 /* BEQZ16, BNEZ16: bits 10x011 */
7007 /* B16: bits 110011 */
7009 /* 32-bit instructions. */
7011 /* POOL32A: bits 000000 */
7012 {
7018 /* POOL32Axf: bits 000000 ... 111100 */
7020 /* JALR, JALR.HB: 000000 000x111100 111100 */
7021 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7022 }
7025 /* POOL32I: bits 010000 */
7027 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7029 /* BLEZ, BGTZ: bits 010000 001x0 */
7031 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7034 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7036 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7039 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7042 /* BC1ANY*: bits 010000 111xx xxx01 */
7044 /* JALS, JAL: bits x11101 */
7046 /* BEQ, BNE: bits 10x101 */
7048 /* J: bits 110101 */
7050 /* JALX: bits 111100 */
7051 }
7053 static int
7056 {
7067 }
7069 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7070 This assumes KSSEG exists. */
7072 static CORE_ADDR
7074 {
7079 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7080 a compiler warning produced where CORE_ADDR is a 32-bit type even
7081 though in that case this is dead code). */
7083 {
7087 else
7096 }
7099 else
7103 }
7105 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7106 it backwards if necessary. Return the address of the new location. */
7108 static CORE_ADDR
7110 {
7111 CORE_ADDR prev_addr;
7112 CORE_ADDR boundary;
7113 CORE_ADDR func_addr;
7115 /* If a breakpoint is set on the instruction in a branch delay slot,
7116 GDB gets confused. When the breakpoint is hit, the PC isn't on
7117 the instruction in the branch delay slot, the PC will point to
7118 the branch instruction. Since the PC doesn't match any known
7119 breakpoints, GDB reports a trap exception.
7121 There are two possible fixes for this problem.
7123 1) When the breakpoint gets hit, see if the BD bit is set in the
7124 Cause register (which indicates the last exception occurred in a
7125 branch delay slot). If the BD bit is set, fix the PC to point to
7126 the instruction in the branch delay slot.
7128 2) When the user sets the breakpoint, don't allow him to set the
7129 breakpoint on the instruction in the branch delay slot. Instead
7130 move the breakpoint to the branch instruction (which will have
7131 the same result).
7133 The problem with the first solution is that if the user then
7134 single-steps the processor, the branch instruction will get
7135 skipped (since GDB thinks the PC is on the instruction in the
7136 branch delay slot).
7138 So, we'll use the second solution. To do this we need to know if
7139 the instruction we're trying to set the breakpoint on is in the
7140 branch delay slot. */
7144 /* Make sure we don't scan back before the beginning of the current
7145 function, since we may fetch constant data or insns that look like
7146 a jump. Of course we might do that anyway if the compiler has
7147 moved constants inline. :-( */
7153 {
7157 /* If the previous instruction has a branch delay slot, we have
7158 to move the breakpoint to the branch instruction. */
7162 }
7163 else
7164 {
7171 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7172 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7173 so try for that first, then try the 2 byte JALR/JR.
7174 The microMIPS ASE has a whole range of jumps and branches
7175 with delay slots, some of which take 4 bytes and some take
7176 2 bytes, so the idea is the same.
7177 FIXME: We have to assume that bpaddr is not the second half
7178 of an extended instruction. */
7180 ? micromips_instruction_has_delay_slot
7186 {
7191 /* Looks like a JR/JALR at [target-1], but it could be
7192 the second word of a previous JAL/JALX, so record it
7193 and check back one more. */
7196 {
7198 /* Looks like a JAL/JALX at [target-2], but it could also
7199 be the second word of a previous JAL/JALX, record it,
7200 and check back one more. */
7202 else
7203 /* Looks like a JAL/JALX at [target-3], so any previously
7204 recorded JAL/JALX or JR/JALR must be wrong, because:
7206 >-3: JAL
7207 -2: JAL-ext (can't be JAL/JALX)
7208 -1: bdslot (can't be JR/JALR)
7209 0: target insn
7211 Of course it could be another JAL-ext which looks
7212 like a JAL, but in that case we'd have broken out
7213 of this loop at [target-2]:
7215 -4: JAL
7216 >-3: JAL-ext
7217 -2: bdslot (can't be jmp)
7218 -1: JR/JALR
7219 0: target insn */
7221 }
7222 else
7223 {
7224 /* Not a jump instruction: if we're at [target-1] this
7225 could be the second word of a JAL/JALX, so continue;
7226 otherwise we're done. */
7229 }
7230 }
7234 }
7237 }
7239 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7240 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7242 static int
7244 {
7246 {
7258 }
7259 }
7261 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7262 call stubs, one of sf, df, sc, or dc. */
7264 static int
7266 {
7269 }
7271 /* Code at PC is a compiler-generated stub. Such a stub for a function
7272 bar might have a name like __fn_stub_bar, and might look like this:
7274 mfc1 $4, $f13
7275 mfc1 $5, $f12
7276 mfc1 $6, $f15
7277 mfc1 $7, $f14
7279 followed by (or interspersed with):
7281 j bar
7283 or:
7285 lui $25, %hi(bar)
7286 addiu $25, $25, %lo(bar)
7287 jr $25
7289 ($1 may be used in old code; for robustness we accept any register)
7290 or, in PIC code:
7292 lui $28, %hi(_gp_disp)
7293 addiu $28, $28, %lo(_gp_disp)
7294 addu $28, $28, $25
7295 lw $25, %got(bar)
7296 addiu $25, $25, %lo(bar)
7297 jr $25
7299 In the case of a __call_stub_bar stub, the sequence to set up
7300 arguments might look like this:
7302 mtc1 $4, $f13
7303 mtc1 $5, $f12
7304 mtc1 $6, $f15
7305 mtc1 $7, $f14
7307 followed by (or interspersed with) one of the jump sequences above.
7309 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7310 of J or JR, respectively, followed by:
7312 mfc1 $2, $f0
7313 mfc1 $3, $f1
7314 jr $18
7316 We are at the beginning of the stub here, and scan down and extract
7317 the target address from the jump immediate instruction or, if a jump
7318 register instruction is used, from the register referred. Return
7319 the value of PC calculated or 0 if inconclusive.
7321 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7323 static CORE_ADDR
7325 {
7339 {
7341 CORE_ADDR imm;
7347 {
7350 {
7369 }
7382 {
7388 }
7397 {
7400 }
7408 {
7415 }
7417 }
7418 }
7421 }
7423 /* If PC is in a MIPS16 call or return stub, return the address of the
7424 target PC, which is either the callee or the caller. There are several
7425 cases which must be handled:
7427 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7428 and the target PC is in $31 ($ra).
7429 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7430 and the target PC is in $2.
7431 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7432 i.e. before the JALR instruction, this is effectively a call stub
7433 and the target PC is in $2. Otherwise this is effectively
7434 a return stub and the target PC is in $18.
7435 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7436 JAL or JALR instruction, this is effectively a call stub and the
7437 target PC is buried in the instruction stream. Otherwise this
7438 is effectively a return stub and the target PC is in $18.
7439 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7440 stub and the target PC is buried in the instruction stream.
7442 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7443 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7444 gory details. */
7446 static CORE_ADDR
7448 {
7450 CORE_ADDR start_addr;
7454 /* Find the starting address and name of the function containing the PC. */
7458 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7459 and the target PC is in $31 ($ra). */
7464 return get_frame_register_signed
7467 /* If the PC is in __mips16_call_stub_*, this is one of the call
7468 call/return stubs. */
7471 {
7472 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7473 and the target PC is in $2. */
7475 return get_frame_register_signed
7478 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7479 i.e. before the JALR instruction, this is effectively a call stub
7480 and the target PC is in $2. Otherwise this is effectively
7481 a return stub and the target PC is in $18. */
7485 {
7487 /* This is the 'call' part of a call stub. The return
7488 address is in $2. */
7489 return get_frame_register_signed
7491 else
7492 /* This is the 'return' part of a call stub. The return
7493 address is in $18. */
7494 return get_frame_register_signed
7496 }
7497 else
7499 }
7501 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7502 compiler-generated call or call/return stubs. */
7505 {
7507 /* This is the 'call' part of a call stub. Call this helper
7508 to scan through this code for interesting instructions
7509 and determine the final PC. */
7511 else
7512 /* This is the 'return' part of a call stub. The return address
7513 is in $18. */
7514 return get_frame_register_signed
7516 }
7519 }
7521 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7522 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7524 static int
7526 {
7527 CORE_ADDR start_addr;
7530 /* Find the starting address of the function containing the PC. */
7534 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7535 the start, i.e. after the JALR instruction, this is effectively
7536 a return stub. */
7545 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7546 the JAL or JALR instruction, this is effectively a return stub. */
7552 /* Consume the .pic. prefix of any PIC stub, this function must return
7553 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7554 or the call stub path will trigger in handle_inferior_event causing
7555 it to go astray. */
7560 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7568 }
7570 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7571 PC of the stub target. The stub just loads $t9 and jumps to it,
7572 so that $t9 has the correct value at function entry. */
7574 static CORE_ADDR
7576 {
7584 /* The stub for foo is named ".pic.foo", and is either two
7585 instructions inserted before foo or a three instruction sequence
7586 which jumps to foo. */
7594 /* A two-instruction header. */
7598 /* A three-instruction (plus delay slot) trampoline. */
7600 {
7607 /* A stub contains these instructions:
7608 lui t9, %hi(target)
7609 j target
7610 addiu t9, t9, %lo(target)
7611 nop
7613 This works even for N64, since stubs are only generated with
7614 -msym32. */
7621 }
7623 /* Not a recognized stub. */
7625 }
7627 static CORE_ADDR
7629 {
7631 CORE_ADDR target_pc;
7632 CORE_ADDR new_pc;
7634 do
7635 {
7640 {
7644 }
7648 {
7652 }
7656 {
7660 }
7661 }
7665 }
7667 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7668 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7670 static int
7672 {
7684 else
7685 /* This will hopefully (eventually) provoke a warning. Should
7686 we be calling complaint() here? */
7689 }
7692 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7693 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7695 static int
7697 {
7709 else
7710 /* This will hopefully (eventually) provoke a warning. Should we
7711 be calling complaint() here? */
7714 }
7716 static int
7718 {
7719 /* Only makes sense to supply raw registers. */
7721 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7722 decide if it is valid. Should instead define a standard sim/gdb
7723 register numbering scheme. */
7730 else
7732 }
7735 /* Convert an integer into an address. Extracting the value signed
7736 guarantees a correctly sign extended address. */
7738 static CORE_ADDR
7741 {
7744 }
7746 /* Dummy virtual frame pointer method. This is no more or less accurate
7747 than most other architectures; we just need to be explicit about it,
7748 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7749 an assertion failure. */
7751 static void
7754 {
7757 }
7759 static void
7761 {
7783 else
7785 }
7787 static void
7789 {
7799 }
7801 static enum mips_abi
7803 {
7811 }
7813 /* Return the default compressed instruction set, either of MIPS16
7814 or microMIPS, selected when none could have been determined from
7815 the ELF header of the binary being executed (or no binary has been
7816 selected. */
7818 static enum mips_isa
7820 {
7828 }
7830 static void
7832 {
7833 /* If the size matches the set of 32-bit or 64-bit integer registers,
7834 assume that's what we've got. */
7838 /* If the size matches the full set of registers GDB traditionally
7839 knows about, including floating point, for either 32-bit or
7840 64-bit, assume that's what we've got. */
7844 /* Otherwise we don't have a useful guess. */
7845 }
7849 {
7852 }
7856 {
7871 /* Fill in the OS dependent register numbers and names. */
7873 {
7886 }
7888 {
7903 }
7904 else
7905 {
7920 else
7922 }
7924 /* Check any target description for validity. */
7926 {
7932 };
7938 };
7964 {
7967 }
7972 {
7975 }
7986 {
7989 }
7991 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
7992 backend is not prepared for that, though. */
7996 {
7999 }
8009 valid_p
8015 {
8018 }
8021 {
8024 /* The DSP registers are optional; it's OK if they are absent. */
8026 {
8046 {
8049 }
8053 }
8054 }
8056 /* It would be nice to detect an attempt to use a 64-bit ABI
8057 when only 32-bit registers are provided. */
8059 }
8061 /* First of all, extract the elf_flags, if available. */
8066 else
8072 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8074 {
8090 else
8093 }
8095 /* GCC creates a pseudo-section whose name describes the ABI. */
8099 /* If we have no useful BFD information, use the ABI from the last
8100 MIPS architecture (if there is one). */
8104 /* Try the architecture for any hint of the correct ABI. */
8108 {
8110 {
8120 /* On Irix, ELF64 executables use the N64 ABI. The
8121 pseudo-sections which describe the ABI aren't present
8122 on IRIX. (Even for executables created by gcc.) */
8126 else
8129 }
8130 }
8132 /* Default 64-bit objects to N64 instead of O32. */
8141 found_abi);
8143 /* What has the user specified from the command line? */
8147 wanted_abi);
8149 /* Now that we have found what the ABI for this binary would be,
8150 check whether the user is overriding it. */
8155 else
8159 mips_abi);
8161 /* Determine the default compressed ISA. */
8168 else
8172 /* Also used when doing an architecture lookup. */
8175 "mips_gdbarch_init: "
8177 mips64_transfers_32bit_regs_p);
8179 /* Determine the MIPS FPU type. */
8180 #ifdef HAVE_ELF
8184 Tag_GNU_MIPS_ABI_FP);
8190 {
8192 {
8201 /* Soft float or unknown. */
8204 }
8205 }
8209 {
8222 }
8225 else
8231 /* Check for blatant incompatibilities. */
8233 /* If we have only 32-bit registers, then we can't debug a 64-bit
8234 ABI. */
8239 {
8243 }
8245 /* Try to find a pre-existing architecture. */
8249 {
8250 /* MIPS needs to be pedantic about which ABI the object is
8251 using. */
8256 /* Need to be pedantic about which register virtual size is
8257 used. */
8261 /* Be pedantic about which FPU is selected. */
8268 }
8270 /* Need a new architecture. Fill in a target specific vector. */
8287 {
8288 /* Some useful properties can be inferred from the target. */
8290 {
8293 }
8295 {
8298 }
8299 }
8301 /* Initially set everything according to the default ABI/ISA. */
8312 mips_ax_pseudo_register_collect);
8313 set_gdbarch_ax_pseudo_register_push_stack
8317 mips_elf_make_msymbol_special);
8330 {
8397 }
8399 /* GCC creates a pseudo-section whose name specifies the size of
8400 longs, since -mlong32 or -mlong64 may be used independent of
8401 other options. How those options affect pointer sizes is ABI and
8402 architecture dependent, so use them to override the default sizes
8403 set by the ABI. This table shows the relationship between ABI,
8404 -mlongXX, and size of pointers:
8406 ABI -mlongXX ptr bits
8407 --- -------- --------
8408 o32 32 32
8409 o32 64 32
8410 n32 32 32
8411 n32 64 64
8412 o64 32 32
8413 o64 64 64
8414 n64 32 32
8415 n64 64 64
8416 eabi32 32 32
8417 eabi32 64 32
8418 eabi64 32 32
8419 eabi64 64 64
8421 Note that for o32 and eabi32, pointers are always 32 bits
8422 regardless of any -mlongXX option. For all others, pointers and
8423 longs are the same, as set by -mlongXX or set by defaults. */
8426 {
8431 {
8434 {
8446 }
8447 }
8448 }
8450 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8451 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8452 comment:
8454 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8455 flag in object files because to do so would make it impossible to
8456 link with libraries compiled without "-gp32". This is
8457 unnecessarily restrictive.
8459 We could solve this problem by adding "-gp32" multilibs to gcc,
8460 but to set this flag before gcc is built with such multilibs will
8461 break too many systems.''
8463 But even more unhelpfully, the default linker output target for
8464 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8465 for 64-bit programs - you need to change the ABI to change this,
8466 and not all gcc targets support that currently. Therefore using
8467 this flag to detect 32-bit mode would do the wrong thing given
8468 the current gcc - it would make GDB treat these 64-bit programs
8469 as 32-bit programs by default. */
8474 /* Add/remove bits from an address. The MIPS needs be careful to
8475 ensure that all 32 bit addresses are sign extended to 64 bits. */
8478 /* Unwind the frame. */
8483 /* Map debug register numbers onto internal register numbers. */
8486 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8488 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
8491 /* MIPS version of CALL_DUMMY. */
8504 mips_remote_breakpoint_from_pc);
8506 mips_adjust_breakpoint_address);
8524 else
8527 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8528 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8529 need to all be folded into the target vector. Since they are
8530 being used as guards for target_stopped_by_watchpoint, why not have
8531 target_stopped_by_watchpoint return the type of watchpoint that the code
8532 is sitting on? */
8537 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8538 to support MIPS16. This is a bad thing. Make sure not to do it
8539 if we have an OS ABI that actually supports shared libraries, since
8540 shared library support is more important. If we have an OS someday
8541 that supports both shared libraries and MIPS16, we'll have to find
8542 a better place for these.
8543 macro/2012-04-25: But that applies to return trampolines only and
8544 currently no MIPS OS ABI uses shared libraries that have them. */
8548 mips_single_step_through_delay);
8550 /* Virtual tables. */
8555 /* Hook in OS ABI-specific overrides, if they have been registered. */
8559 /* The hook may have adjusted num_regs, fetch the final value and
8560 set pc_regnum and sp_regnum now that it has been fixed. */
8565 /* Unwind the frame. */
8578 {
8582 /* Override the normal target description methods to handle our
8583 dual real and pseudo registers. */
8586 mips_tdesc_register_reggroup_p);
8592 }
8594 /* Add ABI-specific aliases for the registers. */
8599 else
8604 /* Add some other standard aliases. */
8611 value_of_mips_user_reg,
8615 }
8617 static void
8619 {
8622 /* Force the architecture to update, and (if it's a MIPS architecture)
8623 mips_gdbarch_init will take care of the rest. */
8626 }
8628 /* Print out which MIPS ABI is in use. */
8630 static void
8635 {
8637 fprintf_filtered
8639 "The MIPS ABI is unknown because the current architecture "
8641 else
8642 {
8648 fprintf_filtered
8651 actual_abi_str);
8653 fprintf_filtered
8656 actual_abi_str);
8657 else
8658 {
8659 /* Probably shouldn't happen... */
8664 }
8665 }
8666 }
8668 /* Print out which MIPS compressed ISA encoding is used. */
8670 static void
8673 {
8675 value);
8676 }
8678 static void
8680 {
8683 {
8686 /* Determine the ISA. */
8688 {
8704 }
8705 /* Determine the size of a pointer. */
8712 ef_mips_32bitmode);
8715 ef_mips_arch);
8720 "mips_dump_tdep: "
8724 }
8727 MIPS_DEFAULT_FPU_TYPE,
8741 }
8745 void
8747 {
8760 /* Create feature sets with the appropriate properties. The values
8761 are not important. */
8768 /* Add root prefix command for all "set mips"/"show mips" commands. */
8777 /* Allow the user to override the ABI. */
8790 mips_abi_update,
8791 show_mips_abi,
8794 /* Allow the user to set the ISA to assume for compressed code if ELF
8795 file flags don't tell or there is no program file selected. This
8796 setting is updated whenever unambiguous ELF file flags are interpreted,
8797 and carried over to subsequent sessions. */
8807 mips_abi_update,
8808 show_mips_compression,
8811 /* Let the user turn off floating point and set the fence post for
8812 heuristic_proc_start. */
8838 /* We really would like to have both "0" and "unlimited" work, but
8839 command.c doesn't deal with that. So make it a var_zinteger
8840 because the user can always use "999999" or some such for unlimited. */
8848 reinit_frame_cache_sfunc,
8850 the start of a function is %s. */
8853 /* Allow the user to control whether the upper bits of 64-bit
8854 addresses should be zeroed. */
8864 /* Allow the user to control the size of 32 bit registers within the
8865 raw remote packet. */
8875 set_mips64_transfers_32bit_regs,
8877 MIPS target that transfers 32-bit
8878 quantities is %s. */
8881 /* Debug this files internals. */
8887 NULL,
8889 currently %s. */
8891 }