include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright (C) 1994-2019 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version 3,
  10    or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING3.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #ifndef PPC_H
  23 #define PPC_H
  24
  25 #include "bfd_stdint.h"
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 typedef uint64_t ppc_cpu_t;
  32
  33 /* The opcode table is an array of struct powerpc_opcode.  */
  34
  35 struct powerpc_opcode
  36 {
  37   /* The opcode name.  */
  38   const char *name;
  39
  40   /* The opcode itself.  Those bits which will be filled in with
  41      operands are zeroes.  */
  42   uint64_t opcode;
  43
  44   /* The opcode mask.  This is used by the disassembler.  This is a
  45      mask containing ones indicating those bits which must match the
  46      opcode field, and zeroes indicating those bits which need not
  47      match (and are presumably filled in by operands).  */
  48   uint64_t mask;
  49
  50   /* One bit flags for the opcode.  These are used to indicate which
  51      specific processors support the instructions.  The defined values
  52      are listed below.  */
  53   ppc_cpu_t flags;
  54
  55   /* One bit flags for the opcode.  These are used to indicate which
  56      specific processors no longer support the instructions.  The defined
  57      values are listed below.  */
  58   ppc_cpu_t deprecated;
  59
  60   /* An array of operand codes.  Each code is an index into the
  61      operand table.  They appear in the order which the operands must
  62      appear in assembly code, and are terminated by a zero.  */
  63   unsigned char operands[8];
  64 };
  65
  66 /* The table itself is sorted by major opcode number, and is otherwise
  67    in the order in which the disassembler should consider
  68    instructions.  */
  69 extern const struct powerpc_opcode powerpc_opcodes[];
  70 extern const unsigned int powerpc_num_opcodes;
  71 extern const struct powerpc_opcode vle_opcodes[];
  72 extern const unsigned int vle_num_opcodes;
  73 extern const struct powerpc_opcode spe2_opcodes[];
  74 extern const unsigned int spe2_num_opcodes;
  75
  76 /* Values defined for the flags field of a struct powerpc_opcode.  */
  77
  78 /* Opcode is defined for the PowerPC architecture.  */
  79 #define PPC_OPCODE_PPC                 0x1ull
  80
  81 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  82 #define PPC_OPCODE_POWER               0x2ull
  83
  84 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  85 #define PPC_OPCODE_POWER2              0x4ull
  86
  87 /* Opcode is only defined on 64 bit architectures.  */
  88 #define PPC_OPCODE_64                  0x8ull
  89
  90 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  91    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  92    but it also supports many additional POWER instructions.  */
  93 #define PPC_OPCODE_601                0x10ull
  94
  95 /* Opcode is supported in both the Power and PowerPC architectures
  96    (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
  97    the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
  98    and PPC_OPCODE_POWER2 because many instructions changed mnemonics
  99    between POWER and POWERPC.  */
 100 #define PPC_OPCODE_COMMON             0x20ull
 101
 102 /* Opcode is supported for any Power or PowerPC platform (this is
 103    for the assembler's -many option, and it eliminates duplicates).  */
 104 #define PPC_OPCODE_ANY                0x40ull
 105
 106 /* Opcode is supported as part of the 64-bit bridge.  */
 107 #define PPC_OPCODE_64_BRIDGE          0x80ull
 108
 109 /* Opcode is supported by Altivec Vector Unit */
 110 #define PPC_OPCODE_ALTIVEC           0x100ull
 111
 112 /* Opcode is supported by PowerPC 403 processor.  */
 113 #define PPC_OPCODE_403               0x200ull
 114
 115 /* Opcode is supported by PowerPC BookE processor.  */
 116 #define PPC_OPCODE_BOOKE             0x400ull
 117
 118 /* Opcode is only supported by Power4 architecture.  */
 119 #define PPC_OPCODE_POWER4            0x800ull
 120
 121 /* Opcode is only supported by e500x2 Core.
 122    This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in
 123    their comment mark opcodes so that when those instructions are used
 124    an APUinfo entry can be generated.  */
 125 #define PPC_OPCODE_SPE              0x1000ull
 126
 127 /* Opcode is supported by Integer select APU.  */
 128 #define PPC_OPCODE_ISEL             0x2000ull
 129
 130 /* Opcode is an e500 SPE floating point instruction.  */
 131 #define PPC_OPCODE_EFS              0x4000ull
 132
 133 /* Opcode is supported by branch locking APU.  */
 134 #define PPC_OPCODE_BRLOCK           0x8000ull
 135
 136 /* Opcode is supported by performance monitor APU.  */
 137 #define PPC_OPCODE_PMR             0x10000ull
 138
 139 /* Opcode is supported by cache locking APU.  */
 140 #define PPC_OPCODE_CACHELCK        0x20000ull
 141
 142 /* Opcode is supported by machine check APU.  */
 143 #define PPC_OPCODE_RFMCI           0x40000ull
 144
 145 /* Opcode is supported by PowerPC 440 processor.  */
 146 #define PPC_OPCODE_440             0x80000ull
 147
 148 /* Opcode is only supported by Power5 architecture.  */
 149 #define PPC_OPCODE_POWER5         0x100000ull
 150
 151 /* Opcode is supported by PowerPC e300 family.  */
 152 #define PPC_OPCODE_E300           0x200000ull
 153
 154 /* Opcode is only supported by Power6 architecture.  */
 155 #define PPC_OPCODE_POWER6         0x400000ull
 156
 157 /* Opcode is only supported by PowerPC Cell family.  */
 158 #define PPC_OPCODE_CELL           0x800000ull
 159
 160 /* Opcode is supported by CPUs with paired singles support.  */
 161 #define PPC_OPCODE_PPCPS         0x1000000ull
 162
 163 /* Opcode is supported by Power E500MC */
 164 #define PPC_OPCODE_E500MC        0x2000000ull
 165
 166 /* Opcode is supported by PowerPC 405 processor.  */
 167 #define PPC_OPCODE_405           0x4000000ull
 168
 169 /* Opcode is supported by Vector-Scalar (VSX) Unit */
 170 #define PPC_OPCODE_VSX           0x8000000ull
 171
 172 /* Opcode is only supported by Power7 architecture.  */
 173 #define PPC_OPCODE_POWER7       0x10000000ull
 174
 175 /* Opcode is supported by A2.  */
 176 #define PPC_OPCODE_A2           0x20000000ull
 177
 178 /* Opcode is supported by PowerPC 476 processor.  */
 179 #define PPC_OPCODE_476          0x40000000ull
 180
 181 /* Opcode is supported by AppliedMicro Titan core */
 182 #define PPC_OPCODE_TITAN        0x80000000ull
 183
 184 /* Opcode which is supported by the e500 family */
 185 #define PPC_OPCODE_E500        0x100000000ull
 186
 187 /* Opcode is supported by Power E6500 */
 188 #define PPC_OPCODE_E6500       0x200000000ull
 189
 190 /* Opcode is supported by Thread management APU */
 191 #define PPC_OPCODE_TMR         0x400000000ull
 192
 193 /* Opcode which is supported by the VLE extension.  */
 194 #define PPC_OPCODE_VLE         0x800000000ull
 195
 196 /* Opcode is only supported by Power8 architecture.  */
 197 #define PPC_OPCODE_POWER8     0x1000000000ull
 198
 199 /* Opcode is supported by ppc750cl/Gekko/Broadway.  */
 200 #define PPC_OPCODE_750        0x2000000000ull
 201
 202 /* Opcode is supported by ppc7450.  */
 203 #define PPC_OPCODE_7450       0x4000000000ull
 204
 205 /* Opcode is supported by ppc821/850/860.  */
 206 #define PPC_OPCODE_860        0x8000000000ull
 207
 208 /* Opcode is only supported by Power9 architecture.  */
 209 #define PPC_OPCODE_POWER9    0x10000000000ull
 210
 211 /* Opcode is supported by e200z4.  */
 212 #define PPC_OPCODE_E200Z4    0x20000000000ull
 213
 214 /* Disassemble to instructions matching later in the opcode table
 215    with fewer "mask" bits set rather than the earlist match.  Fewer
 216    "mask" bits set imply a more general form of the opcode, in fact
 217    the underlying machine instruction.  */
 218 #define PPC_OPCODE_RAW       0x40000000000ull
 219
 220 /* Opcode is supported by PowerPC LSP */
 221 #define PPC_OPCODE_LSP       0x80000000000ull
 222
 223 /* Opcode is only supported by Freescale SPE2 APU.  */
 224 #define PPC_OPCODE_SPE2     0x100000000000ull
 225
 226 /* Opcode is supported by EFS2.  */
 227 #define PPC_OPCODE_EFS2     0x200000000000ull
 228
 229 /* A macro to extract the major opcode from an instruction.  */
 230 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 231
 232 /* A macro to determine if the instruction is a 2-byte VLE insn.  */
 233 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
 234
 235 /* A macro to extract the major opcode from a VLE instruction.  */
 236 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
 237
 238 /* A macro to convert a VLE opcode to a VLE opcode segment.  */
 239 #define VLE_OP_TO_SEG(i) ((i) >> 1)
 240
 241 /* A macro to extract the extended opcode from a SPE2 instruction.  */
 242 #define SPE2_XOP(i) ((i) & 0x7ff)
 243
 244 /* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment.  */
 245 #define SPE2_XOP_TO_SEG(i) ((i) >> 7)
 246 \f
 247 /* The operands table is an array of struct powerpc_operand.  */
 248
 249 struct powerpc_operand
 250 {
 251   /* A bitmask of bits in the operand.  */
 252   uint64_t bitm;
 253
 254   /* The shift operation to be applied to the operand.  No shift
 255      is made if this is zero.  For positive values, the operand
 256      is shifted left by SHIFT.  For negative values, the operand
 257      is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
 258      that BITM and SHIFT cannot be used to determine where the
 259      operand goes in the insn.  */
 260   int shift;
 261
 262   /* Insertion function.  This is used by the assembler.  To insert an
 263      operand value into an instruction, check this field.
 264
 265      If it is NULL, execute
 266          if (o->shift >= 0)
 267            i |= (op & o->bitm) << o->shift;
 268          else
 269            i |= (op & o->bitm) >> -o->shift;
 270      (i is the instruction which we are filling in, o is a pointer to
 271      this structure, and op is the operand value).
 272
 273      If this field is not NULL, then simply call it with the
 274      instruction and the operand value.  It will return the new value
 275      of the instruction.  If the operand value is illegal, *ERRMSG
 276      will be set to a warning string (the operand will be inserted in
 277      any case).  If the operand value is legal, *ERRMSG will be
 278      unchanged (most operands can accept any value).  */
 279   uint64_t (*insert)
 280     (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg);
 281
 282   /* Extraction function.  This is used by the disassembler.  To
 283      extract this operand type from an instruction, check this field.
 284
 285      If it is NULL, compute
 286          if (o->shift >= 0)
 287            op = (i >> o->shift) & o->bitm;
 288          else
 289            op = (i << -o->shift) & o->bitm;
 290          if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 291            sign_extend (op);
 292      (i is the instruction, o is a pointer to this structure, and op
 293      is the result).
 294
 295      If this field is not NULL, then simply call it with the
 296      instruction value.  It will return the value of the operand.
 297      *INVALID will be set to one by the extraction function if this
 298      operand type can not be extracted from this operand (i.e., the
 299      instruction does not match).  If the operand is valid, *INVALID
 300      will not be changed.  *INVALID will always be non-negative when
 301      used to extract a field from an instruction.
 302
 303      The extraction function is also called by both the assembler and
 304      disassembler if an operand is optional, in which case the
 305      function should return the default value of the operand.
 306      *INVALID is negative in this case, and is the negative count of
 307      omitted optional operands up to and including this operand.  */
 308   int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid);
 309
 310   /* One bit syntax flags.  */
 311   unsigned long flags;
 312 };
 313
 314 /* Elements in the table are retrieved by indexing with values from
 315    the operands field of the powerpc_opcodes table.  */
 316
 317 extern const struct powerpc_operand powerpc_operands[];
 318 extern const unsigned int num_powerpc_operands;
 319
 320 /* Use with the shift field of a struct powerpc_operand to indicate
 321      that BITM and SHIFT cannot be used to determine where the operand
 322      goes in the insn.  */
 323 #define PPC_OPSHIFT_INV (-1U << 31)
 324
 325 /* Values defined for the flags field of a struct powerpc_operand.
 326    Keep the register bits low:  They need to fit in an unsigned short.  */
 327
 328 /* This operand names a register.  The disassembler uses this to print
 329    register names with a leading 'r'.  */
 330 #define PPC_OPERAND_GPR (0x1)
 331
 332 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
 333 #define PPC_OPERAND_GPR_0 (0x2)
 334
 335 /* This operand names a floating point register.  The disassembler
 336    prints these with a leading 'f'.  */
 337 #define PPC_OPERAND_FPR (0x4)
 338
 339 /* This operand names a vector unit register.  The disassembler
 340    prints these with a leading 'v'.  */
 341 #define PPC_OPERAND_VR (0x8)
 342
 343 /* This operand names a vector-scalar unit register.  The disassembler
 344    prints these with a leading 'vs'.  */
 345 #define PPC_OPERAND_VSR (0x10)
 346
 347 /* This operand may use the symbolic names for the CR fields (even
 348    without -mregnames), which are
 349        lt  0    gt  1   eq  2   so  3   un  3
 350        cr0 0    cr1 1   cr2 2   cr3 3
 351        cr4 4    cr5 5   cr6 6   cr7 7
 352    These may be combined arithmetically, as in cr2*4+gt.  These are
 353    only supported on the PowerPC, not the POWER.  */
 354 #define PPC_OPERAND_CR_BIT (0x20)
 355
 356 /* This is a CR FIELD that does not use symbolic names (unless
 357    -mregnames is in effect).  If both PPC_OPERAND_CR_BIT and
 358    PPC_OPERAND_CR_REG are set then treat the field as per
 359    PPC_OPERAND_CR_BIT for assembly, but as if neither of these
 360    bits are set for disassembly.  */
 361 #define PPC_OPERAND_CR_REG (0x40)
 362
 363 /* This operand names a special purpose register.  */
 364 #define PPC_OPERAND_SPR (0x80)
 365
 366 /* This operand names a paired-single graphics quantization register.  */
 367 #define PPC_OPERAND_GQR (0x100)
 368
 369 /* This operand is a relative branch displacement.  The disassembler
 370    prints these symbolically if possible.  */
 371 #define PPC_OPERAND_RELATIVE (0x200)
 372
 373 /* This operand is an absolute branch address.  The disassembler
 374    prints these symbolically if possible.  */
 375 #define PPC_OPERAND_ABSOLUTE (0x400)
 376
 377 /* This operand takes signed values.  */
 378 #define PPC_OPERAND_SIGNED (0x800)
 379
 380 /* This operand takes signed values, but also accepts a full positive
 381    range of values when running in 32 bit mode.  That is, if bits is
 382    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 383    this flag is ignored.  */
 384 #define PPC_OPERAND_SIGNOPT (0x1000)
 385
 386 /* The next operand should be wrapped in parentheses rather than
 387    separated from this one by a comma.  This is used for the load and
 388    store instructions which want their operands to look like
 389        reg,displacement(reg)
 390    */
 391 #define PPC_OPERAND_PARENS (0x2000)
 392
 393 /* This operand is for the DS field in a DS form instruction.  */
 394 #define PPC_OPERAND_DS (0x4000)
 395
 396 /* This operand is for the DQ field in a DQ form instruction.  */
 397 #define PPC_OPERAND_DQ (0x8000)
 398
 399 /* This operand should be regarded as a negative number for the
 400    purposes of overflow checking (i.e., the normal most negative
 401    number is disallowed and one more than the normal most positive
 402    number is allowed).  This flag will only be set for a signed
 403    operand.  */
 404 #define PPC_OPERAND_NEGATIVE (0x10000)
 405
 406 /* Valid range of operand is 0..n rather than 0..n-1.  */
 407 #define PPC_OPERAND_PLUS1 (0x20000)
 408
 409 /* This operand is optional, and is zero if omitted.  This is used for
 410    example, in the optional BF field in the comparison instructions.  The
 411    assembler must count the number of operands remaining on the line,
 412    and the number of operands remaining for the opcode, and decide
 413    whether this operand is present or not.  The disassembler should
 414    print this operand out only if it is not zero.  */
 415 #define PPC_OPERAND_OPTIONAL (0x80000)
 416
 417 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 418    is omitted, then for the next operand use this operand value plus
 419    1, ignoring the next operand field for the opcode.  This wretched
 420    hack is needed because the Power rotate instructions can take
 421    either 4 or 5 operands.  The disassembler should print this operand
 422    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 423 #define PPC_OPERAND_NEXT (0x100000)
 424
 425 /* This flag is only used with PPC_OPERAND_OPTIONAL.  The operand is
 426    only optional when generating 32-bit code.  */
 427 #define PPC_OPERAND_OPTIONAL32 (0x400000)
 428
 429 /* Xilinx APU and FSL related operands */
 430 #define PPC_OPERAND_FSL (0x800000)
 431 #define PPC_OPERAND_FCR (0x1000000)
 432 #define PPC_OPERAND_UDI (0x2000000)
 433 \f
 434 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 435    with the operands table for simplicity.  The macro table is an
 436    array of struct powerpc_macro.  */
 437
 438 struct powerpc_macro
 439 {
 440   /* The macro name.  */
 441   const char *name;
 442
 443   /* The number of operands the macro takes.  */
 444   unsigned int operands;
 445
 446   /* One bit flags for the opcode.  These are used to indicate which
 447      specific processors support the instructions.  The values are the
 448      same as those for the struct powerpc_opcode flags field.  */
 449   ppc_cpu_t flags;
 450
 451   /* A format string to turn the macro into a normal instruction.
 452      Each %N in the string is replaced with operand number N (zero
 453      based).  */
 454   const char *format;
 455 };
 456
 457 extern const struct powerpc_macro powerpc_macros[];
 458 extern const int powerpc_num_macros;
 459
 460 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
 461
 462 static inline int64_t
 463 ppc_optional_operand_value (const struct powerpc_operand *operand,
 464                             uint64_t insn,
 465                             ppc_cpu_t dialect,
 466                             int num_optional)
 467 {
 468   if (operand->extract)
 469     return (*operand->extract) (insn, dialect, &num_optional);
 470   return 0;
 471 }
 472
 473 /* PowerPC VLE insns.  */
 474 #define E_OPCODE_MASK           0xfc00f800
 475
 476 /* Form I16L, uses 16A relocs.  */
 477 #define E_OR2I_INSN             0x7000C000
 478 #define E_AND2I_DOT_INSN        0x7000C800
 479 #define E_OR2IS_INSN            0x7000D000
 480 #define E_LIS_INSN              0x7000E000
 481 #define E_AND2IS_DOT_INSN       0x7000E800
 482
 483 /* Form I16A, uses 16D relocs.  */
 484 #define E_ADD2I_DOT_INSN        0x70008800
 485 #define E_ADD2IS_INSN           0x70009000
 486 #define E_CMP16I_INSN           0x70009800
 487 #define E_MULL2I_INSN           0x7000A000
 488 #define E_CMPL16I_INSN          0x7000A800
 489 #define E_CMPH16I_INSN          0x7000B000
 490 #define E_CMPHL16I_INSN         0x7000B800
 491
 492 #define E_LI_INSN               0x70000000
 493 #define E_LI_MASK               0xfc008000
 494
 495 #ifdef __cplusplus
 496 }
 497 #endif
 498
 499 #endif /* PPC_H */