sim/bfin/dv-bfin_ctimer.c

   1 /* Blackfin Core Timer model.
   2
   3    Copyright (C) 2010-2019 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "config.h"
  22
  23 #include "sim-main.h"
  24 #include "devices.h"
  25 #include "dv-bfin_cec.h"
  26 #include "dv-bfin_ctimer.h"
  27
  28 struct bfin_ctimer
  29 {
  30   bu32 base;
  31   struct hw_event *handler;
  32   signed64 timeout;
  33
  34   /* Order after here is important -- matches hardware MMR layout.  */
  35   bu32 tcntl, tperiod, tscale, tcount;
  36 };
  37 #define mmr_base()      offsetof(struct bfin_ctimer, tcntl)
  38 #define mmr_offset(mmr) (offsetof(struct bfin_ctimer, mmr) - mmr_base())
  39
  40 static const char * const mmr_names[] =
  41 {
  42   "TCNTL", "TPERIOD", "TSCALE", "TCOUNT",
  43 };
  44 #define mmr_name(off) mmr_names[(off) / 4]
  45
  46 static bool
  47 bfin_ctimer_enabled (struct bfin_ctimer *ctimer)
  48 {
  49   return (ctimer->tcntl & TMPWR) && (ctimer->tcntl & TMREN);
  50 }
  51
  52 static bu32
  53 bfin_ctimer_scale (struct bfin_ctimer *ctimer)
  54 {
  55   /* Only low 8 bits are actually checked.  */
  56   return (ctimer->tscale & 0xff) + 1;
  57 }
  58
  59 static void
  60 bfin_ctimer_schedule (struct hw *me, struct bfin_ctimer *ctimer);
  61
  62 static void
  63 bfin_ctimer_expire (struct hw *me, void *data)
  64 {
  65   struct bfin_ctimer *ctimer = data;
  66
  67   ctimer->tcntl |= TINT;
  68   if (ctimer->tcntl & TAUTORLD)
  69     {
  70       ctimer->tcount = ctimer->tperiod;
  71       bfin_ctimer_schedule (me, ctimer);
  72     }
  73   else
  74     {
  75       ctimer->tcount = 0;
  76       ctimer->handler = NULL;
  77     }
  78
  79   hw_port_event (me, IVG_IVTMR, 1);
  80 }
  81
  82 static void
  83 bfin_ctimer_update_count (struct hw *me, struct bfin_ctimer *ctimer)
  84 {
  85   bu32 scale, ticks;
  86   signed64 timeout;
  87
  88   /* If the timer was enabled w/out autoreload and has expired, then
  89      there's nothing to calculate here.  */
  90   if (ctimer->handler == NULL)
  91     return;
  92
  93   scale = bfin_ctimer_scale (ctimer);
  94   timeout = hw_event_remain_time (me, ctimer->handler);
  95   ticks = ctimer->timeout - timeout;
  96   ctimer->tcount -= (scale * ticks);
  97   ctimer->timeout = timeout;
  98 }
  99
 100 static void
 101 bfin_ctimer_deschedule (struct hw *me, struct bfin_ctimer *ctimer)
 102 {
 103   if (ctimer->handler)
 104     {
 105       hw_event_queue_deschedule (me, ctimer->handler);
 106       ctimer->handler = NULL;
 107     }
 108 }
 109
 110 static void
 111 bfin_ctimer_schedule (struct hw *me, struct bfin_ctimer *ctimer)
 112 {
 113   bu32 scale = bfin_ctimer_scale (ctimer);
 114   ctimer->timeout = (ctimer->tcount / scale) + !!(ctimer->tcount % scale);
 115   ctimer->handler = hw_event_queue_schedule (me, ctimer->timeout,
 116                                              bfin_ctimer_expire,
 117                                              ctimer);
 118 }
 119
 120 static unsigned
 121 bfin_ctimer_io_write_buffer (struct hw *me, const void *source,
 122                              int space, address_word addr, unsigned nr_bytes)
 123 {
 124   struct bfin_ctimer *ctimer = hw_data (me);
 125   bool curr_enabled;
 126   bu32 mmr_off;
 127   bu32 value;
 128   bu32 *valuep;
 129
 130   /* Invalid access mode is higher priority than missing register.  */
 131   if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
 132     return 0;
 133
 134   value = dv_load_4 (source);
 135   mmr_off = addr - ctimer->base;
 136   valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off);
 137
 138   HW_TRACE_WRITE ();
 139
 140   curr_enabled = bfin_ctimer_enabled (ctimer);
 141   switch (mmr_off)
 142     {
 143     case mmr_offset(tcntl):
 144       /* HRM describes TINT as sticky, but it isn't W1C.  */
 145       *valuep = value;
 146
 147       if (bfin_ctimer_enabled (ctimer) == curr_enabled)
 148         {
 149           /* Do nothing.  */
 150         }
 151       else if (curr_enabled)
 152         {
 153           bfin_ctimer_update_count (me, ctimer);
 154           bfin_ctimer_deschedule (me, ctimer);
 155         }
 156       else
 157         bfin_ctimer_schedule (me, ctimer);
 158
 159       break;
 160     case mmr_offset(tcount):
 161       /* HRM says writes are discarded when enabled.  */
 162       /* XXX: But hardware seems to be writeable all the time ?  */
 163       /* if (!curr_enabled) */
 164         *valuep = value;
 165       break;
 166     case mmr_offset(tperiod):
 167       /* HRM says writes are discarded when enabled.  */
 168       /* XXX: But hardware seems to be writeable all the time ?  */
 169       /* if (!curr_enabled) */
 170         {
 171           /* Writes are mirrored into TCOUNT.  */
 172           ctimer->tcount = value;
 173           *valuep = value;
 174         }
 175       break;
 176     case mmr_offset(tscale):
 177       if (curr_enabled)
 178         {
 179           bfin_ctimer_update_count (me, ctimer);
 180           bfin_ctimer_deschedule (me, ctimer);
 181         }
 182       *valuep = value;
 183       if (curr_enabled)
 184         bfin_ctimer_schedule (me, ctimer);
 185       break;
 186     }
 187
 188   return nr_bytes;
 189 }
 190
 191 static unsigned
 192 bfin_ctimer_io_read_buffer (struct hw *me, void *dest,
 193                             int space, address_word addr, unsigned nr_bytes)
 194 {
 195   struct bfin_ctimer *ctimer = hw_data (me);
 196   bu32 mmr_off;
 197   bu32 *valuep;
 198
 199   /* Invalid access mode is higher priority than missing register.  */
 200   if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
 201     return 0;
 202
 203   mmr_off = addr - ctimer->base;
 204   valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off);
 205
 206   HW_TRACE_READ ();
 207
 208   switch (mmr_off)
 209     {
 210     case mmr_offset(tcount):
 211       /* Since we're optimizing events here, we need to calculate
 212          the new tcount value.  */
 213       if (bfin_ctimer_enabled (ctimer))
 214         bfin_ctimer_update_count (me, ctimer);
 215       break;
 216     }
 217
 218   dv_store_4 (dest, *valuep);
 219
 220   return nr_bytes;
 221 }
 222
 223 static const struct hw_port_descriptor bfin_ctimer_ports[] =
 224 {
 225   { "ivtmr", IVG_IVTMR, 0, output_port, },
 226   { NULL, 0, 0, 0, },
 227 };
 228
 229 static void
 230 attach_bfin_ctimer_regs (struct hw *me, struct bfin_ctimer *ctimer)
 231 {
 232   address_word attach_address;
 233   int attach_space;
 234   unsigned attach_size;
 235   reg_property_spec reg;
 236
 237   if (hw_find_property (me, "reg") == NULL)
 238     hw_abort (me, "Missing \"reg\" property");
 239
 240   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 241     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 242
 243   hw_unit_address_to_attach_address (hw_parent (me),
 244                                      &reg.address,
 245                                      &attach_space, &attach_address, me);
 246   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 247
 248   if (attach_size != BFIN_COREMMR_CTIMER_SIZE)
 249     hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_CTIMER_SIZE);
 250
 251   hw_attach_address (hw_parent (me),
 252                      0, attach_space, attach_address, attach_size, me);
 253
 254   ctimer->base = attach_address;
 255 }
 256
 257 static void
 258 bfin_ctimer_finish (struct hw *me)
 259 {
 260   struct bfin_ctimer *ctimer;
 261
 262   ctimer = HW_ZALLOC (me, struct bfin_ctimer);
 263
 264   set_hw_data (me, ctimer);
 265   set_hw_io_read_buffer (me, bfin_ctimer_io_read_buffer);
 266   set_hw_io_write_buffer (me, bfin_ctimer_io_write_buffer);
 267   set_hw_ports (me, bfin_ctimer_ports);
 268
 269   attach_bfin_ctimer_regs (me, ctimer);
 270
 271   /* Initialize the Core Timer.  */
 272 }
 273
 274 const struct hw_descriptor dv_bfin_ctimer_descriptor[] =
 275 {
 276   {"bfin_ctimer", bfin_ctimer_finish,},
 277   {NULL, NULL},
 278 };