[PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav...
[binutils-gdb.git] / sim / bfin / dv-bfin_otp.c
blob6e13179b36e801386696ce366917a506dd9126eb
1 /* Blackfin One-Time Programmable Memory (OTP) model
3 Copyright (C) 2010-2019 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "config.h"
23 #include "sim-main.h"
24 #include "devices.h"
25 #include "dv-bfin_otp.h"
27 /* XXX: No public documentation on this interface. This seems to work
28 with the on-chip ROM functions though and was figured out by
29 disassembling & walking that code. */
30 /* XXX: About only thing that should be done here are CRC fields. And
31 supposedly there is an interrupt that could be generated. */
33 struct bfin_otp
35 bu32 base;
37 /* The actual OTP storage -- 0x200 pages, each page is 128bits.
38 While certain pages have predefined and/or secure access, we don't
39 bother trying to implement that coverage. All pages are open for
40 reading & writing. */
41 bu32 mem[0x200 * 4];
43 /* Order after here is important -- matches hardware MMR layout. */
44 bu16 BFIN_MMR_16(control);
45 bu16 BFIN_MMR_16(ben);
46 bu16 BFIN_MMR_16(status);
47 bu32 timing;
48 bu32 _pad0[28];
49 bu32 data0, data1, data2, data3;
51 #define mmr_base() offsetof(struct bfin_otp, control)
52 #define mmr_offset(mmr) (offsetof(struct bfin_otp, mmr) - mmr_base())
53 #define mmr_idx(mmr) (mmr_offset (mmr) / 4)
55 static const char * const mmr_names[] =
57 "OTP_CONTROL", "OTP_BEN", "OTP_STATUS", "OTP_TIMING",
58 [mmr_idx (data0)] = "OTP_DATA0", "OTP_DATA1", "OTP_DATA2", "OTP_DATA3",
60 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
62 /* XXX: This probably misbehaves with big endian hosts. */
63 static void
64 bfin_otp_transfer (struct bfin_otp *otp, void *vdst, void *vsrc)
66 bu8 *dst = vdst, *src = vsrc;
67 int bidx;
68 for (bidx = 0; bidx < 16; ++bidx)
69 if (otp->ben & (1 << bidx))
70 dst[bidx] = src[bidx];
73 static void
74 bfin_otp_read_page (struct bfin_otp *otp, bu16 page)
76 bfin_otp_transfer (otp, &otp->data0, &otp->mem[page * 4]);
79 static void
80 bfin_otp_write_page_val (struct bfin_otp *otp, bu16 page, bu64 val[2])
82 bfin_otp_transfer (otp, &otp->mem[page * 4], val);
84 static void
85 bfin_otp_write_page_val2 (struct bfin_otp *otp, bu16 page, bu64 lo, bu64 hi)
87 bu64 val[2] = { lo, hi };
88 bfin_otp_write_page_val (otp, page, val);
90 static void
91 bfin_otp_write_page (struct bfin_otp *otp, bu16 page)
93 bfin_otp_write_page_val (otp, page, (void *)&otp->data0);
96 static unsigned
97 bfin_otp_io_write_buffer (struct hw *me, const void *source, int space,
98 address_word addr, unsigned nr_bytes)
100 struct bfin_otp *otp = hw_data (me);
101 bu32 mmr_off;
102 bu32 value;
103 bu16 *value16p;
104 bu32 *value32p;
105 void *valuep;
107 /* Invalid access mode is higher priority than missing register. */
108 if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
109 return 0;
111 if (nr_bytes == 4)
112 value = dv_load_4 (source);
113 else
114 value = dv_load_2 (source);
116 mmr_off = addr - otp->base;
117 valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
118 value16p = valuep;
119 value32p = valuep;
121 HW_TRACE_WRITE ();
123 switch (mmr_off)
125 case mmr_offset(control):
127 int page;
129 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
130 return 0;
131 /* XXX: Seems like these bits aren't writable. */
132 *value16p = value & 0x39FF;
134 /* Low bits seem to be the page address. */
135 page = value & PAGE_ADDR;
137 /* Write operation. */
138 if (value & DO_WRITE)
139 bfin_otp_write_page (otp, page);
141 /* Read operation. */
142 if (value & DO_READ)
143 bfin_otp_read_page (otp, page);
145 otp->status |= STATUS_DONE;
147 break;
149 case mmr_offset(ben):
150 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
151 return 0;
152 /* XXX: All bits seem to be writable. */
153 *value16p = value;
154 break;
155 case mmr_offset(status):
156 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
157 return 0;
158 /* XXX: All bits seem to be W1C. */
159 dv_w1c_2 (value16p, value, -1);
160 break;
161 case mmr_offset(timing):
162 case mmr_offset(data0):
163 case mmr_offset(data1):
164 case mmr_offset(data2):
165 case mmr_offset(data3):
166 if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
167 return 0;
168 *value32p = value;
169 break;
170 default:
171 dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
172 return 0;
175 return nr_bytes;
178 static unsigned
179 bfin_otp_io_read_buffer (struct hw *me, void *dest, int space,
180 address_word addr, unsigned nr_bytes)
182 struct bfin_otp *otp = hw_data (me);
183 bu32 mmr_off;
184 bu16 *value16p;
185 bu32 *value32p;
186 void *valuep;
188 /* Invalid access mode is higher priority than missing register. */
189 if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
190 return 0;
192 mmr_off = addr - otp->base;
193 valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
194 value16p = valuep;
195 value32p = valuep;
197 HW_TRACE_READ ();
199 switch (mmr_off)
201 case mmr_offset(control):
202 case mmr_offset(ben):
203 case mmr_offset(status):
204 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
205 return 0;
206 dv_store_2 (dest, *value16p);
207 break;
208 case mmr_offset(timing):
209 case mmr_offset(data0):
210 case mmr_offset(data1):
211 case mmr_offset(data2):
212 case mmr_offset(data3):
213 if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
214 return 0;
215 dv_store_4 (dest, *value32p);
216 break;
217 default:
218 dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
219 return 0;
222 return nr_bytes;
225 static void
226 attach_bfin_otp_regs (struct hw *me, struct bfin_otp *otp)
228 address_word attach_address;
229 int attach_space;
230 unsigned attach_size;
231 reg_property_spec reg;
233 if (hw_find_property (me, "reg") == NULL)
234 hw_abort (me, "Missing \"reg\" property");
236 if (!hw_find_reg_array_property (me, "reg", 0, &reg))
237 hw_abort (me, "\"reg\" property must contain three addr/size entries");
239 hw_unit_address_to_attach_address (hw_parent (me),
240 &reg.address,
241 &attach_space, &attach_address, me);
242 hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
244 if (attach_size != BFIN_MMR_OTP_SIZE)
245 hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_OTP_SIZE);
247 hw_attach_address (hw_parent (me),
248 0, attach_space, attach_address, attach_size, me);
250 otp->base = attach_address;
253 static const struct hw_port_descriptor bfin_otp_ports[] =
255 { "stat", 0, 0, output_port, },
256 { NULL, 0, 0, 0, },
259 static void
260 bfin_otp_finish (struct hw *me)
262 char part_str[16];
263 struct bfin_otp *otp;
264 unsigned int fps03;
265 int type = hw_find_integer_property (me, "type");
267 otp = HW_ZALLOC (me, struct bfin_otp);
269 set_hw_data (me, otp);
270 set_hw_io_read_buffer (me, bfin_otp_io_read_buffer);
271 set_hw_io_write_buffer (me, bfin_otp_io_write_buffer);
272 set_hw_ports (me, bfin_otp_ports);
274 attach_bfin_otp_regs (me, otp);
276 /* Initialize the OTP. */
277 otp->ben = 0xFFFF;
278 otp->timing = 0x00001485;
280 /* Semi-random value for unique chip id. */
281 bfin_otp_write_page_val2 (otp, FPS00, (unsigned long)otp, ~(unsigned long)otp);
283 memset (part_str, 0, sizeof (part_str));
284 sprintf (part_str, "ADSP-BF%iX", type);
285 switch (type)
287 case 512:
288 fps03 = FPS03_BF512;
289 break;
290 case 514:
291 fps03 = FPS03_BF514;
292 break;
293 case 516:
294 fps03 = FPS03_BF516;
295 break;
296 case 518:
297 fps03 = FPS03_BF518;
298 break;
299 case 522:
300 fps03 = FPS03_BF522;
301 break;
302 case 523:
303 fps03 = FPS03_BF523;
304 break;
305 case 524:
306 fps03 = FPS03_BF524;
307 break;
308 case 525:
309 fps03 = FPS03_BF525;
310 break;
311 case 526:
312 fps03 = FPS03_BF526;
313 break;
314 case 527:
315 fps03 = FPS03_BF527;
316 break;
317 default:
318 fps03 = 0;
319 break;
321 part_str[14] = (fps03 >> 0);
322 part_str[15] = (fps03 >> 8);
323 bfin_otp_write_page_val (otp, FPS03, (void *)part_str);
326 const struct hw_descriptor dv_bfin_otp_descriptor[] =
328 {"bfin_otp", bfin_otp_finish,},
329 {NULL, NULL},