sim/common/cgen-defs.h

   1 /* General Cpu tools GENerated simulator support.
   2    Copyright (C) 1996-2019 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef CGEN_DEFS_H
  21 #define CGEN_DEFS_H
  22
  23 /* Compute number of longs required to hold N bits.  */
  24 #define HOST_LONGS_FOR_BITS(n) \
  25   (((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8)
  26 \f
  27 /* Forward decls.  Defined in the machine generated files.  */
  28
  29 /* This holds the contents of the extracted insn.
  30    There are a few common entries (e.g. pc address), and then one big
  31    union with an entry for each of the instruction formats.  */
  32 typedef struct argbuf ARGBUF;
  33
  34 /* ARGBUF accessors.  */
  35 #define ARGBUF_ADDR(abuf) ((abuf)->addr)
  36 #define ARGBUF_IDESC(abuf) ((abuf)->idesc)
  37 #define ARGBUF_TRACE_P(abuf) ((abuf)->trace_p)
  38 #define ARGBUF_PROFILE_P(abuf) ((abuf)->profile_p)
  39
  40 /* This is one ARGBUF plus whatever else is needed for WITH_SCACHE support.
  41    At present there is nothing else, but it also provides a level of
  42    abstraction.  */
  43 typedef struct scache SCACHE;
  44
  45 /* This is a union with one entry for each instruction format.
  46    Each entry contains all of the non-constant inputs of the instruction
  47    in the case of read-before-exec support, or all outputs of the instruction
  48    in the case of write-after-exec support.  */
  49 typedef struct parexec PAREXEC;
  50
  51 /* An "Instruction DESCriptor".
  52    This is the main handle on an instruction for the simulator.  */
  53 typedef struct idesc IDESC;
  54 \f
  55 /* Engine support.
  56    ??? This is here because it's needed before eng.h (built by genmloop.sh)
  57    which is needed before cgen-engine.h and cpu.h.
  58    ??? This depends on a cpu family specific type, IADDR, but no machine
  59    generated headers will have been included yet.  sim/common currently
  60    requires the typedef of sim_cia in sim-main.h between the inclusion of
  61    sim-basics.h and sim-base.h so this is no different.  */
  62
  63 /* SEM_ARG is intended to hide whether or not the scache is in use from the
  64    semantic routines.  In reality for the with-extraction case it is always
  65    an SCACHE * even when not using the SCACHE since there's no current win to
  66    making it something else ("not using the SCACHE" is like having a cache
  67    size of 1).
  68    The without-extraction case still uses an ARGBUF:
  69    - consistency with scache version
  70    - still need to record which operands are written
  71      This wouldn't be needed if modeling was done in the semantic routines
  72      but this isn't as general as handling it outside of the semantic routines.
  73      For example Shade allows calling user-supplied code before/after each
  74      instruction and this is something that is being planned.
  75    ??? There is still some clumsiness in how much of ARGBUF to use.  */
  76 typedef SCACHE *SEM_ARG;
  77
  78 /* instruction address
  79    ??? This was intended to be a struct of two elements in the WITH_SCACHE_PBB
  80    case.  The first element is the IADDR, the second element is the SCACHE *.
  81    Haven't found the time yet to make this work, but it seemed a nicer approach
  82    than the current br_cache stuff.  */
  83 typedef IADDR PCADDR;
  84
  85 /* Current instruction address, used by common. */
  86 typedef IADDR CIA;
  87
  88 /* Semantic routines' version of the PC.  */
  89 #if WITH_SCACHE_PBB
  90 typedef SCACHE *SEM_PC;
  91 #else
  92 typedef IADDR SEM_PC;
  93 #endif
  94
  95 /* Kinds of branches.  */
  96 typedef enum {
  97   SEM_BRANCH_UNTAKEN,
  98   /* Branch to an uncacheable address (e.g. j reg).  */
  99   SEM_BRANCH_UNCACHEABLE,
 100   /* Branch to a cacheable (fixed) address.  */
 101   SEM_BRANCH_CACHEABLE
 102 } SEM_BRANCH_TYPE;
 103 \f
 104 /* Virtual insn support.  */
 105
 106 /* Opcode table for virtual insns (only used by the simulator).  */
 107 extern const CGEN_INSN cgen_virtual_insn_table[];
 108
 109 /* -ve of indices of virtual insns in cgen_virtual_insn_table.  */
 110 typedef enum {
 111   VIRTUAL_INSN_X_INVALID = 0,
 112   VIRTUAL_INSN_X_BEFORE = -1, VIRTUAL_INSN_X_AFTER = -2,
 113   VIRTUAL_INSN_X_BEGIN = -3,
 114   VIRTUAL_INSN_X_CHAIN= -4, VIRTUAL_INSN_X_CTI_CHAIN = -5
 115 } CGEN_INSN_VIRTUAL_TYPE;
 116
 117 /* Return non-zero if CGEN_INSN* INSN is a virtual insn.  */
 118 #define CGEN_INSN_VIRTUAL_P(insn) \
 119   CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_VIRTUAL)
 120 \f
 121 /* GNU C's "computed goto" facility is used to speed things up where
 122    possible.  These macros provide a portable way to use them.
 123    Nesting of these switch statements is done by providing an extra argument
 124    that distinguishes them.  `N' can be a number or symbol.
 125    Variable `labels_##N' must be initialized with the labels of each case.  */
 126
 127 #ifdef __GNUC__
 128 #define SWITCH(N, X) goto *X;
 129 #define CASE(N, X) case_##N##_##X
 130 #define BREAK(N) goto end_switch_##N
 131 #define DEFAULT(N) default_##N
 132 #define ENDSWITCH(N) end_switch_##N:;
 133 #else
 134 #define SWITCH(N, X) switch (X)
 135 #define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */
 136 #define BREAK(N) break
 137 #define DEFAULT(N) default
 138 #define ENDSWITCH(N)
 139 #endif
 140 \f
 141 /* Simulator state.  */
 142
 143 /* CGEN_STATE contains additional state information not present in
 144    sim_state_base.  */
 145
 146 typedef struct cgen_state {
 147   /* Non-zero if no tracing or profiling is selected.  */
 148   int run_fast_p;
 149 #define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p)
 150 } CGEN_STATE;
 151 \f
 152 /* Various utilities.  */
 153
 154 /* Called after sim_post_argv_init to do any cgen initialization.  */
 155 extern void cgen_init (SIM_DESC);
 156
 157 /* Return the name of an insn.  */
 158 extern CPU_INSN_NAME_FN cgen_insn_name;
 159
 160 /* Return the maximum number of extra bytes required for a sim_cpu struct.  */
 161 /* ??? Ok, yes, this is less pretty than it should be.  Give me a better
 162    language [or suggest a better way].  */
 163 extern int cgen_cpu_max_extra_bytes (void);
 164
 165 /* Target supplied routine to process an invalid instruction.  */
 166 extern SEM_PC sim_engine_invalid_insn (SIM_CPU *, IADDR, SEM_PC);
 167
 168 #endif /* CGEN_DEFS_H */