2 Copyright (C) 1999-2019 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #define WANT_CPU frvbf
21 #define WANT_CPU_FRVBF
24 #include "targ-vals.h"
25 #include "cgen-engine.h"
30 #include "libiberty.h"
32 CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot
;
34 /* The semantic code invokes this for invalid (unrecognized) instructions. */
37 sim_engine_invalid_insn (SIM_CPU
*current_cpu
, IADDR cia
, SEM_PC vpc
)
39 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
43 /* Process an address exception. */
46 frv_core_signal (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
,
47 unsigned int map
, int nr_bytes
, address_word addr
,
48 transfer_type transfer
, sim_core_signals sig
)
50 if (sig
== sim_core_unaligned_signal
)
52 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
53 || STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr450
)
54 frv_queue_data_access_error_interrupt (current_cpu
, addr
);
56 frv_queue_mem_address_not_aligned_interrupt (current_cpu
, addr
);
60 sim_core_signal (sd
, current_cpu
, cia
, map
, nr_bytes
, addr
, transfer
, sig
);
64 frv_sim_engine_halt_hook (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
)
67 if (current_cpu
!= NULL
)
68 CPU_PC_SET (current_cpu
, cia
);
70 /* Invalidate the insn and data caches of all cpus. */
71 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
73 current_cpu
= STATE_CPU (sd
, i
);
74 frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu
), 0);
75 frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu
), 1);
80 /* Read/write functions for system call interface. */
83 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
84 unsigned long taddr
, char *buf
, int bytes
)
86 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
87 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
89 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
90 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
94 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
95 unsigned long taddr
, const char *buf
, int bytes
)
97 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
98 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
100 frv_cache_invalidate_all (CPU_INSN_CACHE (cpu
), 0);
101 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
102 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
105 /* Handle TRA and TIRA insns. */
107 frv_itrap (SIM_CPU
*current_cpu
, PCADDR pc
, USI base
, SI offset
)
109 SIM_DESC sd
= CPU_STATE (current_cpu
);
110 host_callback
*cb
= STATE_CALLBACK (sd
);
111 USI num
= ((base
+ offset
) & 0x7f) + 0x80;
113 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
115 frv_queue_software_interrupt (current_cpu
, num
);
124 CB_SYSCALL_INIT (&s
);
125 s
.func
= GET_H_GR (7);
126 s
.arg1
= GET_H_GR (8);
127 s
.arg2
= GET_H_GR (9);
128 s
.arg3
= GET_H_GR (10);
130 if (s
.func
== TARGET_SYS_exit
)
132 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_exited
, s
.arg1
);
136 s
.p2
= (PTR
) current_cpu
;
137 s
.read_mem
= syscall_read_mem
;
138 s
.write_mem
= syscall_write_mem
;
140 SET_H_GR (8, s
.result
);
141 SET_H_GR (9, s
.result2
);
142 SET_H_GR (10, s
.errcode
);
146 case TRAP_BREAKPOINT
:
147 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
150 /* Add support for dumping registers, either at fixed traps, or all
151 unknown traps if configured with --enable-sim-trapdump. */
154 frv_queue_software_interrupt (current_cpu
, num
);
166 #if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2))
172 if (STATE_TEXT_SECTION (sd
)
173 && pc
>= STATE_TEXT_START (sd
)
174 && pc
< STATE_TEXT_END (sd
))
176 const char *pc_filename
= (const char *)0;
177 const char *pc_function
= (const char *)0;
178 unsigned int pc_linenum
= 0;
180 if (bfd_find_nearest_line (STATE_PROG_BFD (sd
),
181 STATE_TEXT_SECTION (sd
),
182 (struct bfd_symbol
**) 0,
183 pc
- STATE_TEXT_START (sd
),
184 &pc_filename
, &pc_function
, &pc_linenum
)
185 && (pc_function
|| pc_filename
))
192 strcpy (p
, pc_function
);
197 char *q
= (char *) strrchr (pc_filename
, '/');
198 strcpy (p
, (q
) ? q
+1 : pc_filename
);
204 sprintf (p
, " line %d", pc_linenum
);
210 if ((p
+1) - buf
> sizeof (buf
))
216 "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n",
217 (unsigned)pc
, buf
, (unsigned)base
, (int)offset
);
219 for (i
= 0; i
< 64; i
+= 8)
221 long g0
= (long)GET_H_GR (i
);
222 long g1
= (long)GET_H_GR (i
+1);
223 long g2
= (long)GET_H_GR (i
+2);
224 long g3
= (long)GET_H_GR (i
+3);
225 long g4
= (long)GET_H_GR (i
+4);
226 long g5
= (long)GET_H_GR (i
+5);
227 long g6
= (long)GET_H_GR (i
+6);
228 long g7
= (long)GET_H_GR (i
+7);
230 if ((g0
| g1
| g2
| g3
| g4
| g5
| g6
| g7
) != 0)
232 "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
233 i
, i
+7, g0
, g1
, g2
, g3
, g4
, g5
, g6
, g7
);
236 for (i
= 0; i
< 64; i
+= 8)
238 long f0
= (long)GET_H_FR (i
);
239 long f1
= (long)GET_H_FR (i
+1);
240 long f2
= (long)GET_H_FR (i
+2);
241 long f3
= (long)GET_H_FR (i
+3);
242 long f4
= (long)GET_H_FR (i
+4);
243 long f5
= (long)GET_H_FR (i
+5);
244 long f6
= (long)GET_H_FR (i
+6);
245 long f7
= (long)GET_H_FR (i
+7);
247 if ((f0
| f1
| f2
| f3
| f4
| f5
| f6
| f7
) != 0)
249 "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
250 i
, i
+7, f0
, f1
, f2
, f3
, f4
, f5
, f6
, f7
);
254 "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
255 (long)GET_H_SPR (272),
256 (long)GET_H_SPR (273),
257 (long)GET_H_SPR (256),
258 (long)GET_H_SPR (263));
265 /* Handle the MTRAP insn. */
267 frv_mtrap (SIM_CPU
*current_cpu
)
269 SIM_DESC sd
= CPU_STATE (current_cpu
);
271 /* Check the status of media exceptions in MSR0. */
272 SI msr
= GET_MSR (0);
273 if (GET_MSR_AOVF (msr
) || GET_MSR_MTT (msr
) && STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
274 frv_queue_program_interrupt (current_cpu
, FRV_MP_EXCEPTION
);
277 /* Handle the BREAK insn. */
279 frv_break (SIM_CPU
*current_cpu
)
282 SIM_DESC sd
= CPU_STATE (current_cpu
);
284 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
286 /* Invalidate the insn cache because the debugger will presumably
287 replace the breakpoint insn with the real one. */
288 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
291 frv_queue_break_interrupt (current_cpu
);
294 /* Return from trap. */
296 frv_rett (SIM_CPU
*current_cpu
, PCADDR pc
, BI debug_field
)
299 /* if (normal running mode and debug_field==0
303 else if (debug running mode and debug_field==1)
307 change to normal running mode
309 int psr_s
= GET_H_PSR_S ();
310 int psr_et
= GET_H_PSR_ET ();
312 /* Check for exceptions in the priority order listed in the FRV Architecture
316 /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */
319 SIM_DESC sd
= CPU_STATE (current_cpu
);
320 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
323 /* privileged_instruction interrupt will have already been queued by
324 frv_detect_insn_access_interrupts. */
329 /* Halt if PSR.S is set. See chapter 6 of the LSI. */
332 SIM_DESC sd
= CPU_STATE (current_cpu
);
333 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
336 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
339 else if (! CPU_DEBUG_STATE (current_cpu
) && debug_field
== 0)
341 USI psr
= GET_PSR ();
342 /* Return from normal running state. */
343 new_pc
= GET_H_SPR (H_SPR_PCSR
);
345 SET_PSR_S (psr
, GET_PSR_PS (psr
));
346 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
348 else if (CPU_DEBUG_STATE (current_cpu
) && debug_field
== 1)
350 USI psr
= GET_PSR ();
351 /* Return from debug state. */
352 new_pc
= GET_H_SPR (H_SPR_BPCSR
);
353 SET_PSR_ET (psr
, GET_H_BPSR_BET ());
354 SET_PSR_S (psr
, GET_H_BPSR_BS ());
355 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
356 CPU_DEBUG_STATE (current_cpu
) = 0;
364 /* Functions for handling non-excepting instruction side effects. */
365 static SI
next_available_nesr (SIM_CPU
*current_cpu
, SI current_index
)
367 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
368 if (control
->spr
[H_SPR_NECR
].implemented
)
371 USI necr
= GET_NECR ();
373 /* See if any NESRs are implemented. First need to check the validity of
375 if (! GET_NECR_VALID (necr
))
378 limit
= GET_NECR_NEN (necr
);
379 for (++current_index
; current_index
< limit
; ++current_index
)
381 SI nesr
= GET_NESR (current_index
);
382 if (! GET_NESR_VALID (nesr
))
383 return current_index
;
389 static SI
next_valid_nesr (SIM_CPU
*current_cpu
, SI current_index
)
391 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
392 if (control
->spr
[H_SPR_NECR
].implemented
)
395 USI necr
= GET_NECR ();
397 /* See if any NESRs are implemented. First need to check the validity of
399 if (! GET_NECR_VALID (necr
))
402 limit
= GET_NECR_NEN (necr
);
403 for (++current_index
; current_index
< limit
; ++current_index
)
405 SI nesr
= GET_NESR (current_index
);
406 if (GET_NESR_VALID (nesr
))
407 return current_index
;
414 frvbf_check_non_excepting_load (
415 SIM_CPU
*current_cpu
, SI base_index
, SI disp_index
, SI target_index
,
416 SI immediate_disp
, QI data_size
, BI is_float
419 BI rc
= 1; /* perform the load. */
420 SIM_DESC sd
= CPU_STATE (current_cpu
);
430 FRV_REGISTER_CONTROL
*control
;
432 SI address
= GET_H_GR (base_index
);
434 address
+= GET_H_GR (disp_index
);
436 address
+= immediate_disp
;
438 /* Check for interrupt factors. */
456 if (target_index
& 1)
462 if (target_index
& 3)
467 IADDR pc
= GET_H_PC ();
468 sim_engine_abort (sd
, current_cpu
, pc
,
469 "check_non_excepting_load: Incorrect data_size\n");
474 control
= CPU_REGISTER_CONTROL (current_cpu
);
475 if (control
->spr
[H_SPR_NECR
].implemented
)
478 do_elos
= GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
);
483 /* NECR, NESR, NEEAR are only implemented for the full frv machine. */
486 ne_index
= next_available_nesr (current_cpu
, NO_NESR
);
487 if (ne_index
== NO_NESR
)
489 IADDR pc
= GET_H_PC ();
490 sim_engine_abort (sd
, current_cpu
, pc
,
491 "No available NESR register\n");
494 /* Fill in the basic fields of the NESR. */
495 nesr
= GET_NESR (ne_index
);
496 SET_NESR_VALID (nesr
);
498 SET_NESR_DRN (nesr
, target_index
);
499 SET_NESR_SIZE (nesr
, data_size
);
500 SET_NESR_NEAN (nesr
, ne_index
);
504 CLEAR_NESR_FR (nesr
);
506 /* Set the corresponding NEEAR. */
507 SET_NEEAR (ne_index
, address
);
509 SET_NESR_DAEC (nesr
, 0);
510 SET_NESR_REC (nesr
, 0);
511 SET_NESR_EC (nesr
, 0);
514 /* Set the NE flag corresponding to the target register if an interrupt
516 daec is not checked here yet, but is declared for future reference. */
518 NE_base
= H_SPR_FNER0
;
520 NE_base
= H_SPR_GNER0
;
522 GET_NE_FLAGS (NE_flags
, NE_base
);
525 SET_NE_FLAG (NE_flags
, target_index
);
527 SET_NESR_REC (nesr
, NESR_REGISTER_NOT_ALIGNED
);
532 SET_NE_FLAG (NE_flags
, target_index
);
534 SET_NESR_EC (nesr
, NESR_MEM_ADDRESS_NOT_ALIGNED
);
538 SET_NESR (ne_index
, nesr
);
540 /* If no interrupt factor was detected then set the NE flag on the
541 target register if the NE flag on one of the input registers
543 if (! rec
&& ! ec
&& ! daec
)
545 BI ne_flag
= GET_NE_FLAG (NE_flags
, base_index
);
547 ne_flag
|= GET_NE_FLAG (NE_flags
, disp_index
);
550 SET_NE_FLAG (NE_flags
, target_index
);
551 rc
= 0; /* Do not perform the load. */
554 CLEAR_NE_FLAG (NE_flags
, target_index
);
557 SET_NE_FLAGS (NE_base
, NE_flags
);
559 return rc
; /* perform the load? */
562 /* Record state for media exception: media_cr_not_aligned. */
564 frvbf_media_cr_not_aligned (SIM_CPU
*current_cpu
)
566 SIM_DESC sd
= CPU_STATE (current_cpu
);
568 /* On some machines this generates an illegal_instruction interrupt. */
569 switch (STATE_ARCHITECTURE (sd
)->mach
)
571 /* Note: there is a discrepancy between V2.2 of the FR400
572 instruction manual and the various FR4xx LSI specs. The former
573 claims that unaligned registers cause an mp_exception while the
574 latter say it's an illegal_instruction. The LSI specs appear
575 to be correct since MTT is fixed at 1. */
579 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
582 frv_set_mp_exception_registers (current_cpu
, MTT_CR_NOT_ALIGNED
, 0);
587 /* Record state for media exception: media_acc_not_aligned. */
589 frvbf_media_acc_not_aligned (SIM_CPU
*current_cpu
)
591 SIM_DESC sd
= CPU_STATE (current_cpu
);
593 /* On some machines this generates an illegal_instruction interrupt. */
594 switch (STATE_ARCHITECTURE (sd
)->mach
)
596 /* See comment in frvbf_cr_not_aligned(). */
600 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
603 frv_set_mp_exception_registers (current_cpu
, MTT_ACC_NOT_ALIGNED
, 0);
608 /* Record state for media exception: media_register_not_aligned. */
610 frvbf_media_register_not_aligned (SIM_CPU
*current_cpu
)
612 SIM_DESC sd
= CPU_STATE (current_cpu
);
614 /* On some machines this generates an illegal_instruction interrupt. */
615 switch (STATE_ARCHITECTURE (sd
)->mach
)
617 /* See comment in frvbf_cr_not_aligned(). */
621 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
624 frv_set_mp_exception_registers (current_cpu
, MTT_INVALID_FR
, 0);
629 /* Record state for media exception: media_overflow. */
631 frvbf_media_overflow (SIM_CPU
*current_cpu
, int sie
)
633 frv_set_mp_exception_registers (current_cpu
, MTT_OVERFLOW
, sie
);
636 /* Queue a division exception. */
638 frvbf_division_exception (SIM_CPU
*current_cpu
, enum frv_dtt dtt
,
639 int target_index
, int non_excepting
)
641 /* If there was an overflow and it is masked, then record it in
643 USI isr
= GET_ISR ();
644 if ((dtt
& FRV_DTT_OVERFLOW
) && GET_ISR_EDE (isr
))
646 dtt
&= ~FRV_DTT_OVERFLOW
;
650 if (dtt
!= FRV_DTT_NO_EXCEPTION
)
654 /* Non excepting instruction, simply set the NE flag for the target
657 GET_NE_FLAGS (NE_flags
, H_SPR_GNER0
);
658 SET_NE_FLAG (NE_flags
, target_index
);
659 SET_NE_FLAGS (H_SPR_GNER0
, NE_flags
);
662 frv_queue_division_exception_interrupt (current_cpu
, dtt
);
668 frvbf_check_recovering_store (
669 SIM_CPU
*current_cpu
, PCADDR address
, SI regno
, int size
, int is_float
672 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
675 CPU_RSTR_INVALIDATE(current_cpu
) = 0;
677 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
679 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
681 if (address
== GET_H_SPR (H_SPR_NEEAR0
+ reg_ix
))
683 SI nesr
= GET_NESR (reg_ix
);
684 int nesr_drn
= GET_NESR_DRN (nesr
);
685 BI nesr_fr
= GET_NESR_FR (nesr
);
688 /* Invalidate cache block containing this address.
689 If we need to count cycles, then the cache operation will be
690 initiated from the model profiling functions.
691 See frvbf_model_.... */
694 CPU_RSTR_INVALIDATE(current_cpu
) = 1;
695 CPU_LOAD_ADDRESS (current_cpu
) = address
;
698 frv_cache_invalidate (cache
, address
, 1/* flush */);
700 /* Copy the stored value to the register indicated by NESR.DRN. */
701 for (remain
= size
; remain
> 0; remain
-= 4)
706 value
= GET_H_FR (regno
);
708 value
= GET_H_GR (regno
);
723 sim_queue_fn_sf_write (current_cpu
, frvbf_h_fr_set
, nesr_drn
,
726 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, nesr_drn
,
732 break; /* Only consider the first matching register. */
734 } /* loop over active neear registers. */
738 frvbf_check_acc_range (SIM_CPU
*current_cpu
, SI regno
)
740 /* Only applicable to fr550 */
741 SIM_DESC sd
= CPU_STATE (current_cpu
);
742 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
745 /* On the fr550, media insns in slots 0 and 2 can only access
746 accumulators acc0-acc3. Insns in slots 1 and 3 can only access
747 accumulators acc4-acc7 */
748 switch (frv_current_fm_slot
)
753 return 1; /* all is ok */
758 return 1; /* all is ok */
762 /* The specified accumulator is out of range. Queue an illegal_instruction
764 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
769 frvbf_check_swap_address (SIM_CPU
*current_cpu
, SI address
)
771 /* Only applicable to fr550 */
772 SIM_DESC sd
= CPU_STATE (current_cpu
);
773 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
776 /* Adress must be aligned on a word boundary. */
778 frv_queue_data_access_exception_interrupt (current_cpu
);
782 clear_nesr_neear (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
786 /* Only implemented for full frv. */
787 SIM_DESC sd
= CPU_STATE (current_cpu
);
788 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_frv
)
791 /* Clear the appropriate NESR and NEEAR registers. */
792 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
794 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
797 /* The register is available, now check if it is active. */
798 nesr
= GET_NESR (reg_ix
);
799 if (GET_NESR_FR (nesr
) == is_float
)
801 if (target_index
< 0 || GET_NESR_DRN (nesr
) == target_index
)
803 SET_NESR (reg_ix
, 0);
804 SET_NEEAR (reg_ix
, 0);
812 SIM_CPU
*current_cpu
,
822 GET_NE_FLAGS (NE_flags
, NE_base
);
823 if (target_index
>= 0)
824 CLEAR_NE_FLAG (NE_flags
, target_index
);
832 SET_NE_FLAGS (NE_base
, NE_flags
);
835 /* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1
836 means to check for any register available. */
838 which_registers_available (
839 SIM_CPU
*current_cpu
, int *hi_available
, int *lo_available
, int is_float
843 frv_fr_registers_available (current_cpu
, hi_available
, lo_available
);
845 frv_gr_registers_available (current_cpu
, hi_available
, lo_available
);
849 frvbf_clear_ne_flags (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
856 FRV_REGISTER_CONTROL
*control
;
858 /* Check for availability of the target register(s). */
859 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
862 /* Check to make sure that the target register is available. */
863 if (! frv_check_register_access (current_cpu
, target_index
,
864 hi_available
, lo_available
))
867 /* Determine whether we're working with GR or FR registers. */
869 NE_base
= H_SPR_FNER0
;
871 NE_base
= H_SPR_GNER0
;
873 /* Always clear the appropriate NE flags. */
874 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
877 /* Clear the appropriate NESR and NEEAR registers. */
878 control
= CPU_REGISTER_CONTROL (current_cpu
);
879 if (control
->spr
[H_SPR_NECR
].implemented
)
882 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
))
883 clear_nesr_neear (current_cpu
, target_index
, is_float
);
888 frvbf_commit (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
897 FRV_REGISTER_CONTROL
*control
;
899 /* Check for availability of the target register(s). */
900 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
903 /* Check to make sure that the target register is available. */
904 if (! frv_check_register_access (current_cpu
, target_index
,
905 hi_available
, lo_available
))
908 /* Determine whether we're working with GR or FR registers. */
910 NE_base
= H_SPR_FNER0
;
912 NE_base
= H_SPR_GNER0
;
914 /* Determine whether a ne exception is pending. */
915 GET_NE_FLAGS (NE_flags
, NE_base
);
916 if (target_index
>= 0)
917 NE_flag
= GET_NE_FLAG (NE_flags
, target_index
);
921 hi_available
&& NE_flags
[0] != 0 || lo_available
&& NE_flags
[1] != 0;
924 /* Always clear the appropriate NE flags. */
925 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
928 control
= CPU_REGISTER_CONTROL (current_cpu
);
929 if (control
->spr
[H_SPR_NECR
].implemented
)
932 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
) && NE_flag
)
934 /* Clear the appropriate NESR and NEEAR registers. */
935 clear_nesr_neear (current_cpu
, target_index
, is_float
);
936 frv_queue_program_interrupt (current_cpu
, FRV_COMMIT_EXCEPTION
);
941 /* Generate the appropriate fp_exception(s) based on the given status code. */
943 frvbf_fpu_error (CGEN_FPU
* fpu
, int status
)
945 struct frv_fp_exception_info fp_info
= {
946 FSR_NO_EXCEPTION
, FTT_IEEE_754_EXCEPTION
950 (sim_fpu_status_invalid_snan
|
951 sim_fpu_status_invalid_qnan
|
952 sim_fpu_status_invalid_isi
|
953 sim_fpu_status_invalid_idi
|
954 sim_fpu_status_invalid_zdz
|
955 sim_fpu_status_invalid_imz
|
956 sim_fpu_status_invalid_cvi
|
957 sim_fpu_status_invalid_cmp
|
958 sim_fpu_status_invalid_sqrt
))
959 fp_info
.fsr_mask
|= FSR_INVALID_OPERATION
;
961 if (status
& sim_fpu_status_invalid_div0
)
962 fp_info
.fsr_mask
|= FSR_DIVISION_BY_ZERO
;
964 if (status
& sim_fpu_status_inexact
)
965 fp_info
.fsr_mask
|= FSR_INEXACT
;
967 if (status
& sim_fpu_status_overflow
)
968 fp_info
.fsr_mask
|= FSR_OVERFLOW
;
970 if (status
& sim_fpu_status_underflow
)
971 fp_info
.fsr_mask
|= FSR_UNDERFLOW
;
973 if (status
& sim_fpu_status_denorm
)
975 fp_info
.fsr_mask
|= FSR_DENORMAL_INPUT
;
976 fp_info
.ftt
= FTT_DENORMAL_INPUT
;
979 if (fp_info
.fsr_mask
!= FSR_NO_EXCEPTION
)
981 SIM_CPU
*current_cpu
= (SIM_CPU
*)fpu
->owner
;
982 frv_queue_fp_exception_interrupt (current_cpu
, & fp_info
);