[PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav...
[binutils-gdb.git] / sim / microblaze / microblaze.h
blobc22faafc02b40a422f47587d972430e3a643a184
1 #ifndef MICROBLAZE_H
2 #define MICROBLAZE_H
4 /* Copyright 2009-2019 Free Software Foundation, Inc.
6 This file is part of the Xilinx MicroBlaze simulator.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, see <http://www.gnu.org/licenses/>. */
21 #include "../../opcodes/microblaze-opcm.h"
23 #define GET_RD ((inst & RD_MASK) >> RD_LOW)
24 #define GET_RA ((inst & RA_MASK) >> RA_LOW)
25 #define GET_RB ((inst & RB_MASK) >> RB_LOW)
27 #define CPU cpu->microblaze_cpu
29 #define RD CPU.regs[rd]
30 #define RA CPU.regs[ra]
31 #define RB CPU.regs[rb]
32 /* #define IMM immword */
34 #define SA CPU.spregs[IMM & 0x1]
36 #define IMM_H CPU.imm_high
37 #define IMM_L ((inst & IMM_MASK) >> IMM_LOW)
39 #define IMM_ENABLE CPU.imm_enable
41 #define IMM (IMM_ENABLE ? \
42 (((uhalf)IMM_H << 16) | (uhalf)IMM_L) : \
43 (imm_unsigned ? \
44 (0xFFFF & IMM_L) : \
45 (IMM_L & 0x8000 ? \
46 (0xFFFF0000 | IMM_L) : \
47 (0x0000FFFF & IMM_L))))
49 #define PC CPU.spregs[0]
50 #define MSR CPU.spregs[1]
51 #define SP CPU.regs[29]
52 #define RETREG CPU.regs[3]
55 #define MEM_RD_BYTE(X) sim_core_read_1 (cpu, 0, read_map, X)
56 #define MEM_RD_HALF(X) sim_core_read_2 (cpu, 0, read_map, X)
57 #define MEM_RD_WORD(X) sim_core_read_4 (cpu, 0, read_map, X)
58 #define MEM_RD_UBYTE(X) (ubyte) MEM_RD_BYTE(X)
59 #define MEM_RD_UHALF(X) (uhalf) MEM_RD_HALF(X)
60 #define MEM_RD_UWORD(X) (uword) MEM_RD_WORD(X)
62 #define MEM_WR_BYTE(X, D) sim_core_write_1 (cpu, 0, write_map, X, D)
63 #define MEM_WR_HALF(X, D) sim_core_write_2 (cpu, 0, write_map, X, D)
64 #define MEM_WR_WORD(X, D) sim_core_write_4 (cpu, 0, write_map, X, D)
67 #define MICROBLAZE_SEXT8(X) ((char) X)
68 #define MICROBLAZE_SEXT16(X) ((short) X)
71 #define CARRY carry
72 #define C_rd ((MSR & 0x4) >> 2)
73 #define C_wr(D) MSR = (D ? MSR | 0x80000004 : MSR & 0x7FFFFFFB)
75 #define C_calc(X, Y, C) ((((uword)Y == MAX_WORD) && (C == 1)) ? \
76 1 : \
77 ((MAX_WORD - (uword)X) < ((uword)Y + C)))
79 #define BIP_MASK 0x00000008
80 #define CARRY_MASK 0x00000004
81 #define INTR_EN_MASK 0x00000002
82 #define BUSLOCK_MASK 0x00000001
84 #define DELAY_SLOT delay_slot_enable = 1
85 #define BRANCH branch_taken = 1
87 #define NUM_REGS 32
88 #define NUM_SPECIAL 2
89 #define INST_SIZE 4
91 #define MAX_WORD 0xFFFFFFFF
92 #define MICROBLAZE_HALT_INST 0xb8000000
94 typedef char byte;
95 typedef short half;
96 typedef int word;
97 typedef unsigned char ubyte;
98 typedef unsigned short uhalf;
99 typedef unsigned int uword;
101 #endif /* MICROBLAZE_H */