1 /* Decode header for or1k32bf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2019 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
25 #ifndef OR1K32BF_DECODE_H
26 #define OR1K32BF_DECODE_H
28 extern const IDESC
*or1k32bf_decode (SIM_CPU
*, IADDR
,
29 CGEN_INSN_WORD
, CGEN_INSN_WORD
,
31 extern void or1k32bf_init_idesc_table (SIM_CPU
*);
32 extern void or1k32bf_sem_init_idesc_table (SIM_CPU
*);
33 extern void or1k32bf_semf_init_idesc_table (SIM_CPU
*);
35 /* Enum declaration for instructions in cpu family or1k32bf. */
36 typedef enum or1k32bf_insn_type
{
37 OR1K32BF_INSN_X_INVALID
, OR1K32BF_INSN_X_AFTER
, OR1K32BF_INSN_X_BEFORE
, OR1K32BF_INSN_X_CTI_CHAIN
38 , OR1K32BF_INSN_X_CHAIN
, OR1K32BF_INSN_X_BEGIN
, OR1K32BF_INSN_L_J
, OR1K32BF_INSN_L_ADRP
39 , OR1K32BF_INSN_L_JAL
, OR1K32BF_INSN_L_JR
, OR1K32BF_INSN_L_JALR
, OR1K32BF_INSN_L_BNF
40 , OR1K32BF_INSN_L_BF
, OR1K32BF_INSN_L_TRAP
, OR1K32BF_INSN_L_SYS
, OR1K32BF_INSN_L_MSYNC
41 , OR1K32BF_INSN_L_PSYNC
, OR1K32BF_INSN_L_CSYNC
, OR1K32BF_INSN_L_RFE
, OR1K32BF_INSN_L_NOP_IMM
42 , OR1K32BF_INSN_L_MOVHI
, OR1K32BF_INSN_L_MACRC
, OR1K32BF_INSN_L_MFSPR
, OR1K32BF_INSN_L_MTSPR
43 , OR1K32BF_INSN_L_LWZ
, OR1K32BF_INSN_L_LWS
, OR1K32BF_INSN_L_LWA
, OR1K32BF_INSN_L_LBZ
44 , OR1K32BF_INSN_L_LBS
, OR1K32BF_INSN_L_LHZ
, OR1K32BF_INSN_L_LHS
, OR1K32BF_INSN_L_SW
45 , OR1K32BF_INSN_L_SB
, OR1K32BF_INSN_L_SH
, OR1K32BF_INSN_L_SWA
, OR1K32BF_INSN_L_SLL
46 , OR1K32BF_INSN_L_SLLI
, OR1K32BF_INSN_L_SRL
, OR1K32BF_INSN_L_SRLI
, OR1K32BF_INSN_L_SRA
47 , OR1K32BF_INSN_L_SRAI
, OR1K32BF_INSN_L_ROR
, OR1K32BF_INSN_L_RORI
, OR1K32BF_INSN_L_AND
48 , OR1K32BF_INSN_L_OR
, OR1K32BF_INSN_L_XOR
, OR1K32BF_INSN_L_ADD
, OR1K32BF_INSN_L_SUB
49 , OR1K32BF_INSN_L_ADDC
, OR1K32BF_INSN_L_MUL
, OR1K32BF_INSN_L_MULD
, OR1K32BF_INSN_L_MULU
50 , OR1K32BF_INSN_L_MULDU
, OR1K32BF_INSN_L_DIV
, OR1K32BF_INSN_L_DIVU
, OR1K32BF_INSN_L_FF1
51 , OR1K32BF_INSN_L_FL1
, OR1K32BF_INSN_L_ANDI
, OR1K32BF_INSN_L_ORI
, OR1K32BF_INSN_L_XORI
52 , OR1K32BF_INSN_L_ADDI
, OR1K32BF_INSN_L_ADDIC
, OR1K32BF_INSN_L_MULI
, OR1K32BF_INSN_L_EXTHS
53 , OR1K32BF_INSN_L_EXTBS
, OR1K32BF_INSN_L_EXTHZ
, OR1K32BF_INSN_L_EXTBZ
, OR1K32BF_INSN_L_EXTWS
54 , OR1K32BF_INSN_L_EXTWZ
, OR1K32BF_INSN_L_CMOV
, OR1K32BF_INSN_L_SFGTS
, OR1K32BF_INSN_L_SFGTSI
55 , OR1K32BF_INSN_L_SFGTU
, OR1K32BF_INSN_L_SFGTUI
, OR1K32BF_INSN_L_SFGES
, OR1K32BF_INSN_L_SFGESI
56 , OR1K32BF_INSN_L_SFGEU
, OR1K32BF_INSN_L_SFGEUI
, OR1K32BF_INSN_L_SFLTS
, OR1K32BF_INSN_L_SFLTSI
57 , OR1K32BF_INSN_L_SFLTU
, OR1K32BF_INSN_L_SFLTUI
, OR1K32BF_INSN_L_SFLES
, OR1K32BF_INSN_L_SFLESI
58 , OR1K32BF_INSN_L_SFLEU
, OR1K32BF_INSN_L_SFLEUI
, OR1K32BF_INSN_L_SFEQ
, OR1K32BF_INSN_L_SFEQI
59 , OR1K32BF_INSN_L_SFNE
, OR1K32BF_INSN_L_SFNEI
, OR1K32BF_INSN_L_MAC
, OR1K32BF_INSN_L_MACI
60 , OR1K32BF_INSN_L_MACU
, OR1K32BF_INSN_L_MSB
, OR1K32BF_INSN_L_MSBU
, OR1K32BF_INSN_L_CUST1
61 , OR1K32BF_INSN_L_CUST2
, OR1K32BF_INSN_L_CUST3
, OR1K32BF_INSN_L_CUST4
, OR1K32BF_INSN_L_CUST5
62 , OR1K32BF_INSN_L_CUST6
, OR1K32BF_INSN_L_CUST7
, OR1K32BF_INSN_L_CUST8
, OR1K32BF_INSN_LF_ADD_S
63 , OR1K32BF_INSN_LF_SUB_S
, OR1K32BF_INSN_LF_MUL_S
, OR1K32BF_INSN_LF_DIV_S
, OR1K32BF_INSN_LF_REM_S
64 , OR1K32BF_INSN_LF_ITOF_S
, OR1K32BF_INSN_LF_FTOI_S
, OR1K32BF_INSN_LF_EQ_S
, OR1K32BF_INSN_LF_NE_S
65 , OR1K32BF_INSN_LF_GE_S
, OR1K32BF_INSN_LF_GT_S
, OR1K32BF_INSN_LF_LT_S
, OR1K32BF_INSN_LF_LE_S
66 , OR1K32BF_INSN_LF_MADD_S
, OR1K32BF_INSN_LF_CUST1_S
, OR1K32BF_INSN__MAX
69 /* Enum declaration for semantic formats in cpu family or1k32bf. */
70 typedef enum or1k32bf_sfmt_type
{
71 OR1K32BF_SFMT_EMPTY
, OR1K32BF_SFMT_L_J
, OR1K32BF_SFMT_L_ADRP
, OR1K32BF_SFMT_L_JAL
72 , OR1K32BF_SFMT_L_JR
, OR1K32BF_SFMT_L_JALR
, OR1K32BF_SFMT_L_BNF
, OR1K32BF_SFMT_L_TRAP
73 , OR1K32BF_SFMT_L_MSYNC
, OR1K32BF_SFMT_L_NOP_IMM
, OR1K32BF_SFMT_L_MOVHI
, OR1K32BF_SFMT_L_MACRC
74 , OR1K32BF_SFMT_L_MFSPR
, OR1K32BF_SFMT_L_MTSPR
, OR1K32BF_SFMT_L_LWZ
, OR1K32BF_SFMT_L_LWS
75 , OR1K32BF_SFMT_L_LWA
, OR1K32BF_SFMT_L_LBZ
, OR1K32BF_SFMT_L_LBS
, OR1K32BF_SFMT_L_LHZ
76 , OR1K32BF_SFMT_L_LHS
, OR1K32BF_SFMT_L_SW
, OR1K32BF_SFMT_L_SB
, OR1K32BF_SFMT_L_SH
77 , OR1K32BF_SFMT_L_SWA
, OR1K32BF_SFMT_L_SLL
, OR1K32BF_SFMT_L_SLLI
, OR1K32BF_SFMT_L_AND
78 , OR1K32BF_SFMT_L_ADD
, OR1K32BF_SFMT_L_ADDC
, OR1K32BF_SFMT_L_MUL
, OR1K32BF_SFMT_L_MULD
79 , OR1K32BF_SFMT_L_MULU
, OR1K32BF_SFMT_L_DIV
, OR1K32BF_SFMT_L_DIVU
, OR1K32BF_SFMT_L_FF1
80 , OR1K32BF_SFMT_L_XORI
, OR1K32BF_SFMT_L_ADDI
, OR1K32BF_SFMT_L_ADDIC
, OR1K32BF_SFMT_L_MULI
81 , OR1K32BF_SFMT_L_EXTHS
, OR1K32BF_SFMT_L_CMOV
, OR1K32BF_SFMT_L_SFGTS
, OR1K32BF_SFMT_L_SFGTSI
82 , OR1K32BF_SFMT_L_MAC
, OR1K32BF_SFMT_L_MACI
, OR1K32BF_SFMT_L_MACU
, OR1K32BF_SFMT_LF_ADD_S
83 , OR1K32BF_SFMT_LF_ITOF_S
, OR1K32BF_SFMT_LF_FTOI_S
, OR1K32BF_SFMT_LF_EQ_S
, OR1K32BF_SFMT_LF_MADD_S
86 /* Function unit handlers (user written). */
88 extern int or1k32bf_model_or1200_u_exec (SIM_CPU
*, const IDESC
*, int /*unit_num*/, int /*referenced*/);
89 extern int or1k32bf_model_or1200nd_u_exec (SIM_CPU
*, const IDESC
*, int /*unit_num*/, int /*referenced*/);
91 /* Profiling before/after handlers (user written) */
93 extern void or1k32bf_model_insn_before (SIM_CPU
*, int /*first_p*/);
94 extern void or1k32bf_model_insn_after (SIM_CPU
*, int /*last_p*/, int /*cycles*/);
96 #endif /* OR1K32BF_DECODE_H */