sim/or1k/sim-if.c

   1 /* Main simulator entry points specific to the OR1K.
   2    Copyright (C) 2017-2019 Free Software Foundation, Inc.
   3
   4    This file is part of GDB, the GNU debugger.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "sim-main.h"
  20 #include "sim-options.h"
  21 #include "libiberty.h"
  22 #include "bfd.h"
  23
  24 #ifdef HAVE_STRING_H
  25 #include <string.h>
  26 #else
  27 #ifdef HAVE_STRINGS_H
  28 #include <strings.h>
  29 #endif
  30 #endif
  31 #ifdef HAVE_STDLIB_H
  32 #include <stdlib.h>
  33 #endif
  34
  35 static void free_state (SIM_DESC);
  36 \f
  37
  38 /* Cover function of sim_state_free to free the cpu buffers as well.  */
  39
  40 static void
  41 free_state (SIM_DESC sd)
  42 {
  43   if (STATE_MODULES (sd) != NULL)
  44     sim_module_uninstall (sd);
  45   sim_cpu_free_all (sd);
  46   sim_state_free (sd);
  47 }
  48
  49 /* Defaults for user passed arguments.  */
  50 static const USI or1k_default_vr = 0x0;
  51 static const USI or1k_default_upr = 0x0
  52   | SPR_FIELD_MASK_SYS_UPR_UP;
  53 static const USI or1k_default_cpucfgr = 0x0
  54   | SPR_FIELD_MASK_SYS_CPUCFGR_OB32S
  55   | SPR_FIELD_MASK_SYS_CPUCFGR_OF32S;
  56
  57 static UWI or1k_upr;
  58 static UWI or1k_vr;
  59 static UWI or1k_cpucfgr;
  60
  61 enum
  62 {
  63   OPTION_OR1K_VR,
  64   OPTION_OR1K_UPR,
  65   OPTION_OR1K_CPUCFGR = OPTION_START,
  66 };
  67
  68 /* Setup help and handlers for the user defined arguments.  */
  69 DECLARE_OPTION_HANDLER (or1k_option_handler);
  70
  71 static const OPTION or1k_options[] = {
  72   {{"or1k-cpucfgr", required_argument, NULL, OPTION_OR1K_CPUCFGR},
  73    '\0', "INTEGER|default", "Set simulator CPUCFGR value",
  74    or1k_option_handler},
  75   {{"or1k-vr", required_argument, NULL, OPTION_OR1K_VR},
  76    '\0', "INTEGER|default", "Set simulator VR value",
  77    or1k_option_handler},
  78   {{"or1k-upr", required_argument, NULL, OPTION_OR1K_UPR},
  79    '\0', "INTEGER|default", "Set simulator UPR value",
  80    or1k_option_handler},
  81   {{NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL}
  82 };
  83
  84 /* Handler for parsing user defined arguments.  Currently we support
  85    configuring some of the CPU implementation specific registers including
  86    the Version Register (VR), the Unit Present Register (UPR) and the CPU
  87    Configuration Register (CPUCFGR).  */
  88 SIM_RC
  89 or1k_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
  90                      int is_command)
  91 {
  92   switch (opt)
  93     {
  94     case OPTION_OR1K_VR:
  95       if (strcmp ("default", arg) == 0)
  96         or1k_vr = or1k_default_vr;
  97       else
  98         {
  99           unsigned long long n;
 100           char *endptr;
 101
 102           n = strtoull (arg, &endptr, 0);
 103           if (*arg != '\0' && *endptr == '\0')
 104             or1k_vr = n;
 105           else
 106             return SIM_RC_FAIL;
 107         }
 108       return SIM_RC_OK;
 109
 110     case OPTION_OR1K_UPR:
 111       if (strcmp ("default", arg) == 0)
 112         or1k_upr = or1k_default_upr;
 113       else
 114         {
 115           unsigned long long n;
 116           char *endptr;
 117
 118           n = strtoull (arg, &endptr, 0);
 119           if (*arg != '\0' && *endptr == '\0')
 120             or1k_upr = n;
 121           else
 122             {
 123               sim_io_eprintf
 124                 (sd, "invalid argument to option --or1k-upr: `%s'\n", arg);
 125               return SIM_RC_FAIL;
 126             }
 127         }
 128       return SIM_RC_OK;
 129
 130     case OPTION_OR1K_CPUCFGR:
 131       if (strcmp ("default", arg) == 0)
 132         or1k_cpucfgr = or1k_default_cpucfgr;
 133       else
 134         {
 135           unsigned long long n;
 136           char *endptr;
 137
 138           n = strtoull (arg, &endptr, 0);
 139           if (*arg != '\0' && *endptr == '\0')
 140             or1k_cpucfgr = n;
 141           else
 142             {
 143               sim_io_eprintf
 144                 (sd, "invalid argument to option --or1k-cpucfgr: `%s'\n", arg);
 145               return SIM_RC_FAIL;
 146             }
 147         }
 148       return SIM_RC_OK;
 149
 150     default:
 151       sim_io_eprintf (sd, "Unknown or1k option %d\n", opt);
 152       return SIM_RC_FAIL;
 153     }
 154
 155   return SIM_RC_FAIL;
 156 }
 157
 158 /* Create an instance of the simulator.  */
 159
 160 SIM_DESC
 161 sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
 162           char * const *argv)
 163 {
 164   SIM_DESC sd = sim_state_alloc (kind, callback);
 165   char c;
 166   int i;
 167
 168   /* The cpu data is kept in a separately allocated chunk of memory.  */
 169   if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
 170     {
 171       free_state (sd);
 172       return 0;
 173     }
 174
 175   /* Perform initial sim setups.  */
 176   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
 177     {
 178       free_state (sd);
 179       return 0;
 180     }
 181
 182   or1k_upr = or1k_default_upr;
 183   or1k_vr = or1k_default_vr;
 184   or1k_cpucfgr = or1k_default_cpucfgr;
 185   sim_add_option_table (sd, NULL, or1k_options);
 186
 187   /* Parse the user passed arguments.  */
 188   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 189     {
 190       free_state (sd);
 191       return 0;
 192     }
 193
 194   /* Allocate core managed memory if none specified by user.
 195      Use address 4 here in case the user wanted address 0 unmapped.  */
 196   if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
 197     {
 198       sim_do_commandf (sd, "memory region 0,0x%x", OR1K_DEFAULT_MEM_SIZE);
 199     }
 200
 201   /* Check for/establish the reference program image.  */
 202   if (sim_analyze_program (sd,
 203                            (STATE_PROG_ARGV (sd) != NULL
 204                             ? *STATE_PROG_ARGV (sd)
 205                             : NULL), abfd) != SIM_RC_OK)
 206     {
 207       free_state (sd);
 208       return 0;
 209     }
 210
 211   /* Establish any remaining configuration options.  */
 212   if (sim_config (sd) != SIM_RC_OK)
 213     {
 214       free_state (sd);
 215       return 0;
 216     }
 217
 218   if (sim_post_argv_init (sd) != SIM_RC_OK)
 219     {
 220       free_state (sd);
 221       return 0;
 222     }
 223
 224   /* Make sure delay slot mode is consistent with the loaded binary.  */
 225   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_or1knd)
 226     or1k_cpucfgr |= SPR_FIELD_MASK_SYS_CPUCFGR_ND;
 227   else
 228     or1k_cpucfgr &= ~SPR_FIELD_MASK_SYS_CPUCFGR_ND;
 229
 230   /* Open a copy of the cpu descriptor table and initialize the
 231      disassembler.  These initialization functions are generated by CGEN
 232      using the binutils scheme cpu description files.  */
 233   {
 234     CGEN_CPU_DESC cd =
 235       or1k_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
 236                             CGEN_ENDIAN_BIG);
 237     for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 238       {
 239         SIM_CPU *cpu = STATE_CPU (sd, i);
 240         CPU_CPU_DESC (cpu) = cd;
 241         CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
 242       }
 243     or1k_cgen_init_dis (cd);
 244   }
 245
 246   /* Initialize various cgen things not done by common framework.
 247      Must be done after or1k_cgen_cpu_open.  */
 248   cgen_init (sd);
 249
 250   /* Do some final OpenRISC sim specific initializations.  */
 251   for (c = 0; c < MAX_NR_PROCESSORS; ++c)
 252     {
 253       SIM_CPU *cpu = STATE_CPU (sd, i);
 254       /* Only needed for profiling, but the structure member is small.  */
 255       memset (CPU_OR1K_MISC_PROFILE (cpu), 0,
 256               sizeof (*CPU_OR1K_MISC_PROFILE (cpu)));
 257
 258       or1k_cpu_init (sd, cpu, or1k_vr, or1k_upr, or1k_cpucfgr);
 259     }
 260
 261   return sd;
 262 }
 263 \f
 264
 265 SIM_RC
 266 sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
 267                      char * const *argv, char * const *envp)
 268 {
 269   SIM_CPU *current_cpu = STATE_CPU (sd, 0);
 270   SIM_ADDR addr;
 271
 272   if (abfd != NULL)
 273     addr = bfd_get_start_address (abfd);
 274   else
 275     addr = 0;
 276   sim_pc_set (current_cpu, addr);
 277
 278   return SIM_RC_OK;
 279 }