sim/or1k/traps.c

   1 /* OpenRISC exception, interrupts, syscall and trap support
   2    Copyright (C) 2017-2019 Free Software Foundation, Inc.
   3
   4    This file is part of GDB, the GNU debugger.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #define WANT_CPU_OR1K32BF
  20 #define WANT_CPU
  21
  22 #include "sim-main.h"
  23 #include "cgen-ops.h"
  24
  25 /* Implement the sim invalid instruction function.  This will set the error
  26    effective address to that of the invalid instruction then call the
  27    exception handler.  */
  28
  29 SEM_PC
  30 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
  31 {
  32   SET_H_SYS_EEAR0 (cia);
  33
  34 #ifdef WANT_CPU_OR1K32BF
  35   or1k32bf_exception (current_cpu, cia, EXCEPT_ILLEGAL);
  36 #endif
  37
  38   return vpc;
  39 }
  40
  41 /* Generate the appropriate OpenRISC fpu exception based on the status code from
  42    the sim fpu.  */
  43 void
  44 or1k32bf_fpu_error (CGEN_FPU* fpu, int status)
  45 {
  46   SIM_CPU *current_cpu = (SIM_CPU *)fpu->owner;
  47
  48   /* If floating point exceptions are enabled.  */
  49   if (GET_H_SYS_FPCSR_FPEE() != 0)
  50     {
  51       /* Set all of the status flag bits.  */
  52       if (status
  53           & (sim_fpu_status_invalid_snan
  54              | sim_fpu_status_invalid_qnan
  55              | sim_fpu_status_invalid_isi
  56              | sim_fpu_status_invalid_idi
  57              | sim_fpu_status_invalid_zdz
  58              | sim_fpu_status_invalid_imz
  59              | sim_fpu_status_invalid_cvi
  60              | sim_fpu_status_invalid_cmp
  61              | sim_fpu_status_invalid_sqrt))
  62         SET_H_SYS_FPCSR_IVF (1);
  63
  64       if (status & sim_fpu_status_invalid_snan)
  65         SET_H_SYS_FPCSR_SNF (1);
  66
  67       if (status & sim_fpu_status_invalid_qnan)
  68         SET_H_SYS_FPCSR_QNF (1);
  69
  70       if (status & sim_fpu_status_overflow)
  71         SET_H_SYS_FPCSR_OVF (1);
  72
  73       if (status & sim_fpu_status_underflow)
  74         SET_H_SYS_FPCSR_UNF (1);
  75
  76       if (status
  77           & (sim_fpu_status_invalid_isi
  78              | sim_fpu_status_invalid_idi))
  79         SET_H_SYS_FPCSR_INF (1);
  80
  81       if (status & sim_fpu_status_invalid_div0)
  82         SET_H_SYS_FPCSR_DZF (1);
  83
  84       if (status & sim_fpu_status_inexact)
  85         SET_H_SYS_FPCSR_IXF (1);
  86
  87       /* If any of the exception bits were actually set.  */
  88       if (GET_H_SYS_FPCSR()
  89           & (SPR_FIELD_MASK_SYS_FPCSR_IVF
  90              | SPR_FIELD_MASK_SYS_FPCSR_SNF
  91              | SPR_FIELD_MASK_SYS_FPCSR_QNF
  92              | SPR_FIELD_MASK_SYS_FPCSR_OVF
  93              | SPR_FIELD_MASK_SYS_FPCSR_UNF
  94              | SPR_FIELD_MASK_SYS_FPCSR_INF
  95              | SPR_FIELD_MASK_SYS_FPCSR_DZF
  96              | SPR_FIELD_MASK_SYS_FPCSR_IXF))
  97         {
  98           SIM_DESC sd = CPU_STATE (current_cpu);
  99
 100           /* If the sim is running in fast mode, i.e. not profiling,
 101              per-instruction callbacks are not triggered which would allow
 102              us to track the PC.  This means we cannot track which
 103              instruction caused the FPU error.  */
 104           if (STATE_RUN_FAST_P (sd) == 1)
 105             sim_io_eprintf
 106               (sd, "WARNING: ignoring fpu error caught in fast mode.\n");
 107           else
 108             or1k32bf_exception (current_cpu, GET_H_SYS_PPC (), EXCEPT_FPE);
 109         }
 110     }
 111 }
 112
 113
 114 /* Implement the OpenRISC exception function.  This is mostly used by the
 115    CGEN generated files.  For example, this is used when handling a
 116    overflow exception during a multiplication instruction. */
 117
 118 void
 119 or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
 120 {
 121   SIM_DESC sd = CPU_STATE (current_cpu);
 122
 123   if (exnum == EXCEPT_TRAP)
 124     {
 125       /* Trap, used for breakpoints, sends control back to gdb breakpoint
 126          handling.  */
 127       sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
 128     }
 129   else
 130     {
 131
 132       /* Calculate the exception program counter.  */
 133       switch (exnum)
 134         {
 135         case EXCEPT_RESET:
 136           break;
 137
 138         case EXCEPT_FPE:
 139         case EXCEPT_SYSCALL:
 140           SET_H_SYS_EPCR0 (pc + 4 - (current_cpu->delay_slot ? 4 : 0));
 141           break;
 142
 143         case EXCEPT_BUSERR:
 144         case EXCEPT_ALIGN:
 145         case EXCEPT_ILLEGAL:
 146         case EXCEPT_RANGE:
 147           SET_H_SYS_EPCR0 (pc - (current_cpu->delay_slot ? 4 : 0));
 148           break;
 149
 150         default:
 151           sim_io_error (sd, "unexpected exception 0x%x raised at PC 0x%08x",
 152                         exnum, pc);
 153           break;
 154         }
 155
 156       /* Store the current SR into ESR0.  */
 157       SET_H_SYS_ESR0 (GET_H_SYS_SR ());
 158
 159       /* Indicate in SR if the failed instruction is in delay slot or not.  */
 160       SET_H_SYS_SR_DSX (current_cpu->delay_slot);
 161
 162       current_cpu->next_delay_slot = 0;
 163
 164       /* Jump program counter into handler.  */
 165       IADDR handler_pc =
 166         (GET_H_SYS_SR_EPH ()? 0xf0000000 : 0x00000000) + (exnum << 8);
 167
 168       sim_engine_restart (sd, current_cpu, NULL, handler_pc);
 169     }
 170 }
 171
 172 /* Implement the return from exception instruction.  This is used to return
 173    the CPU to its previous state from within an exception handler.  */
 174
 175 void
 176 or1k32bf_rfe (sim_cpu *current_cpu)
 177 {
 178   SET_H_SYS_SR (GET_H_SYS_ESR0 ());
 179   SET_H_SYS_SR_FO (1);
 180
 181   current_cpu->next_delay_slot = 0;
 182
 183   sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
 184                       GET_H_SYS_EPCR0 ());
 185 }
 186
 187 /* Implement the move from SPR instruction.  This is used to read from the
 188    CPU's special purpose registers.  */
 189
 190 USI
 191 or1k32bf_mfspr (sim_cpu *current_cpu, USI addr)
 192 {
 193   SIM_DESC sd = CPU_STATE (current_cpu);
 194
 195   if (!GET_H_SYS_SR_SM () && !GET_H_SYS_SR_SUMRA ())
 196     {
 197       sim_io_eprintf (sd, "WARNING: l.mfspr in user mode (SR 0x%x)\n",
 198                       GET_H_SYS_SR ());
 199       return 0;
 200     }
 201
 202   if (addr >= NUM_SPR)
 203     goto bad_address;
 204
 205   SI val = GET_H_SPR (addr);
 206
 207   switch (addr)
 208     {
 209
 210     case SPR_ADDR (SYS, VR):
 211     case SPR_ADDR (SYS, UPR):
 212     case SPR_ADDR (SYS, CPUCFGR):
 213     case SPR_ADDR (SYS, SR):
 214     case SPR_ADDR (SYS, PPC):
 215     case SPR_ADDR (SYS, FPCSR):
 216     case SPR_ADDR (SYS, EPCR0):
 217     case SPR_ADDR (MAC, MACLO):
 218     case SPR_ADDR (MAC, MACHI):
 219       break;
 220
 221     default:
 222       if (addr < SPR_ADDR (SYS, GPR0) || addr > SPR_ADDR (SYS, GPR511))
 223         goto bad_address;
 224       break;
 225
 226     }
 227
 228   return val;
 229
 230 bad_address:
 231   sim_io_eprintf (sd, "WARNING: l.mfspr with invalid SPR address 0x%x\n", addr);
 232   return 0;
 233
 234 }
 235
 236 /* Implement the move to SPR instruction.  This is used to write too the
 237    CPU's special purpose registers.  */
 238
 239 void
 240 or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val)
 241 {
 242   SIM_DESC sd = CPU_STATE (current_cpu);
 243
 244   if (!GET_H_SYS_SR_SM () && !GET_H_SYS_SR_SUMRA ())
 245     {
 246       sim_io_eprintf
 247         (sd, "WARNING: l.mtspr with address 0x%x in user mode (SR 0x%x)\n",
 248          addr, GET_H_SYS_SR ());
 249       return;
 250     }
 251
 252   if (addr >= NUM_SPR)
 253     goto bad_address;
 254
 255   switch (addr)
 256     {
 257
 258     case SPR_ADDR (SYS, FPCSR):
 259     case SPR_ADDR (SYS, EPCR0):
 260     case SPR_ADDR (SYS, ESR0):
 261     case SPR_ADDR (MAC, MACHI):
 262     case SPR_ADDR (MAC, MACLO):
 263       SET_H_SPR (addr, val);
 264       break;
 265
 266     case SPR_ADDR (SYS, SR):
 267       SET_H_SPR (addr, val);
 268       SET_H_SYS_SR_FO (1);
 269       break;
 270
 271     case SPR_ADDR (SYS, NPC):
 272       current_cpu->next_delay_slot = 0;
 273
 274       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, val);
 275       break;
 276
 277     case SPR_ADDR (TICK, TTMR):
 278       /* Allow some registers to be silently cleared.  */
 279       if (val != 0)
 280         sim_io_eprintf
 281           (sd, "WARNING: l.mtspr to SPR address 0x%x with invalid value 0x%x\n",
 282            addr, val);
 283       break;
 284
 285     default:
 286       if (addr >= SPR_ADDR (SYS, GPR0) && addr <= SPR_ADDR (SYS, GPR511))
 287         SET_H_SPR (addr, val);
 288       else
 289         goto bad_address;
 290       break;
 291
 292     }
 293
 294   return;
 295
 296 bad_address:
 297   sim_io_eprintf (sd, "WARNING: l.mtspr with invalid SPR address 0x%x\n", addr);
 298
 299 }