sim/rx/cpu.h

   1 /* cpu.h --- declarations for the RX core.
   2
   3 Copyright (C) 2005-2019 Free Software Foundation, Inc.
   4 Contributed by Red Hat, Inc.
   5
   6 This file is part of the GNU simulators.
   7
   8 This program is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3 of the License, or
  11 (at your option) any later version.
  12
  13 This program is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include <stdint.h>
  22 #include <setjmp.h>
  23
  24 extern int verbose;
  25 extern int trace;
  26 extern int enable_counting;
  27
  28 typedef uint8_t QI;
  29 typedef uint16_t HI;
  30 typedef uint32_t SI;
  31 typedef uint64_t DI;
  32
  33 extern int rx_in_gdb;
  34 extern int rx_big_endian;
  35
  36 typedef struct
  37 {
  38   SI r[16];
  39
  40   SI r_psw;
  41   SI r_pc;
  42   SI r_usp;
  43   SI r_fpsw;
  44   SI r__reserved_cr_4;
  45   SI r__reserved_cr_5;
  46   SI r__reserved_cr_6;
  47   SI r__reserved_cr_7;
  48
  49   SI r_bpsw;
  50   SI r_bpc;
  51   SI r_isp;
  52   SI r_fintv;
  53   SI r_intb;
  54   SI r__reserved_cr_13;
  55   SI r__reserved_cr_14;
  56   SI r__reserved_cr_15;
  57
  58   SI r__reserved_cr_16;
  59   SI r__reserved_cr_17;
  60   SI r__reserved_cr_18;
  61   SI r__reserved_cr_19;
  62   SI r__reserved_cr_20;
  63   SI r__reserved_cr_21;
  64   SI r__reserved_cr_22;
  65   SI r__reserved_cr_23;
  66
  67   SI r__reserved_cr_24;
  68   SI r__reserved_cr_25;
  69   SI r__reserved_cr_26;
  70   SI r__reserved_cr_27;
  71   SI r__reserved_cr_28;
  72   SI r__reserved_cr_29;
  73   SI r__reserved_cr_30;
  74   SI r__reserved_cr_31;
  75
  76   SI r_temp;
  77
  78   DI r_acc;
  79
  80 #ifdef CYCLE_ACCURATE
  81   /* If set, RTS/RTSD take 2 fewer cycles.  */
  82   char fast_return;
  83   SI link_register;
  84
  85   unsigned long long cycle_count;
  86   /* Bits saying what kind of memory operands the previous insn had.  */
  87   int m2m;
  88   /* Target register for load. */
  89   int rt;
  90 #endif
  91 } regs_type;
  92
  93 #define M2M_SRC         0x01
  94 #define M2M_DST         0x02
  95 #define M2M_BOTH        0x03
  96
  97 #define sp      0
  98 #define psw     16
  99 #define pc      17
 100 #define usp     18
 101 #define fpsw    19
 102
 103 #define bpsw    24
 104 #define bpc     25
 105 #define isp     26
 106 #define fintv   27
 107 #define intb    28
 108
 109 #define r_temp_idx 48
 110 #define acc64   49
 111 #define acchi   50
 112 #define accmi   51
 113 #define acclo   52
 114
 115 extern regs_type regs;
 116
 117 #define FLAGBIT_C       0x00000001
 118 #define FLAGBIT_Z       0x00000002
 119 #define FLAGBIT_S       0x00000004
 120 #define FLAGBIT_O       0x00000008
 121 #define FLAGBIT_I       0x00010000
 122 #define FLAGBIT_U       0x00020000
 123 #define FLAGBIT_PM      0x00100000
 124 #define FLAGBITS_IPL    0x0f000000
 125 #define FLAGSHIFT_IPL   24
 126
 127 #define FPSWBITS_RM     0x00000003
 128 #define FPSWBITS_CV     0x00000004 /* invalid operation */
 129 #define FPSWBITS_CO     0x00000008 /* overflow */
 130 #define FPSWBITS_CZ     0x00000010 /* divide-by-zero */
 131 #define FPSWBITS_CU     0x00000020 /* underflow */
 132 #define FPSWBITS_CX     0x00000040 /* inexact */
 133 #define FPSWBITS_CE     0x00000080 /* unimplemented processing */
 134 #define FPSWBITS_CMASK  0x000000fc /* all the above */
 135 #define FPSWBITS_DN     0x00000100
 136 #define FPSW_CESH       8
 137 #define FPSWBITS_EV     0x00000400
 138 #define FPSWBITS_EO     0x00000800
 139 #define FPSWBITS_EZ     0x00001000
 140 #define FPSWBITS_EU     0x00002000
 141 #define FPSWBITS_EX     0x00004000
 142 #define FPSW_EFSH       16
 143 #define FPSW_CFSH       24
 144 #define FPSWBITS_FV     0x04000000
 145 #define FPSWBITS_FO     0x08000000
 146 #define FPSWBITS_FZ     0x10000000
 147 #define FPSWBITS_FU     0x20000000
 148 #define FPSWBITS_FX     0x40000000
 149 #define FPSWBITS_FSUM   0x80000000
 150 #define FPSWBITS_FMASK  0x7c000000
 151 #define FPSWBITS_CLEAR  0xffffff03 /* masked at start of any FP opcode */
 152
 153 #define FPRM_NEAREST    0
 154 #define FPRM_ZERO       1
 155 #define FPRM_PINF       2
 156 #define FPRM_NINF       3
 157
 158 extern char *reg_names[];
 159
 160 extern int rx_flagmask;
 161 extern int rx_flagand;
 162 extern int rx_flagor;
 163
 164 extern unsigned int b2mask[];
 165 extern unsigned int b2signbit[];
 166 extern int b2maxsigned[];
 167 extern int b2minsigned[];
 168
 169 void init_regs (void);
 170 void stack_heap_stats (void);
 171 void set_pointer_width (int bytes);
 172 unsigned int get_reg (int id);
 173 unsigned long long get_reg64 (int id);
 174 void put_reg (int id, unsigned int value);
 175 void put_reg64 (int id, unsigned long long value);
 176
 177 void set_flags (int mask, int newbits);
 178 void set_oszc (long long value, int bytes, int c);
 179 void set_szc (long long value, int bytes, int c);
 180 void set_osz (long long value, int bytes);
 181 void set_sz (long long value, int bytes);
 182 void set_zc (int z, int c);
 183 void set_c (int c);
 184
 185 const char *bits (int v, int b);
 186
 187 int condition_true (int cond_id);
 188
 189 #define FLAG(f) ((regs.r_psw & f) ? 1 : 0)
 190 #define FLAG_C  FLAG(FLAGBIT_C)
 191 #define FLAG_D  FLAG(FLAGBIT_D)
 192 #define FLAG_Z  FLAG(FLAGBIT_Z)
 193 #define FLAG_S  FLAG(FLAGBIT_S)
 194 #define FLAG_B  FLAG(FLAGBIT_B)
 195 #define FLAG_O  FLAG(FLAGBIT_O)
 196 #define FLAG_I  FLAG(FLAGBIT_I)
 197 #define FLAG_U  FLAG(FLAGBIT_U)
 198 #define FLAG_PM FLAG(FLAGBIT_PM)
 199
 200 /* Instruction step return codes.
 201    Suppose one of the decode_* functions below returns a value R:
 202    - If RX_STEPPED (R), then the single-step completed normally.
 203    - If RX_HIT_BREAK (R), then the program hit a breakpoint.
 204    - If RX_EXITED (R), then the program has done an 'exit' system
 205      call, and the exit code is RX_EXIT_STATUS (R).
 206    - If RX_STOPPED (R), then a signal (number RX_STOP_SIG (R)) was
 207      generated.
 208
 209    For building step return codes:
 210    - RX_MAKE_STEPPED is the return code for finishing a normal step.
 211    - RX_MAKE_HIT_BREAK is the return code for hitting a breakpoint.
 212    - RX_MAKE_EXITED (C) is the return code for exiting with status C.
 213    - RX_MAKE_STOPPED (S) is the return code for stopping on signal S.  */
 214 #define RX_MAKE_STEPPED()   (1)
 215 #define RX_MAKE_HIT_BREAK() (2)
 216 #define RX_MAKE_EXITED(c)   (((int) (c) << 8) + 3)
 217 #define RX_MAKE_STOPPED(s)  (((int) (s) << 8) + 4)
 218
 219 #define RX_STEPPED(r)       ((r) == RX_MAKE_STEPPED ())
 220 #define RX_HIT_BREAK(r)     ((r) == RX_MAKE_HIT_BREAK ())
 221 #define RX_EXITED(r)        (((r) & 0xff) == 3)
 222 #define RX_EXIT_STATUS(r)   ((r) >> 8)
 223 #define RX_STOPPED(r)       (((r) & 0xff) == 4)
 224 #define RX_STOP_SIG(r)      ((r) >> 8)
 225
 226 /* The step result for the current step.  Global to allow
 227    communication between the stepping function and the system
 228    calls.  */
 229 extern int step_result;
 230
 231 extern unsigned int rx_cycles;
 232
 233 /* Used to detect heap/stack collisions.  */
 234 extern unsigned int heaptop;
 235 extern unsigned int heapbottom;
 236
 237 extern int decode_opcode (void);
 238 extern void reset_decoder (void);
 239 extern void reset_pipeline_stats (void);
 240 extern void halt_pipeline_stats (void);
 241 extern void pipeline_stats (void);
 242
 243 extern void trace_register_changes ();
 244 extern void generate_access_exception (void);
 245 extern jmp_buf decode_jmp_buf;